coreboot-gerrit January 2020

coreboot-gerrit@coreboot.org

1 participants
1869 discussions

Change in coreboot[master]: HP sandy/ivy desktops: Fix Kconfig symbol names
by Angel Pons (Code Review) 10 Jan '20

10 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38083 ) Change subject: HP sandy/ivy desktops: Fix Kconfig symbol names ...................................................................... HP sandy/ivy desktops: Fix Kconfig symbol names hp/z220_sff_workstation was using BOARD_HP_COMPAQ_8200_ELITE_SFF_PC, and hp/compaq_8200_elite was using a very long name. Fix that. Change-Id: I434cde42c7b9f30f8de77b96bc924aa298bad921 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/hp/compaq_8200_elite_sff/Kconfig M src/mainboard/hp/compaq_8200_elite_sff/Kconfig.name M src/mainboard/hp/z220_sff_workstation/Kconfig M src/mainboard/hp/z220_sff_workstation/Kconfig.name 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/38083/1 diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig index 42efd4a..e3b2ebd 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig +++ b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig @@ -1,4 +1,4 @@ -if BOARD_HEWLETT_PACKARD_HP_COMPAQ_8200_ELITE_SFF_PC +if BOARD_HP_COMPAQ_8200_ELITE_SFF_PC config BOARD_SPECIFIC_OPTIONS def_bool y diff --git a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig.name b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig.name index 8de7363..fad77d0 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/Kconfig.name +++ b/src/mainboard/hp/compaq_8200_elite_sff/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_HEWLETT_PACKARD_HP_COMPAQ_8200_ELITE_SFF_PC +config BOARD_HP_COMPAQ_8200_ELITE_SFF_PC bool "Compaq 8200 Elite SFF" diff --git a/src/mainboard/hp/z220_sff_workstation/Kconfig b/src/mainboard/hp/z220_sff_workstation/Kconfig index 649cbb1..dc288d6 100644 --- a/src/mainboard/hp/z220_sff_workstation/Kconfig +++ b/src/mainboard/hp/z220_sff_workstation/Kconfig @@ -1,4 +1,4 @@ -if BOARD_HP_COMPAQ_8200_ELITE_SFF_PC +if BOARD_HP_Z220_SFF_WORKSTATION config BOARD_SPECIFIC_OPTIONS def_bool y diff --git a/src/mainboard/hp/z220_sff_workstation/Kconfig.name b/src/mainboard/hp/z220_sff_workstation/Kconfig.name index b6cfda6..037ebc0 100644 --- a/src/mainboard/hp/z220_sff_workstation/Kconfig.name +++ b/src/mainboard/hp/z220_sff_workstation/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_HP_COMPAQ_8200_ELITE_SFF_PC +config BOARD_HP_Z220_SFF_WORKSTATION bool "Z220 SFF Workstation" -- To view, visit https://review.coreboot.org/c/coreboot/+/38083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I434cde42c7b9f30f8de77b96bc924aa298bad921 Gerrit-Change-Number: 38083 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/hp/*/devicetree.cb: Move northbridge devices up
by Angel Pons (Code Review) 10 Jan '20

10 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38082 ) Change subject: mb/hp/*/devicetree.cb: Move northbridge devices up ...................................................................... mb/hp/*/devicetree.cb: Move northbridge devices up It makes more sense for them to be above the southbridge block. Change-Id: I7dc06a46123f4bfc23d91f9c8cc4c9bdc4fb64f5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/hp/2570p/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/folio_9470m/devicetree.cb M src/mainboard/hp/revolve_810_g1/devicetree.cb M src/mainboard/hp/z220_sff_workstation/devicetree.cb 5 files changed, 22 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38082/1 diff --git a/src/mainboard/hp/2570p/devicetree.cb b/src/mainboard/hp/2570p/devicetree.cb index abac787..c659be6 100644 --- a/src/mainboard/hp/2570p/devicetree.cb +++ b/src/mainboard/hp/2570p/devicetree.cb @@ -44,6 +44,11 @@ end device domain 0x0 on subsystemid 0x103c 0x17df inherit + + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" @@ -95,8 +100,5 @@ device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 off end # Thermal end - device pci 00.0 on end # Host bridge Host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller end end diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index 660e3b0..9dc18be 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -41,6 +41,10 @@ device domain 0x0 on subsystemid 0x103c 0x1495 inherit + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" @@ -176,8 +180,5 @@ device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 off end # Thermal end - device pci 00.0 on end # Host bridge Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller end end diff --git a/src/mainboard/hp/folio_9470m/devicetree.cb b/src/mainboard/hp/folio_9470m/devicetree.cb index 7d0265d..b3299e8 100644 --- a/src/mainboard/hp/folio_9470m/devicetree.cb +++ b/src/mainboard/hp/folio_9470m/devicetree.cb @@ -45,6 +45,10 @@ device domain 0x0 on subsystemid 0x103c 0x18df inherit + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" @@ -100,8 +104,5 @@ device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 off end # Thermal end - device pci 00.0 on end # Host bridge Host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller end end diff --git a/src/mainboard/hp/revolve_810_g1/devicetree.cb b/src/mainboard/hp/revolve_810_g1/devicetree.cb index 4a08f42..1866a1e 100644 --- a/src/mainboard/hp/revolve_810_g1/devicetree.cb +++ b/src/mainboard/hp/revolve_810_g1/devicetree.cb @@ -45,6 +45,10 @@ device domain 0x0 on subsystemid 0x103c 0x18f8 inherit + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" @@ -100,8 +104,5 @@ device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 off end # Thermal end - device pci 00.0 on end # Host bridge Host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller end end diff --git a/src/mainboard/hp/z220_sff_workstation/devicetree.cb b/src/mainboard/hp/z220_sff_workstation/devicetree.cb index 94d079a..ab6ee04 100644 --- a/src/mainboard/hp/z220_sff_workstation/devicetree.cb +++ b/src/mainboard/hp/z220_sff_workstation/devicetree.cb @@ -40,6 +40,11 @@ device domain 0x0 on subsystemid 0x103c 0x1791 inherit + + device pci 00.0 on end # Host bridge Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + chip southbridge/intel/bd82x6x # Intel Series 7 PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" @@ -176,8 +181,5 @@ device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 off end # Thermal end - device pci 00.0 on end # Host bridge Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller end end -- To view, visit https://review.coreboot.org/c/coreboot/+/38082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7dc06a46123f4bfc23d91f9c8cc4c9bdc4fb64f5 Gerrit-Change-Number: 38082 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by Nico Huber (Code Review) 10 Jan '20

10 Jan '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 ) Change subject: drivers/fsp2_0: drop support for FSP-T ...................................................................... Patch Set 5: > > > I still need it for BtG > > > > Ack, let's see if we can make CB:36682 work. > > IMHO, I don't see a conflict to support FSP-T. It opens an option for users. Removing the FSP-T support would force a downstream diversity. Sorry, you might not know: optional FSP-T support has caused much friction in the community in the past. Its supporters have often just dumped patches into our repository and ran off, leaving maintenance to the coreboot commu- nity. Which, then again, usually doesn't get questions about FSP answered from Intel's FSP folks. Sometimes, it was unnecessarily enabled by default in a broken state, causing a lot of costs for the active community. So far it has caused more damage than provided value, Intel will have to make up for that if they want us to keep supporting FSP-T (which seems more work than getting rid of it anyway). Also, downstream diversity seems unavoidable. And we have to consider whose downstream we are talking about. So far, none of Intel's customers that want BtG have approached or supported the coreboot community on this matter. So one could say there is nothing to lose for us. On top, your other patch shows that one needed downstream patches anyway. Still, the coreboot commu- nity was leached for years, not to have no downstream patches but just to have one less? Here is what one of your colleagues (somewhere in the CB:36328 discussion) said why he can only help us with FSP issues in his spare time: "[Intel's] management is unwilling to formally assign people to something that won't directly impact chip sales." I'll leave it to you to infer what that means for something that doesn't directly benefit the coreboot community. I'm not saying things have to be or should be like that, but it was Intel who picked this fight... (oh, and I forgot to mention that FSP-T replaces open-source code, hence threatens to destroy coreboot) -- To view, visit https://review.coreboot.org/c/coreboot/+/36622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib791b30b621730f4b7c0a5f668a3b6559245daf5 Gerrit-Change-Number: 36622 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Vincent Zimmer <vincent.zimmer(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 10 Jan 2020 16:36:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/{common,skl,cnl,icl,apl,tgl}: Make me_hfsts1 structure SoC ...
by Sridhar Siricilla (Code Review) 10 Jan '20

10 Jan '20

Sridhar Siricilla has uploaded a new patch set (#22) to the change originally created by Rizwan Qureshi. ( https://review.coreboot.org/c/coreboot/+/35546 ) Change subject: soc/intel/{common,skl,cnl,icl,apl,tgl}: Make me_hfsts1 structure SoC specific ...................................................................... soc/intel/{common,skl,cnl,icl,apl,tgl}: Make me_hfsts1 structure SoC specific Move me_hfsts1 structure from common code to SoC specific. TEST=Build and Boot hatch, soraka, tglrvp, bobba boards. TBD=iclrvp Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/apollolake/cse.c A src/soc/intel/apollolake/include/soc/me.h M src/soc/intel/cannonlake/include/soc/me.h M src/soc/intel/cannonlake/me.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/icelake/Makefile.inc A src/soc/intel/icelake/include/soc/me.h A src/soc/intel/icelake/me.c M src/soc/intel/skylake/include/soc/me.h M src/soc/intel/skylake/me.c M src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/include/soc/me.h A src/soc/intel/tigerlake/me.c 14 files changed, 567 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35546/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/35546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Gerrit-Change-Number: 35546 Gerrit-PatchSet: 22 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <riz.pro(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by Gaggery Tsai (Code Review) 10 Jan '20

10 Jan '20

Gaggery Tsai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 ) Change subject: drivers/fsp2_0: drop support for FSP-T ...................................................................... Patch Set 5: > Patch Set 5: > > > Patch Set 5: Code-Review-1 > > > > I still need it for BtG > > Ack, let's see if we can make CB:36682 work. IMHO, I don't see a conflict to support FSP-T. It opens an option for users. Removing the FSP-T support would force a downstream diversity. -- To view, visit https://review.coreboot.org/c/coreboot/+/36622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib791b30b621730f4b7c0a5f668a3b6559245daf5 Gerrit-Change-Number: 36622 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Vincent Zimmer <vincent.zimmer(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 10 Jan 2020 15:45:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: console/post: Move cmos_post_code() under pc80/rtc
by Kyösti Mälkki (Code Review) 10 Jan '20

10 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38186 ) Change subject: console/post: Move cmos_post_code() under pc80/rtc ...................................................................... console/post: Move cmos_post_code() under pc80/rtc We should keep console/ somewhat arch-agnostic. Change-Id: I4465888023ba5ae0706b5e98e541c40f975d11e3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/console/post.c M src/drivers/pc80/rtc/Makefile.inc A src/drivers/pc80/rtc/post.c M src/include/console/console.h 4 files changed, 147 insertions(+), 133 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/38186/1 diff --git a/src/console/post.c b/src/console/post.c index 9d535cb..b9a7557 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -13,11 +13,7 @@ */ #include <stdint.h> -#include <elog.h> #include <console/console.h> -#include <device/device.h> -#include <pc80/mc146818rtc.h> -#include <smp/spinlock.h> #if CONFIG(POST_IO) #include <arch/io.h> #endif @@ -27,135 +23,7 @@ /* Some mainboards have very nice features beyond just a simple display. * They can override this function. */ -void __weak mainboard_post(uint8_t value) -{ -} - -#if CONFIG(CMOS_POST) - -DECLARE_SPIN_LOCK(cmos_post_lock) - -void cmos_post_log(void) -{ - u8 code = 0; -#if CONFIG(CMOS_POST_EXTRA) - u32 extra = 0; -#endif - - spin_lock(&cmos_post_lock); - - /* Get post code from other bank */ - switch (cmos_read(CMOS_POST_BANK_OFFSET)) { - case CMOS_POST_BANK_0_MAGIC: - code = cmos_read(CMOS_POST_BANK_1_OFFSET); -#if CONFIG(CMOS_POST_EXTRA) - extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); -#endif - break; - case CMOS_POST_BANK_1_MAGIC: - code = cmos_read(CMOS_POST_BANK_0_OFFSET); -#if CONFIG(CMOS_POST_EXTRA) - extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); -#endif - break; - } - - spin_unlock(&cmos_post_lock); - - /* Check last post code in previous boot against normal list */ - switch (code) { - case POST_OS_BOOT: - case POST_OS_RESUME: - case POST_ENTER_ELF_BOOT: - case 0: - break; - default: - printk(BIOS_WARNING, "POST: Unexpected post code " - "in previous boot: 0x%02x\n", code); -#if CONFIG(ELOG) && (ENV_RAMSTAGE || CONFIG(ELOG_PRERAM)) - elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); -#if CONFIG(CMOS_POST_EXTRA) - if (extra) - elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra); -#endif -#endif - } -} - -void cmos_post_init(void) -{ - u8 magic = CMOS_POST_BANK_0_MAGIC; - - /* Switch to the other bank */ - switch (cmos_read(CMOS_POST_BANK_OFFSET)) { - case CMOS_POST_BANK_1_MAGIC: - break; - case CMOS_POST_BANK_0_MAGIC: - magic = CMOS_POST_BANK_1_MAGIC; - break; - default: - /* Initialize to zero */ - cmos_write(0, CMOS_POST_BANK_0_OFFSET); - cmos_write(0, CMOS_POST_BANK_1_OFFSET); -#if CONFIG(CMOS_POST_EXTRA) - cmos_write32(0, CMOS_POST_BANK_0_EXTRA); - cmos_write32(0, CMOS_POST_BANK_1_EXTRA); -#endif - } - - cmos_write(magic, CMOS_POST_BANK_OFFSET); -} - -#if CONFIG(CMOS_POST_EXTRA) -void post_log_extra(u32 value) -{ - spin_lock(&cmos_post_lock); - - switch (cmos_read(CMOS_POST_BANK_OFFSET)) { - case CMOS_POST_BANK_0_MAGIC: - cmos_write32(value, CMOS_POST_BANK_0_EXTRA); - break; - case CMOS_POST_BANK_1_MAGIC: - cmos_write32(value, CMOS_POST_BANK_1_EXTRA); - break; - } - - spin_unlock(&cmos_post_lock); -} - -void post_log_path(const struct device *dev) -{ - if (dev) { - /* Encode path into lower 3 bytes */ - u32 path = dev_path_encode(dev); - /* Upper byte contains the log type */ - path |= CMOS_POST_EXTRA_DEV_PATH << 24; - post_log_extra(path); - } -} - -void post_log_clear(void) -{ - post_log_extra(0); -} -#endif /* CONFIG_CMOS_POST_EXTRA */ - -static void cmos_post_code(u8 value) -{ - spin_lock(&cmos_post_lock); - - switch (cmos_read(CMOS_POST_BANK_OFFSET)) { - case CMOS_POST_BANK_0_MAGIC: - cmos_write(value, CMOS_POST_BANK_0_OFFSET); - break; - case CMOS_POST_BANK_1_MAGIC: - cmos_write(value, CMOS_POST_BANK_1_OFFSET); - break; - } - - spin_unlock(&cmos_post_lock); -} -#endif /* CONFIG_CMOS_POST */ +void __weak mainboard_post(uint8_t value) { } void post_code(uint8_t value) { diff --git a/src/drivers/pc80/rtc/Makefile.inc b/src/drivers/pc80/rtc/Makefile.inc index 998b7e7..eb0ff6f 100644 --- a/src/drivers/pc80/rtc/Makefile.inc +++ b/src/drivers/pc80/rtc/Makefile.inc @@ -7,6 +7,8 @@ ramstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c smm-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c +all-$(CONFIG_CMOS_POST) += post.c + ifeq ($(CONFIG_USE_OPTION_TABLE),y) cbfs-files-$(CONFIG_HAVE_CMOS_DEFAULT) += cmos.default cmos.default-file = $(CONFIG_CMOS_DEFAULT_FILE):nvramtool diff --git a/src/drivers/pc80/rtc/post.c b/src/drivers/pc80/rtc/post.c new file mode 100644 index 0000000..e559edf --- /dev/null +++ b/src/drivers/pc80/rtc/post.c @@ -0,0 +1,143 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <elog.h> +#include <console/console.h> +#include <device/device.h> +#include <pc80/mc146818rtc.h> +#include <smp/spinlock.h> + +DECLARE_SPIN_LOCK(cmos_post_lock) + +void cmos_post_log(void) +{ + u8 code = 0; +#if CONFIG(CMOS_POST_EXTRA) + u32 extra = 0; +#endif + + spin_lock(&cmos_post_lock); + + /* Get post code from other bank */ + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_0_MAGIC: + code = cmos_read(CMOS_POST_BANK_1_OFFSET); +#if CONFIG(CMOS_POST_EXTRA) + extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); +#endif + break; + case CMOS_POST_BANK_1_MAGIC: + code = cmos_read(CMOS_POST_BANK_0_OFFSET); +#if CONFIG(CMOS_POST_EXTRA) + extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); +#endif + break; + } + + spin_unlock(&cmos_post_lock); + + /* Check last post code in previous boot against normal list */ + switch (code) { + case POST_OS_BOOT: + case POST_OS_RESUME: + case POST_ENTER_ELF_BOOT: + case 0: + break; + default: + printk(BIOS_WARNING, "POST: Unexpected post code " + "in previous boot: 0x%02x\n", code); +#if CONFIG(ELOG) && (ENV_RAMSTAGE || CONFIG(ELOG_PRERAM)) + elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); +#if CONFIG(CMOS_POST_EXTRA) + if (extra) + elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra); +#endif +#endif + } +} + +void cmos_post_init(void) +{ + u8 magic = CMOS_POST_BANK_0_MAGIC; + + /* Switch to the other bank */ + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_1_MAGIC: + break; + case CMOS_POST_BANK_0_MAGIC: + magic = CMOS_POST_BANK_1_MAGIC; + break; + default: + /* Initialize to zero */ + cmos_write(0, CMOS_POST_BANK_0_OFFSET); + cmos_write(0, CMOS_POST_BANK_1_OFFSET); +#if CONFIG(CMOS_POST_EXTRA) + cmos_write32(0, CMOS_POST_BANK_0_EXTRA); + cmos_write32(0, CMOS_POST_BANK_1_EXTRA); +#endif + } + + cmos_write(magic, CMOS_POST_BANK_OFFSET); +} + +#if CONFIG(CMOS_POST_EXTRA) +void post_log_extra(u32 value) +{ + spin_lock(&cmos_post_lock); + + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_0_MAGIC: + cmos_write32(value, CMOS_POST_BANK_0_EXTRA); + break; + case CMOS_POST_BANK_1_MAGIC: + cmos_write32(value, CMOS_POST_BANK_1_EXTRA); + break; + } + + spin_unlock(&cmos_post_lock); +} + +void post_log_path(const struct device *dev) +{ + if (dev) { + /* Encode path into lower 3 bytes */ + u32 path = dev_path_encode(dev); + /* Upper byte contains the log type */ + path |= CMOS_POST_EXTRA_DEV_PATH << 24; + post_log_extra(path); + } +} + +void post_log_clear(void) +{ + post_log_extra(0); +} +#endif /* CONFIG_CMOS_POST_EXTRA */ + +void cmos_post_code(u8 value) +{ + spin_lock(&cmos_post_lock); + + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_0_MAGIC: + cmos_write(value, CMOS_POST_BANK_0_OFFSET); + break; + case CMOS_POST_BANK_1_MAGIC: + cmos_write(value, CMOS_POST_BANK_1_OFFSET); + break; + } + + spin_unlock(&cmos_post_lock); +} diff --git a/src/include/console/console.h b/src/include/console/console.h index 583420c..d3c1d54 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -29,6 +29,7 @@ #include <console/vtxprintf.h> void post_code(u8 value); +void cmos_post_code(u8 value); #if CONFIG(CMOS_POST_EXTRA) void post_log_extra(u32 value); struct device; -- To view, visit https://review.coreboot.org/c/coreboot/+/38186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4465888023ba5ae0706b5e98e541c40f975d11e3 Gerrit-Change-Number: 38186 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: drivers/pc80/rtc: Enable normal/fallback without USE_OPTION_TABLE
by Kyösti Mälkki (Code Review) 10 Jan '20

10 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38184 ) Change subject: drivers/pc80/rtc: Enable normal/fallback without USE_OPTION_TABLE ...................................................................... drivers/pc80/rtc: Enable normal/fallback without USE_OPTION_TABLE Due the !USE_OPTION_TABLE it always booted to fallback. Change-Id: I44eb50df4389d1ac9e4c746f53654aff1055d400 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/pc80/rtc/mc146818rtc_boot.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/38184/1 diff --git a/src/drivers/pc80/rtc/mc146818rtc_boot.c b/src/drivers/pc80/rtc/mc146818rtc_boot.c index c009d67..307b1cf 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_boot.c +++ b/src/drivers/pc80/rtc/mc146818rtc_boot.c @@ -84,7 +84,7 @@ { unsigned char byte; - if (!CONFIG(USE_OPTION_TABLE) || cmos_error() || !cmos_chksum_valid()) { + if (cmos_error() || (CONFIG(USE_OPTION_TABLE) && !cmos_chksum_valid())) { /* Invalid CMOS checksum detected! * Force fallback boot... */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44eb50df4389d1ac9e4c746f53654aff1055d400 Gerrit-Change-Number: 38184 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: drivers/pc80/rtc: Move sanitize_cmos()
by Kyösti Mälkki (Code Review) 10 Jan '20

10 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38195 ) Change subject: drivers/pc80/rtc: Move sanitize_cmos() ...................................................................... drivers/pc80/rtc: Move sanitize_cmos() Implementation has dependency on USE_OPTION_TABLE. Change-Id: If7f8f478db3214842b6cc60cd77b4ea81cab6e3a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/pc80/rtc/mc146818rtc_boot.c M src/drivers/pc80/rtc/option.c 2 files changed, 23 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/38195/1 diff --git a/src/drivers/pc80/rtc/mc146818rtc_boot.c b/src/drivers/pc80/rtc/mc146818rtc_boot.c index 89b2be3..d345281 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_boot.c +++ b/src/drivers/pc80/rtc/mc146818rtc_boot.c @@ -12,28 +12,10 @@ */ #include <stdint.h> -#include <cbfs.h> #include <option.h> #include <pc80/mc146818rtc.h> #include <fallback.h> -void sanitize_cmos(void) -{ - if (cmos_error() || !cmos_lb_cks_valid() || CONFIG(STATIC_OPTION_TABLE)) { - size_t length = 128; - const unsigned char *cmos_default = - cbfs_boot_map_with_leak("cmos.default", - CBFS_COMPONENT_CMOS_DEFAULT, &length); - if (cmos_default) { - size_t i; - cmos_disable_rtc(); - for (i = 14; i < MIN(128, length); i++) - cmos_write_inner(cmos_default[i], i); - cmos_enable_rtc(); - } - } -} - #if CONFIG_MAX_REBOOT_CNT > 15 #error "CONFIG_MAX_REBOOT_CNT too high" #endif diff --git a/src/drivers/pc80/rtc/option.c b/src/drivers/pc80/rtc/option.c index 0f4e553..01707c2 100644 --- a/src/drivers/pc80/rtc/option.c +++ b/src/drivers/pc80/rtc/option.c @@ -234,7 +234,30 @@ return CB_SUCCESS; } +static void cmos_load_defaults(void) +{ + size_t length = 128; + size_t i; + + const unsigned char *cmos_default = + cbfs_boot_map_with_leak("cmos.default", + CBFS_COMPONENT_CMOS_DEFAULT, &length); + if (!cmos_default) + return; + + cmos_disable_rtc(); + for (i = 14; i < MIN(128, length); i++) + cmos_write_inner(cmos_default[i], i); + cmos_enable_rtc(); +} + int cmos_lb_cks_valid(void) { return cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC); } + +void sanitize_cmos(void) +{ + if (cmos_error() || !cmos_lb_cks_valid() || CONFIG(STATIC_OPTION_TABLE)) + cmos_load_defaults(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7f8f478db3214842b6cc60cd77b4ea81cab6e3a Gerrit-Change-Number: 38195 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: include/commonlib: Fix typos
by HAOUAS Elyes (Code Review) 10 Jan '20

10 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38271 ) Change subject: include/commonlib: Fix typos ...................................................................... include/commonlib: Fix typos Change-Id: I9650084f42de15c04c7e26d8a4442a4f9ff65a87 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/commonlib/include/commonlib/region.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/38271/1 diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h index 39db1bb..47df9b6 100644 --- a/src/commonlib/include/commonlib/region.h +++ b/src/commonlib/include/commonlib/region.h @@ -31,7 +31,7 @@ struct region_device; /* - * Returns NULL on error otherwise a buffer is returned with the conents of + * Returns NULL on error otherwise a buffer is returned with the contents of * the requested data at offset of size. */ void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size); @@ -173,7 +173,7 @@ struct region_device rdev; }; -/* Inititalize at runtime a mem_region_device. This would be used when +/* Initialize at runtime a mem_region_device. This would be used when * the base and size are dynamic or can't be known during linking. * There are two variants: read-only and read-write. */ void mem_region_device_ro_init(struct mem_region_device *mdev, void *base, -- To view, visit https://review.coreboot.org/c/coreboot/+/38271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9650084f42de15c04c7e26d8a4442a4f9ff65a87 Gerrit-Change-Number: 38271 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: src/commonlib/storage: Fix typos
by HAOUAS Elyes (Code Review) 10 Jan '20

10 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38269 ) Change subject: src/commonlib/storage: Fix typos ...................................................................... src/commonlib/storage: Fix typos Change-Id: Ie210191b79e94d3918ea95d40aeba40f33eb1b2f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/commonlib/storage/mmc.c M src/commonlib/storage/sd_mmc.c M src/commonlib/storage/sdhci.c 3 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/38269/1 diff --git a/src/commonlib/storage/mmc.c b/src/commonlib/storage/mmc.c index 1e0f7d2..8eaa2ee 100644 --- a/src/commonlib/storage/mmc.c +++ b/src/commonlib/storage/mmc.c @@ -436,7 +436,7 @@ if ((capacity >> 20) > 2 * 1024) media->capacity[MMC_PARTITION_USER] = capacity; - /* Determine the boot parition sizes */ + /* Determine the boot partition sizes */ hc_erase_size = ext_csd[224] * 512 * KiB; capacity = ext_csd[EXT_CSD_BOOT_SIZE_MULT] * 128 * KiB; media->capacity[MMC_PARTITION_BOOT_1] = capacity; diff --git a/src/commonlib/storage/sd_mmc.c b/src/commonlib/storage/sd_mmc.c index ae15656..c5fa76c 100644 --- a/src/commonlib/storage/sd_mmc.c +++ b/src/commonlib/storage/sd_mmc.c @@ -199,7 +199,7 @@ /* * For MMC cards, set the Relative Address. - * For SD cards, get the Relatvie Address. + * For SD cards, get the Relative Address. * This also puts the cards into Standby State */ cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index 6d99508..7d48265 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -146,7 +146,7 @@ sdhci_writel(sdhci_ctrlr, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS); mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT; - /* We shouldn't wait for data inihibit for stop commands, even + /* We shouldn't wait for data inhibit for stop commands, even though they might use busy signaling */ if (cmd->flags & CMD_FLAG_IGNORE_INHIBIT) mask &= ~SDHCI_DATA_INHIBIT; @@ -324,7 +324,7 @@ /* * on some platform(like rk3399 etc) need to worry about - * cache coherency, so check the buffer, if not dma + * cache coherence, so check the buffer, if not dma * coherent, use bounce_buffer to do DMA management. */ if (!dma_coherent(buf)) { @@ -408,7 +408,7 @@ & SDHCI_CLOCK_INT_STABLE)) { if (timeout == 0) { sdhc_error( - "Internal clock never stabilised.\n"); + "Internal clock never stabilized.\n"); return -1; } timeout--; -- To view, visit https://review.coreboot.org/c/coreboot/+/38269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie210191b79e94d3918ea95d40aeba40f33eb1b2f Gerrit-Change-Number: 38269 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 7

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2020