coreboot-gerrit January 2020

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Change in coreboot[master]: mb/gigabyte/ga-b75m-d3h/acpi_tables.c: Remove unneeded includes
by HAOUAS Elyes (Code Review) 12 Jan '20

12 Jan '20

HAOUAS Elyes has restored this change. ( https://review.coreboot.org/c/coreboot/+/26892 ) Change subject: mb/gigabyte/ga-b75m-d3h/acpi_tables.c: Remove unneeded includes ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/26892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic94e60188dbb9cdee959ecfa5ef14c92f125e3f2 Gerrit-Change-Number: 26892 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: restore

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Change in coreboot[master]: mb/foxconn/g41s-k/acpi_tables.c: Remove unneeded includes
by HAOUAS Elyes (Code Review) 12 Jan '20

12 Jan '20

Hello Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/26901 to look at the new patch set (#5). Change subject: mb/foxconn/g41s-k/acpi_tables.c: Remove unneeded includes ...................................................................... mb/foxconn/g41s-k/acpi_tables.c: Remove unneeded includes Change-Id: I41e3cbb4fbdd6680c1d9d347efc35d1618233a64 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/foxconn/g41s-k/acpi_tables.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/26901/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/26901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e3cbb4fbdd6680c1d9d347efc35d1618233a64 Gerrit-Change-Number: 26901 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/foxconn/g41s-k/acpi_tables.c: Remove unneeded includes
by HAOUAS Elyes (Code Review) 12 Jan '20

12 Jan '20

HAOUAS Elyes has restored this change. ( https://review.coreboot.org/c/coreboot/+/26901 ) Change subject: mb/foxconn/g41s-k/acpi_tables.c: Remove unneeded includes ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/26901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e3cbb4fbdd6680c1d9d347efc35d1618233a64 Gerrit-Change-Number: 26901 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: restore

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Change in coreboot[master]: mb/asrock/g41c-gs/acpi_tables.c: Remove unneeded includes
by HAOUAS Elyes (Code Review) 12 Jan '20

12 Jan '20

Hello Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/26900 to look at the new patch set (#5). Change subject: mb/asrock/g41c-gs/acpi_tables.c: Remove unneeded includes ...................................................................... mb/asrock/g41c-gs/acpi_tables.c: Remove unneeded includes Change-Id: Icd9efdf5fb4d57756704c62b5f575a3835a8ce11 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asrock/g41c-gs/acpi_tables.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/26900/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/26900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd9efdf5fb4d57756704c62b5f575a3835a8ce11 Gerrit-Change-Number: 26900 Gerrit-PatchSet: 5 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/asrock/g41c-gs/acpi_tables.c: Remove unneeded includes
by HAOUAS Elyes (Code Review) 12 Jan '20

12 Jan '20

HAOUAS Elyes has restored this change. ( https://review.coreboot.org/c/coreboot/+/26900 ) Change subject: mb/asrock/g41c-gs/acpi_tables.c: Remove unneeded includes ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/26900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd9efdf5fb4d57756704c62b5f575a3835a8ce11 Gerrit-Change-Number: 26900 Gerrit-PatchSet: 4 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: restore

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 12 Jan '20

12 Jan '20

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 ) Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... Patch Set 52: (1 comment) https://review.coreboot.org/c/coreboot/+/35402/44/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/cse_bp.c: https://review.coreboot.org/c/coreboot/+/35402/44/src/soc/intel/common/bloc… PS44, Line 64: static struct cse_boot_partition_info cse_bp_info; > Do we really need to maintain the global state of this? In general, I would expect this to be used o […] "cse_bp_info" is made global to retain the boot partition state, and update it when only there a change in the cse_bp_info state. It prevents sending GET_BOOT_PARTITION_INFO command multiple times. We defined granular level APIs around cse_bp_infp to avoid exposing GET_BOOT_PARTITION_INFO response data structure to CSE FW Update Flow. -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 52 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 12 Jan 2020 06:42:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/lenovo/g505s: Fix typos
by HAOUAS Elyes (Code Review) 12 Jan '20

12 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38369 ) Change subject: mb/lenovo/g505s: Fix typos ...................................................................... mb/lenovo/g505s: Fix typos Change-Id: I38fdc8ff92cffe467b2ca176e841bf601be9d24b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/g505s/BiosCallOuts.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/38369/1 diff --git a/src/mainboard/lenovo/g505s/BiosCallOuts.c b/src/mainboard/lenovo/g505s/BiosCallOuts.c index 2eb36fa..876b524 100644 --- a/src/mainboard/lenovo/g505s/BiosCallOuts.c +++ b/src/mainboard/lenovo/g505s/BiosCallOuts.c @@ -100,7 +100,7 @@ */ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) { - /* Enable IMC fan control. the recommand way */ + /* Enable IMC fan control. the recommend way */ if (CONFIG(HUDSON_IMC_FWM)) { imc_reg_init(); @@ -156,11 +156,11 @@ /* NOTE: * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, - * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it. - * so we remove it from AGESA code. Please Seee FchInitLateHwm. + * AGESA put EcDefaultMassege as global data in ROM, so we can't overwrite it. + * so we remove it from AGESA code. Please See FchInitLateHwm. */ } else { - /* HWM fan control, the way not recommand */ + /* HWM fan control, the way not recommend */ FchParams->Imc.ImcEnable = FALSE; FchParams->Hwm.HwMonitorEnable = TRUE; FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38fdc8ff92cffe467b2ca176e841bf601be9d24b Gerrit-Change-Number: 38369 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/{common,skl,cnl,icl,apl,tgl}: Make me_hfsts1 structure SoC ...
by Sridhar Siricilla (Code Review) 12 Jan '20

12 Jan '20

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35546 ) Change subject: soc/intel/{common,skl,cnl,icl,apl,tgl}: Make me_hfsts1 structure SoC specific ...................................................................... Patch Set 22: (15 comments) https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 78: GR_ORIGIN_BIOS_POST > It's not command id or group id. […] Done https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 84: operation and working modes > Modified the comment in the patch: https://review.coreboot. […] Done https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 85: HFS > Implemented the comment in the patch - https://review.coreboot. […] Done https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 86: MODE > Implemented the comment in the patch - https://review.coreboot. […] Done https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 598: rst_type > Are the different reset types supported by ME firmware for all platforms? For CML, I don't see all t […] Done https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 606: heci_reset(); > heci_reset() is called to reset heci interface to synchronize host and ME for communication. Done https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 609: memset(&reply, 0, reply_size); > What is the use of setting this to 0? Not required. Removed the code. https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 650: padding > Rather than padding, can we name this reserved just like it is in BWG? Done in the patch @ https://review.coreboot.org/c/coreboot/+/37283/13/src/soc/intel/common/bloc… https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 662: or temporary disable mode > Is this correct? I don't see this in BWG. Please refer patch: https://review.coreboot.org/c/coreboot/+/37283/13 for latest. Currently, this is not yet documented. We are working internally to document the same. https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 664: hfs1.fields.working_state > Not for this change, but I think we should add helper fucntions for CWS and COP i.e. […] Helper function wouldn't be unnecessay function call & additional operations to return the bitfield. https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 678: } > comment is addressed in the patch - https://review.coreboot. […] Done https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 679: return 1; > HMRFPO enabling needs to be followed by a global reset. […] keeping global reset out of this command handler will help supporting all flows of CSE FW Update. https://review.coreboot.org/c/coreboot/+/35546/15/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35546/15/src/soc/intel/common/bloc… PS15, Line 47: #if CONFIG(SOC_INTEL_APOLLOLAKE) > i don't think in common code we had any soc check so far correct. https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 47: SOC_INTEL_APOLLOLAKE > Moved me_hfsts1 defination into SoC specific code. Done https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 143: > Implemented in the patch : https://review.coreboot. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Gerrit-Change-Number: 35546 Gerrit-PatchSet: 22 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <riz.pro(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 12 Jan 2020 04:32:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge: Tidy up raminit code
by Angel Pons (Code Review) 11 Jan '20

11 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38317 ) Change subject: nb/intel/sandybridge: Tidy up raminit code ...................................................................... nb/intel/sandybridge: Tidy up raminit code Some things fit in a single line now that we have a 96-char limit. Tested, does not change the binary of Gigabyte GA-H61MA-D3V. Change-Id: I3bef75291d1ecb2c9c3c74d9e78caf84a1f726aa Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 64 insertions(+), 120 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/38317/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 43e9e91..3e17328 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1233,8 +1233,7 @@ { u32 timA = ctrl->timings[channel][slotrank].lanes[lane].timA; return ((MCHBAR32(lane_registers[lane] + channel * 0x100 + 4 + - ((timA / 32) & 1) * 4) - >> (timA % 32)) & 1); + ((timA / 32) & 1) * 4) >> (timA % 32)) & 1); } struct run { @@ -1353,8 +1352,7 @@ } } -static int discover_402x(ramctr_timing *ctrl, int channel, int slotrank, - int *upperA) +static int discover_402x(ramctr_timing *ctrl, int channel, int slotrank, int *upperA) { int works[NUM_LANES]; int lane; @@ -1390,11 +1388,9 @@ return MAKE_ERR; } FOR_ALL_LANES if (works[lane]) { - ctrl->timings[channel][slotrank].lanes[lane].timA += - 128; + ctrl->timings[channel][slotrank].lanes[lane].timA += 128; upperA[lane] += 128; - printram("increment %d, %d, %d\n", channel, - slotrank, lane); + printram("increment %d, %d, %d\n", channel, slotrank, lane); } } return 0; @@ -1415,13 +1411,11 @@ if (mnmx->timA_min_high > (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6)) mnmx->timA_min_high = - (ctrl->timings[channel][slotrank].lanes[lane]. - timA >> 6); + (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6); if (mnmx->timA_max_high < (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6)) mnmx->timA_max_high = - (ctrl->timings[channel][slotrank].lanes[lane]. - timA >> 6); + (ctrl->timings[channel][slotrank].lanes[lane].timA >> 6); } } @@ -1431,7 +1425,7 @@ struct timA_minmax post; int shift_402x = 0; - /* Get changed maxima. */ + /* Get changed maxima. */ pre_timA_change(ctrl, channel, slotrank, &post); if (mnmx->timA_max_high - mnmx->timA_min_high < @@ -1450,21 +1444,18 @@ } /* Compensate the skew between DQS and DQs. - * To ease PCB design a small skew between Data Strobe signals and - * Data Signals is allowed. - * The controller has to measure and compensate this skew for every byte-lane. - * By delaying either all DQs signals or DQS signal, a full phase - * shift can be introduced. - * It is assumed that one byte-lane's DQs signals have the same routing delay. + * To ease PCB design, a small skew between Data Strobe signals and Data Signals is allowed. + * The controller has to measure and compensate this skew for every byte-lane. By delaying + * either all DQs signals or DQS signal, a full phase shift can be introduced. It is assumed + * that one byte-lane's DQs signals have the same routing delay. * - * To measure the actual skew, the DRAM is placed in "read leveling" mode. - * In read leveling mode the DRAM-chip outputs an alternating periodic pattern. - * The memory controller iterates over all possible values to do a full phase shift - * and issues read commands. - * With DQS and DQs in phase the data read is expected to alternate on every byte: - * 0xFF 0x00 0xFF ... - * Once the controller has detected this pattern a bit in the result register is - * set for the current phase shift. + * To measure the actual skew, the DRAM is placed in "read leveling" mode. In read leveling + * mode the DRAM-chip outputs an alternating periodic pattern. The memory controller iterates + * over all possible values to do a full phase shift and issues read commands. With DQS and + * DQs in phase the data read is expected to alternate on every byte: + * 0xFF 0x00 0xFF ... + * Once the controller has detected this pattern a bit in the result register is set for the + * current phase shift. */ int read_training(ramctr_timing *ctrl) { @@ -1498,8 +1489,7 @@ all_high = 1; some_high = 0; FOR_ALL_LANES { - if (ctrl->timings[channel][slotrank].lanes[lane].timA >= - 0x40) + if (ctrl->timings[channel][slotrank].lanes[lane].timA >= 0x40) some_high = 1; else all_high = 0; @@ -1509,8 +1499,7 @@ ctrl->timings[channel][slotrank].io_latency--; printram("4028--;\n"); FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane]. - timA -= 0x40; + ctrl->timings[channel][slotrank].lanes[lane].timA -= 0x40; upperA[lane] -= 0x40; } @@ -1659,8 +1648,7 @@ int threshold = min/2 + max/2; for (i = 0; i < count; i++) data[i] = data[i] > threshold; - printram("threshold=%d min=%d max=%d\n", - threshold, min, max); + printram("threshold=%d min=%d max=%d\n", threshold, min, max); } static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) @@ -1681,8 +1669,7 @@ MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(1); for (timC = 0; timC <= MAX_TIMC; timC++) { - FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane]. - timC = timC; + FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = timC; program_timings(ctrl, channel); test_timC(ctrl, channel, slotrank); @@ -1729,8 +1716,7 @@ static void fill_pattern0(ramctr_timing *ctrl, int channel, u32 a, u32 b) { unsigned int j; - unsigned int channel_offset = - get_precedening_channels(ctrl, channel) * 0x40; + unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; for (j = 0; j < 16; j++) write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); sfence(); @@ -1747,8 +1733,7 @@ static void fill_pattern1(ramctr_timing *ctrl, int channel) { unsigned int j; - unsigned int channel_offset = - get_precedening_channels(ctrl, channel) * 0x40; + unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; unsigned int channel_step = 0x40 * num_of_channels(ctrl); for (j = 0; j < 16; j++) write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff); @@ -1763,10 +1748,8 @@ FOR_ALL_POPULATED_CHANNELS { FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = - 16; - ctrl->timings[channel][slotrank].lanes[lane].rising = - 16; + ctrl->timings[channel][slotrank].lanes[lane].falling = 16; + ctrl->timings[channel][slotrank].lanes[lane].rising = 16; } program_timings(ctrl, channel); @@ -1816,10 +1799,8 @@ } FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = - 48; - ctrl->timings[channel][slotrank].lanes[lane].rising = - 48; + ctrl->timings[channel][slotrank].lanes[lane].falling = 48; + ctrl->timings[channel][slotrank].lanes[lane].rising = 48; } program_timings(ctrl, channel); @@ -1872,8 +1853,7 @@ static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) { /* enable DQs on this slotrank */ - write_mrreg(ctrl, channel, slotrank, 1, - 0x80 | make_mr1(ctrl, slotrank, channel)); + write_mrreg(ctrl, channel, slotrank, 1, 0x80 | make_mr1(ctrl, slotrank, channel)); wait_for_iosav(channel); /* DRAM command NOP */ @@ -1885,8 +1865,7 @@ /* DRAM command NOP */ MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f107; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = - 0x4000c01 | ((ctrl->CAS + 38) << 16); + MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x4000c01 | ((ctrl->CAS + 38) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 4; MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; @@ -1896,8 +1875,7 @@ wait_for_iosav(channel); /* disable DQs on this slotrank */ - write_mrreg(ctrl, channel, slotrank, 1, - 0x1080 | make_mr1(ctrl, slotrank, channel)); + write_mrreg(ctrl, channel, slotrank, 1, 0x1080 | make_mr1(ctrl, slotrank, channel)); } static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) @@ -2018,16 +1996,13 @@ /* DRAM command PREA */ MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f002; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = - 0xc01 | ((ctrl->tRP) << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = - (slotrank << 24) | 0x60400; + MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0xc01 | ((ctrl->tRP) << 16); + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60400; MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x240; /* DRAM command ACT */ MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x1f006; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = - 0xc01 | ((ctrl->tRCD) << 16); + MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0xc01 | ((ctrl->tRCD) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = (slotrank << 24) | 0x60000; MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0; @@ -2044,8 +2019,7 @@ wait_for_iosav(channel); FOR_ALL_LANES { - u64 res = MCHBAR32(lane_registers[lane] + - channel * 0x100 + 4); + u64 res = MCHBAR32(lane_registers[lane] + channel * 0x100 + 4); res |= ((u64) MCHBAR32(lane_registers[lane] + channel * 0x100 + 8)) << 32; old = ctrl->timings[channel][slotrank].lanes[lane].timB; @@ -2053,10 +2027,8 @@ get_timB_high_adjust(res) * 64; printram("High adjust %d:%016llx\n", lane, res); - printram("Bval+: %d, %d, %d, %x -> %x\n", channel, - slotrank, lane, old, - ctrl->timings[channel][slotrank].lanes[lane]. - timB); + printram("Bval+: %d, %d, %d, %x -> %x\n", channel, slotrank, lane, + old, ctrl->timings[channel][slotrank].lanes[lane].timB); } } MCHBAR32(GDCRTRAININGMOD) = 0; @@ -2276,8 +2248,7 @@ static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno) { unsigned int i, j; - unsigned int channel_offset = - get_precedening_channels(ctrl, channel) * 0x40; + unsigned int channel_offset = get_precedening_channels(ctrl, channel) * 0x40; unsigned int channel_step = 0x40 * num_of_channels(ctrl); if (patno) { @@ -2367,8 +2338,7 @@ printram("Trying cmd_stretch %d on channel %d\n", cmd_stretch, channel); FOR_ALL_POPULATED_RANKS { - saved_timings[channel][slotrank] = - ctrl->timings[channel][slotrank]; + saved_timings[channel][slotrank] = ctrl->timings[channel][slotrank]; } ctrl->cmd_stretch[channel] = cmd_stretch; @@ -2398,8 +2368,7 @@ program_timings(ctrl, channel); reprogram_320c(ctrl); FOR_ALL_POPULATED_RANKS { - stat[slotrank][c320c + 127] = - test_320c(ctrl, channel, slotrank); + stat[slotrank][c320c + 127] = test_320c(ctrl, channel, slotrank); } } FOR_ALL_POPULATED_RANKS { @@ -2464,8 +2433,7 @@ return err; } - printram("Using CMD rate %uT on channel %u\n", - cmdrate + 1, channel); + printram("Using CMD rate %uT on channel %u\n", cmdrate + 1, channel); } FOR_ALL_POPULATED_CHANNELS @@ -2476,8 +2444,7 @@ } -static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, - int *edges) +static int discover_edges_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) { int edge; int statistics[NUM_LANES][MAX_EDGE_TIMING + 1]; @@ -2485,10 +2452,8 @@ for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].rising = - edge; - ctrl->timings[channel][slotrank].lanes[lane].falling = - edge; + ctrl->timings[channel][slotrank].lanes[lane].rising = edge; + ctrl->timings[channel][slotrank].lanes[lane].falling = edge; } program_timings(ctrl, channel); @@ -2504,8 +2469,7 @@ * all reads return a predefined pattern */ MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f000; MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = - (slotrank << 24) | 0x360004; + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x360004; MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0; /* DRAM command RD */ @@ -2516,8 +2480,7 @@ /* DRAM command RD */ MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = - 0x1001 | ((ctrl->CAS + 8) << 16); + MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x1001 | ((ctrl->CAS + 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = (slotrank << 24) | 0x60000; MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0; @@ -2525,8 +2488,7 @@ * MR3 disable MPR */ MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x1f000; MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = 0xc01 | (ctrl->tMOD << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = - (slotrank << 24) | 0x360000; + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = (slotrank << 24) | 0x360000; MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0; // execute command queue @@ -2540,8 +2502,7 @@ } } FOR_ALL_LANES { - struct run rn = - get_longest_zero_run(statistics[lane], MAX_EDGE_TIMING + 1); + struct run rn = get_longest_zero_run(statistics[lane], MAX_EDGE_TIMING + 1); edges[lane] = rn.middle; if (rn.all) { printk(BIOS_EMERG, "edge discovery failed: %d, %d, %d\n", @@ -2577,10 +2538,8 @@ } FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = - 16; - ctrl->timings[channel][slotrank].lanes[lane].rising = - 16; + ctrl->timings[channel][slotrank].lanes[lane].falling = 16; + ctrl->timings[channel][slotrank].lanes[lane].rising = 16; } program_timings(ctrl, channel); @@ -2633,10 +2592,8 @@ /* XXX: check any measured value ? */ FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = - 48; - ctrl->timings[channel][slotrank].lanes[lane].rising = - 48; + ctrl->timings[channel][slotrank].lanes[lane].falling = 48; + ctrl->timings[channel][slotrank].lanes[lane].rising = 48; } program_timings(ctrl, channel); @@ -2690,8 +2647,7 @@ FOR_ALL_LANES { MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = - ~MCHBAR32(IOSAV_By_BW_SERROR_ch(channel, lane)) - & 0xff; + ~MCHBAR32(IOSAV_By_BW_SERROR_ch(channel, lane)) & 0xff; } fill_pattern0(ctrl, channel, 0, 0xffffffff); @@ -2782,8 +2738,7 @@ MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f006; MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x4 | (ctrl->tRCD << 16) | - (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) - << 10); + (MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x240; @@ -2821,8 +2776,7 @@ MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); } - raw_statistics[edge] = - MCHBAR32(0x436c + channel * 0x400); + raw_statistics[edge] = MCHBAR32(0x436c + channel * 0x400); } FOR_ALL_LANES { struct run rn; @@ -2906,8 +2860,7 @@ /* DRAM command ACT */ MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x1f006; MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = - (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) - << 10) | (ctrl->tRCD << 16) | 4; + (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) | (ctrl->tRCD << 16) | 4; MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = (slotrank << 24) | 0x60000; MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x244; @@ -2921,8 +2874,7 @@ /* DRAM command RD */ MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x1f105; - MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = - 0x40011e0 | (MAX(ctrl->tRTP, 8) << 16); + MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x40011e0 | (MAX(ctrl->tRTP, 8) << 16); MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = slotrank << 24; MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x242; @@ -3090,8 +3042,7 @@ slotrank = 0; FOR_ALL_POPULATED_CHANNELS if (MCHBAR32(MC_INIT_STATE_ch(channel)) & 0xa000) { - printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", - channel); + printk(BIOS_EMERG, "Mini channel test failed (1): %d\n", channel); return MAKE_ERR; } FOR_ALL_POPULATED_CHANNELS { @@ -3112,29 +3063,25 @@ /* DRAM command ACT */ MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 0)) = 0x0001f006; MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 0)) = 0x0028a004; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = - 0x00060000 | (slotrank << 24); + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = 0x00060000 | (slotrank << 24); MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 0)) = 0x00000244; /* DRAM command WR */ MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 1)) = 0x0001f201; MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 1)) = 0x08281064; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = - 0x00000000 | (slotrank << 24); + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = 0x00000000 | (slotrank << 24); MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 1)) = 0x00000242; /* DRAM command RD */ MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 2)) = 0x0001f105; MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 2)) = 0x04281064; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = - 0x00000000 | (slotrank << 24); + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = 0x00000000 | (slotrank << 24); MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 2)) = 0x00000242; /* DRAM command PRE */ MCHBAR32(IOSAV_n_SP_CMD_CTL_ch(channel, 3)) = 0x0001f002; MCHBAR32(IOSAV_n_SUBSEQ_CTL_ch(channel, 3)) = 0x00280c01; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = - 0x00060400 | (slotrank << 24); + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 3)) = 0x00060400 | (slotrank << 24); MCHBAR32(IOSAV_n_ADDR_UPD_ch(channel, 3)) = 0x00000240; // execute command queue @@ -3316,13 +3263,10 @@ t1_ns += 500; t2_ns = 10 * ((MCHBAR32(SAPMTIMERS) >> 8) & 0xfff); - if (MCHBAR32(SAPMCTL) & 8) - { + if (MCHBAR32(SAPMCTL) & 8) { t3_ns = 10 * ((MCHBAR32(BANDTIMERS_IVB) >> 8) & 0xfff); t3_ns += 10 * (MCHBAR32(SAPMTIMERS2_IVB) & 0xff); - } - else - { + } else { t3_ns = 500; } printk(BIOS_DEBUG, "t123: %d, %d, %d\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/38317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bef75291d1ecb2c9c3c74d9e78caf84a1f726aa Gerrit-Change-Number: 38317 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11-lga1151-series:
by Philipp Deppenwiese (Code Review) 11 Jan '20

11 Jan '20

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38344 ) Change subject: mb/supermicro/x11-lga1151-series: ...................................................................... mb/supermicro/x11-lga1151-series: Add vboot RO only fmap file Change-Id: I1ee6087a9e846550958479300b28a288f2551ed8 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/mainboard/supermicro/x11-lga1151-series/Kconfig A src/mainboard/supermicro/x11-lga1151-series/vboot-ro.fmd 2 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/38344/1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index 02c9c86..43bcea3 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -61,6 +61,7 @@ config FMDFILE string default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-ro-rwab.fmd" if VBOOT_SLOTS_RW_AB + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-ro.fmd" config CBFS_SIZE hex diff --git a/src/mainboard/supermicro/x11-lga1151-series/vboot-ro.fmd b/src/mainboard/supermicro/x11-lga1151-series/vboot-ro.fmd new file mode 100644 index 0000000..563e36b --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/vboot-ro.fmd @@ -0,0 +1,26 @@ +FLASH 16M { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x4ff000 + } + SI_BIOS@0x500000 0xb00000 { + MISC_RW@0x0 0x62000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x20000 0x2000 + SMMSTORE(PRESERVE)@0x22000 0x40000 + } + WP_RO@0x62000 0xa9e000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0xa9a000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x9aa000 + } + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ee6087a9e846550958479300b28a288f2551ed8 Gerrit-Change-Number: 38344 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

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