coreboot-gerrit January 2020

coreboot-gerrit@coreboot.org

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1869 discussions

Change in coreboot[master]: vendorcode/intel: Remove Ice Lake FSP Bindings
by Mimoja (Code Review) 10 Jan '20

10 Jan '20

Mimoja has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37579 ) Change subject: vendorcode/intel: Remove Ice Lake FSP Bindings ...................................................................... Patch Set 9: (2 comments) https://review.coreboot.org/c/coreboot/+/37579/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/37579/6//COMMIT_MSG@15 PS6, Line 15: We are also adding back the CHANNEL_PRESENT enum, that has been No. I would neither know where nor how. "Hey guys, the stuff you submitted to coreboot is not working, please fix!"? https://review.coreboot.org/c/coreboot/+/37579/6/src/soc/intel/tigerlake/ro… File src/soc/intel/tigerlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/37579/6/src/soc/intel/tigerlake/ro… PS6, Line 43: > There is no way to predict if the official headers will lack it. And […] Yes. It is build and boottested for icelake. Not touching tigerlake anymore -- To view, visit https://review.coreboot.org/c/coreboot/+/37579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d5520dcd30f4a68af325125052e16e867e91ec9 Gerrit-Change-Number: 37579 Gerrit-PatchSet: 9 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 10 Jan 2020 20:52:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/intel: Remove Ice Lake FSP Bindings
by Mimoja (Code Review) 10 Jan '20

10 Jan '20

Hello Patrick Rudolph, Edward O'Callaghan, Vanessa Eusebio, Subrata Banik, Angel Pons, Aamir Bohra, Philipp Deppenwiese, build bot (Jenkins), Nico Huber, David Guckian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37579 to look at the new patch set (#9). Change subject: vendorcode/intel: Remove Ice Lake FSP Bindings ...................................................................... vendorcode/intel: Remove Ice Lake FSP Bindings By updating the fsp submodule we now got all FSP headers from within that repo. This commit changes the default paths to use these and fixes some include paths to allow the usage of vendorcode/intel/edk2/UDK2017 together with the official Intel distribution. We are also adding back the CHANNEL_PRESENT enum, that has been removed by Intel. This was tested on the Razer Blade Stealth (late 2019). Change-Id: I7d5520dcd30f4a68af325125052e16e867e91ec9 Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> --- M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/romstage/romstage.c D src/vendorcode/intel/fsp/fsp2_0/icelake/FirmwareVersionInfoHob.h D src/vendorcode/intel/fsp/fsp2_0/icelake/FspUpd.h D src/vendorcode/intel/fsp/fsp2_0/icelake/FspmUpd.h D src/vendorcode/intel/fsp/fsp2_0/icelake/FspsUpd.h D src/vendorcode/intel/fsp/fsp2_0/icelake/FsptUpd.h D src/vendorcode/intel/fsp/fsp2_0/icelake/MemInfoHob.h 9 files changed, 17 insertions(+), 7,138 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/37579/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/37579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d5520dcd30f4a68af325125052e16e867e91ec9 Gerrit-Change-Number: 37579 Gerrit-PatchSet: 9 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vendorcode/intel: Remove Ice Lake FSP Bindings
by Mimoja (Code Review) 10 Jan '20

10 Jan '20

Hello Patrick Rudolph, Edward O'Callaghan, Vanessa Eusebio, Subrata Banik, Angel Pons, Aamir Bohra, Philipp Deppenwiese, build bot (Jenkins), Nico Huber, David Guckian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/37579 to look at the new patch set (#8). Change subject: vendorcode/intel: Remove Ice Lake FSP Bindings ...................................................................... vendorcode/intel: Remove Ice Lake FSP Bindings By updating the fsp submodule we now got all FSP headers from within that repo. This commit changes the default paths to use these and fixes some include paths to allow the usage of vendorcode/intel/edk2/UDK2017 together with the official Intel distribution. This was tested on the Razer Blade Stealth (late 2019). Change-Id: I7d5520dcd30f4a68af325125052e16e867e91ec9 Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> --- M src/drivers/intel/fsp2_0/include/fsp/soc_binding.h M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/romstage/romstage.c D src/vendorcode/intel/fsp/fsp2_0/icelake/FirmwareVersionInfoHob.h D src/vendorcode/intel/fsp/fsp2_0/icelake/FspUpd.h D src/vendorcode/intel/fsp/fsp2_0/icelake/FspmUpd.h D src/vendorcode/intel/fsp/fsp2_0/icelake/FspsUpd.h D src/vendorcode/intel/fsp/fsp2_0/icelake/FsptUpd.h D src/vendorcode/intel/fsp/fsp2_0/icelake/MemInfoHob.h 9 files changed, 17 insertions(+), 7,138 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/37579/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/37579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d5520dcd30f4a68af325125052e16e867e91ec9 Gerrit-Change-Number: 37579 Gerrit-PatchSet: 8 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vendorcode/intel: Remove Ice Lake FSP Bindings
by Mimoja (Code Review) 10 Jan '20

10 Jan '20

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Change in coreboot[master]: drivers/fsp2_0: drop support for FSP-T
by Gaggery Tsai (Code Review) 10 Jan '20

10 Jan '20

Gaggery Tsai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36622 ) Change subject: drivers/fsp2_0: drop support for FSP-T ...................................................................... Patch Set 5: > Patch Set 5: > > > > > I still need it for BtG > > > > > > Ack, let's see if we can make CB:36682 work. > > > > IMHO, I don't see a conflict to support FSP-T. It opens an option for users. Removing the FSP-T support would force a downstream diversity. > > Sorry, you might not know: optional FSP-T support has caused much friction > in the community in the past. Its supporters have often just dumped patches > into our repository and ran off, leaving maintenance to the coreboot commu- > nity. Which, then again, usually doesn't get questions about FSP answered > from Intel's FSP folks. Sometimes, it was unnecessarily enabled by default > in a broken state, causing a lot of costs for the active community. So far > it has caused more damage than provided value, Intel will have to make up > for that if they want us to keep supporting FSP-T (which seems more work > than getting rid of it anyway). > > Also, downstream diversity seems unavoidable. And we have to consider whose > downstream we are talking about. So far, none of Intel's customers that want > BtG have approached or supported the coreboot community on this matter. So > one could say there is nothing to lose for us. On top, your other patch > shows that one needed downstream patches anyway. Still, the coreboot commu- > nity was leached for years, not to have no downstream patches but just to > have one less? > > Here is what one of your colleagues (somewhere in the CB:36328 discussion) > said why he can only help us with FSP issues in his spare time: > > "[Intel's] management is unwilling to formally assign people to > something that won't directly impact chip sales." > > I'll leave it to you to infer what that means for something that doesn't > directly benefit the coreboot community. I'm not saying things have to be > or should be like that, but it was Intel who picked this fight... > > (oh, and I forgot to mention that FSP-T replaces open-source code, hence > threatens to destroy coreboot) Thank your for sharing the background as well as the info from CB:36328. I will help to do test for CB:36682 and see if I can make it work. -- To view, visit https://review.coreboot.org/c/coreboot/+/36622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib791b30b621730f4b7c0a5f668a3b6559245daf5 Gerrit-Change-Number: 36622 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Vincent Zimmer <vincent.zimmer(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 10 Jan 2020 18:58:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/hp/revolve_810_g1: Drop default DRAM_RESET_GATE_GPIO
by Angel Pons (Code Review) 10 Jan '20

10 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38088 ) Change subject: mb/hp/revolve_810_g1: Drop default DRAM_RESET_GATE_GPIO ...................................................................... mb/hp/revolve_810_g1: Drop default DRAM_RESET_GATE_GPIO When this board was added, S3 resume was tested and working, so it must be good enough. Change-Id: Ie095868ea2de7846b995271baf8155e57b495e40 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/hp/revolve_810_g1/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/38088/1 diff --git a/src/mainboard/hp/revolve_810_g1/Kconfig b/src/mainboard/hp/revolve_810_g1/Kconfig index f8a5f3f..3bcfc63 100644 --- a/src/mainboard/hp/revolve_810_g1/Kconfig +++ b/src/mainboard/hp/revolve_810_g1/Kconfig @@ -38,10 +38,6 @@ string default "8086,0166" -config DRAM_RESET_GATE_GPIO # FIXME: check this - int - default 60 - config MAX_CPUS int default 8 -- To view, visit https://review.coreboot.org/c/coreboot/+/38088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie095868ea2de7846b995271baf8155e57b495e40 Gerrit-Change-Number: 38088 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/hp/8770w/Kconfig: Drop INTEL_INT15
by Angel Pons (Code Review) 10 Jan '20

10 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38087 ) Change subject: mb/hp/8770w/Kconfig: Drop INTEL_INT15 ...................................................................... mb/hp/8770w/Kconfig: Drop INTEL_INT15 This laptop does not have integrated graphics. Change-Id: Id2209973f66536c8a3ead4bc3e9d5a05b7970c64 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/hp/8770w/Kconfig 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/38087/1 diff --git a/src/mainboard/hp/8770w/Kconfig b/src/mainboard/hp/8770w/Kconfig index 80f9199..0459208 100644 --- a/src/mainboard/hp/8770w/Kconfig +++ b/src/mainboard/hp/8770w/Kconfig @@ -21,7 +21,6 @@ select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select INTEL_INT15 select NORTHBRIDGE_INTEL_SANDYBRIDGE select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_C216 -- To view, visit https://review.coreboot.org/c/coreboot/+/38087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2209973f66536c8a3ead4bc3e9d5a05b7970c64 Gerrit-Change-Number: 38087 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/hp/{folio_9470m,revolve_810_g1}: Trim gfx.did to size
by Angel Pons (Code Review) 10 Jan '20

10 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38086 ) Change subject: mb/hp/{folio_9470m,revolve_810_g1}: Trim gfx.did to size ...................................................................... mb/hp/{folio_9470m,revolve_810_g1}: Trim gfx.did to size It probably comes from older autoport. Change-Id: I9950fd10e45f5016611a5d5b6a9e41c2b0f25a5f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/hp/folio_9470m/devicetree.cb M src/mainboard/hp/revolve_810_g1/devicetree.cb 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/38086/1 diff --git a/src/mainboard/hp/folio_9470m/devicetree.cb b/src/mainboard/hp/folio_9470m/devicetree.cb index 13a12b6..e04ab67 100644 --- a/src/mainboard/hp/folio_9470m/devicetree.cb +++ b/src/mainboard/hp/folio_9470m/devicetree.cb @@ -14,8 +14,8 @@ # GNU General Public License for more details. # -chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" +chip northbridge/intel/sandybridge + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" diff --git a/src/mainboard/hp/revolve_810_g1/devicetree.cb b/src/mainboard/hp/revolve_810_g1/devicetree.cb index 0de3930..048120a 100644 --- a/src/mainboard/hp/revolve_810_g1/devicetree.cb +++ b/src/mainboard/hp/revolve_810_g1/devicetree.cb @@ -14,8 +14,8 @@ # GNU General Public License for more details. # -chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" +chip northbridge/intel/sandybridge + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" register "gfx.link_frequency_270_mhz" = "1" register "gfx.ndid" = "3" register "gfx.use_spread_spectrum_clock" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/38086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9950fd10e45f5016611a5d5b6a9e41c2b0f25a5f Gerrit-Change-Number: 38086 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: HP sandy/ivy laptops: Enable SMBus on devicetree
by Angel Pons (Code Review) 10 Jan '20

10 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38085 ) Change subject: HP sandy/ivy laptops: Enable SMBus on devicetree ...................................................................... HP sandy/ivy laptops: Enable SMBus on devicetree It has no reason to be disabled. Change-Id: Iba82b6f71bc3d3a86576b719f2709595b530b702 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/hp/2570p/devicetree.cb M src/mainboard/hp/2760p/devicetree.cb M src/mainboard/hp/8460p/devicetree.cb M src/mainboard/hp/8470p/devicetree.cb M src/mainboard/hp/8770w/devicetree.cb M src/mainboard/hp/revolve_810_g1/devicetree.cb 6 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/38085/1 diff --git a/src/mainboard/hp/2570p/devicetree.cb b/src/mainboard/hp/2570p/devicetree.cb index aec3380..dcf9116 100644 --- a/src/mainboard/hp/2570p/devicetree.cb +++ b/src/mainboard/hp/2570p/devicetree.cb @@ -96,7 +96,7 @@ end end device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 off end # SMBus + device pci 1f.3 on end # SMBus device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 off end # Thermal end diff --git a/src/mainboard/hp/2760p/devicetree.cb b/src/mainboard/hp/2760p/devicetree.cb index c77367d..4e2b68c 100644 --- a/src/mainboard/hp/2760p/devicetree.cb +++ b/src/mainboard/hp/2760p/devicetree.cb @@ -92,7 +92,7 @@ end end device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 off end # SMBus + device pci 1f.3 on end # SMBus device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 off end # Thermal end diff --git a/src/mainboard/hp/8460p/devicetree.cb b/src/mainboard/hp/8460p/devicetree.cb index aeed664..5bbb4fe 100644 --- a/src/mainboard/hp/8460p/devicetree.cb +++ b/src/mainboard/hp/8460p/devicetree.cb @@ -107,7 +107,7 @@ end end device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 off end # SMBus + device pci 1f.3 on end # SMBus device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 off end # Thermal end diff --git a/src/mainboard/hp/8470p/devicetree.cb b/src/mainboard/hp/8470p/devicetree.cb index ef32189..28d8912 100644 --- a/src/mainboard/hp/8470p/devicetree.cb +++ b/src/mainboard/hp/8470p/devicetree.cb @@ -108,7 +108,7 @@ end end device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 off end # SMBus + device pci 1f.3 on end # SMBus device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 off end # Thermal end diff --git a/src/mainboard/hp/8770w/devicetree.cb b/src/mainboard/hp/8770w/devicetree.cb index 91116c5..9b3f077 100644 --- a/src/mainboard/hp/8770w/devicetree.cb +++ b/src/mainboard/hp/8770w/devicetree.cb @@ -96,7 +96,7 @@ end end device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 off end # SMBus + device pci 1f.3 on end # SMBus device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 off end # Thermal end diff --git a/src/mainboard/hp/revolve_810_g1/devicetree.cb b/src/mainboard/hp/revolve_810_g1/devicetree.cb index 129de70..0de3930 100644 --- a/src/mainboard/hp/revolve_810_g1/devicetree.cb +++ b/src/mainboard/hp/revolve_810_g1/devicetree.cb @@ -99,7 +99,7 @@ end end device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 off end # SMBus + device pci 1f.3 on end # SMBus device pci 1f.5 off end # SATA Controller 2 device pci 1f.6 off end # Thermal end -- To view, visit https://review.coreboot.org/c/coreboot/+/38085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iba82b6f71bc3d3a86576b719f2709595b530b702 Gerrit-Change-Number: 38085 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: HP sandy/ivy laptops: Align devicetrees
by Angel Pons (Code Review) 10 Jan '20

10 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38084 ) Change subject: HP sandy/ivy laptops: Align devicetrees ...................................................................... HP sandy/ivy laptops: Align devicetrees This makes it easier to spot differences. Change-Id: I16596a661ee4e56c2cb1d0aef663067ae6159705 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/hp/2570p/devicetree.cb M src/mainboard/hp/2760p/devicetree.cb M src/mainboard/hp/8460p/devicetree.cb M src/mainboard/hp/8470p/devicetree.cb M src/mainboard/hp/8770w/devicetree.cb M src/mainboard/hp/folio_9470m/devicetree.cb M src/mainboard/hp/revolve_810_g1/devicetree.cb 7 files changed, 77 insertions(+), 83 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/38084/1 diff --git a/src/mainboard/hp/2570p/devicetree.cb b/src/mainboard/hp/2570p/devicetree.cb index c659be6..aec3380 100644 --- a/src/mainboard/hp/2570p/devicetree.cb +++ b/src/mainboard/hp/2570p/devicetree.cb @@ -45,9 +45,9 @@ device domain 0x0 on subsystemid 0x103c 0x17df inherit - device pci 00.0 on end # Host bridge Host bridge + device pci 00.0 on end # Host bridge device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller + device pci 02.0 on end # Internal graphics chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" @@ -62,11 +62,11 @@ register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x33" - register "spi_lvscc" = "0x0" register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0" register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" - register "xhci_switchable_ports" = "0x0000000f" + register "xhci_switchable_ports" = "0x0000000f" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 @@ -75,7 +75,7 @@ device pci 16.3 off end # Management Engine KT device pci 19.0 on end # Intel Gigabit Ethernet device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1b.0 on end # HD Audio controller device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2, ExpressCard device pci 1c.2 on end # PCIe Port #3, SD/MMC @@ -86,14 +86,14 @@ device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device pci 1f.0 on # LPC bridge chip ec/hp/kbc1126 register "ec_data_port" = "0x62" - register "ec_cmd_port" = "0x66" - register "ec_ctrl_reg" = "0x81" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" register "ec_fan_ctrl_value" = "0x4d" device pnp ff.1 off end - end # kbc1126 + end end device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 off end # SMBus diff --git a/src/mainboard/hp/2760p/devicetree.cb b/src/mainboard/hp/2760p/devicetree.cb index f33d016..c77367d 100644 --- a/src/mainboard/hp/2760p/devicetree.cb +++ b/src/mainboard/hp/2760p/devicetree.cb @@ -45,9 +45,9 @@ device domain 0x0 on subsystemid 0x103c 0x162a inherit - device pci 00.0 on end # Host bridge Host bridge + device pci 00.0 on end # Host bridge device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller + device pci 02.0 on end # Internal graphics chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" @@ -71,7 +71,7 @@ device pci 16.3 off end # Management Engine KT device pci 19.0 on end # Intel Gigabit Ethernet device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1b.0 on end # HD Audio controller device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2, ExpressCard device pci 1c.2 on end # PCIe Port #3, SD/MMC @@ -82,14 +82,14 @@ device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device pci 1f.0 on # LPC bridge chip ec/hp/kbc1126 register "ec_data_port" = "0x60" - register "ec_cmd_port" = "0x64" - register "ec_ctrl_reg" = "0xca" + register "ec_cmd_port" = "0x64" + register "ec_ctrl_reg" = "0xca" register "ec_fan_ctrl_value" = "0x4d" device pnp ff.1 off end - end # kbc1126 + end end device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 off end # SMBus diff --git a/src/mainboard/hp/8460p/devicetree.cb b/src/mainboard/hp/8460p/devicetree.cb index 972ee48..aeed664 100644 --- a/src/mainboard/hp/8460p/devicetree.cb +++ b/src/mainboard/hp/8460p/devicetree.cb @@ -72,7 +72,7 @@ device pci 16.3 on end # Management Engine KT device pci 19.0 on end # Intel Gigabit Ethernet device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1b.0 on end # HD Audio controller device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2, ExpressCard device pci 1c.2 on end # PCIe Port #3, SD/MMC @@ -83,27 +83,25 @@ device pci 1c.7 on end # PCIe Port #8, NEC USB 3.0 Host Controller device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device pci 1f.0 on # LPC bridge chip ec/hp/kbc1126 register "ec_data_port" = "0x60" - register "ec_cmd_port" = "0x64" - register "ec_ctrl_reg" = "0xca" + register "ec_cmd_port" = "0x64" + register "ec_ctrl_reg" = "0xca" register "ec_fan_ctrl_value" = "0x6b" device pnp ff.1 off end - end # kbc1126 + end chip superio/smsc/lpc47n217 - device pnp 4e.3 on # Parallel - io 0x60 = 0x378 + device pnp 4e.3 on # Parallel + io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 4e.4 on # Com1 - io 0x60 = 0x3f8 + device pnp 4e.4 on # COM1 + io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.5 off # Com2 - end - end #chip superio/smsc/lpc47n217 - + device pnp 4e.5 off end # COM2 + end chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/hp/8470p/devicetree.cb b/src/mainboard/hp/8470p/devicetree.cb index afb254f..ef32189 100644 --- a/src/mainboard/hp/8470p/devicetree.cb +++ b/src/mainboard/hp/8470p/devicetree.cb @@ -47,7 +47,7 @@ device pci 00.0 on end # Host bridge device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller + device pci 02.0 on end # Internal graphics chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" @@ -63,11 +63,11 @@ register "sata_interface_speed_support" = "0x3" # HDD(0), ODD(1), mSATA(2), eSATA(4) register "sata_port_map" = "0x3f" - register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" - register "xhci_switchable_ports" = "0x0000000f" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 @@ -76,7 +76,7 @@ device pci 16.3 on end # Management Engine KT device pci 19.0 on end # Intel Gigabit Ethernet device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1b.0 on end # HD Audio controller device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2, ExpressCard device pci 1c.2 on end # PCIe Port #3, SD/MMC @@ -87,26 +87,25 @@ device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device pci 1f.0 on # LPC bridge chip ec/hp/kbc1126 register "ec_data_port" = "0x62" - register "ec_cmd_port" = "0x66" - register "ec_ctrl_reg" = "0x81" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" register "ec_fan_ctrl_value" = "0x6b" device pnp ff.1 off end - end # kbc1126 + end chip superio/smsc/lpc47n217 - device pnp 4e.3 on # Parallel - io 0x60 = 0x378 + device pnp 4e.3 on # Parallel + io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 4e.4 on # Com1 - io 0x60 = 0x3f8 + device pnp 4e.4 on # COM1 + io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.5 off # Com2 - end - end #chip superio/smsc/lpc47n217 + device pnp 4e.5 off end # COM2 + end end device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 off end # SMBus diff --git a/src/mainboard/hp/8770w/devicetree.cb b/src/mainboard/hp/8770w/devicetree.cb index a9096c5..91116c5 100644 --- a/src/mainboard/hp/8770w/devicetree.cb +++ b/src/mainboard/hp/8770w/devicetree.cb @@ -36,7 +36,7 @@ device pci 00.0 on end # GPU device pci 00.1 on end # HDMI Audio on GPU end - device pci 02.0 off end # Internal graphics VGA controller + device pci 02.0 off end # Internal graphics chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "c2_latency" = "0x0065" @@ -51,11 +51,11 @@ register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x1f" - register "superspeed_capable_ports" = "0x0000000f" - register "xhci_overcurrent_mapping" = "0x00000c03" - register "xhci_switchable_ports" = "0x0000000f" register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x00000c03" + register "xhci_switchable_ports" = "0x0000000f" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 on end # Management Engine Interface 1 @@ -64,7 +64,7 @@ device pci 16.3 off end # Management Engine KT device pci 19.0 on end # Intel Gigabit Ethernet device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1b.0 on end # HD Audio controller device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 on end # PCIe Port #2 device pci 1c.2 on end # Media Card and FireWire host controller @@ -75,26 +75,25 @@ device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device pci 1f.0 on # LPC bridge chip ec/hp/kbc1126 register "ec_data_port" = "0x62" - register "ec_cmd_port" = "0x66" - register "ec_ctrl_reg" = "0x81" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" register "ec_fan_ctrl_value" = "0x81" device pnp ff.1 off end - end # kbc1126 + end chip superio/smsc/lpc47n217 - device pnp 4e.3 on # Parallel - io 0x60 = 0x378 + device pnp 4e.3 on # Parallel + io 0x60 = 0x378 irq 0x70 = 7 end - device pnp 4e.4 on # Com1 - io 0x60 = 0x3f8 + device pnp 4e.4 on # COM1 + io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 4e.5 off # Com2 - end - end #chip superio/smsc/lpc47n217 + device pnp 4e.5 off end # COM2 + end end device pci 1f.2 on end # SATA Controller 1 device pci 1f.3 off end # SMBus diff --git a/src/mainboard/hp/folio_9470m/devicetree.cb b/src/mainboard/hp/folio_9470m/devicetree.cb index b3299e8..13a12b6 100644 --- a/src/mainboard/hp/folio_9470m/devicetree.cb +++ b/src/mainboard/hp/folio_9470m/devicetree.cb @@ -31,7 +31,7 @@ register "gpu_panel_power_up_delay" = "300" register "gpu_pch_backlight" = "0x0d9c0d9c" device cpu_cluster 0x0 on - chip cpu/intel/model_206ax # FIXME: check all registers + chip cpu/intel/model_206ax register "c1_acpower" = "1" register "c1_battery" = "1" register "c2_acpower" = "3" @@ -45,9 +45,9 @@ device domain 0x0 on subsystemid 0x103c 0x18df inherit - device pci 00.0 on end # Host bridge Host bridge + device pci 00.0 on end # Host bridge device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller + device pci 02.0 on end # Internal graphics chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" @@ -62,11 +62,11 @@ register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x3" - register "spi_lvscc" = "0x0" register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0" register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" - register "xhci_switchable_ports" = "0x0000000f" + register "xhci_switchable_ports" = "0x0000000f" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 off end # Management Engine Interface 1 @@ -75,7 +75,7 @@ device pci 16.3 off end # Management Engine KT device pci 19.0 on end # Intel Gigabit Ethernet device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1b.0 on end # HD Audio controller device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 off end # PCIe Port #2 device pci 1c.2 on end # PCIe Port #3 SDHCI @@ -86,15 +86,14 @@ device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device pci 1f.0 on # LPC bridge chip ec/hp/kbc1126 register "ec_data_port" = "0x62" - register "ec_cmd_port" = "0x66" - register "ec_ctrl_reg" = "0x81" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" register "ec_fan_ctrl_value" = "0x44" device pnp ff.1 off end - end # kbc1126 - + end chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/hp/revolve_810_g1/devicetree.cb b/src/mainboard/hp/revolve_810_g1/devicetree.cb index 1866a1e..129de70 100644 --- a/src/mainboard/hp/revolve_810_g1/devicetree.cb +++ b/src/mainboard/hp/revolve_810_g1/devicetree.cb @@ -31,7 +31,7 @@ register "gpu_panel_power_up_delay" = "300" register "gpu_pch_backlight" = "0x02880288" device cpu_cluster 0x0 on - chip cpu/intel/model_206ax # FIXME: check all registers + chip cpu/intel/model_206ax register "c1_acpower" = "1" register "c1_battery" = "1" register "c2_acpower" = "3" @@ -45,9 +45,9 @@ device domain 0x0 on subsystemid 0x103c 0x18f8 inherit - device pci 00.0 on end # Host bridge Host bridge + device pci 00.0 on end # Host bridge device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller + device pci 02.0 on end # Internal graphics chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" @@ -62,11 +62,11 @@ register "pcie_port_coalesce" = "1" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x1" - register "spi_lvscc" = "0x0" register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0" register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" - register "xhci_switchable_ports" = "0x0000000f" + register "xhci_switchable_ports" = "0x0000000f" device pci 14.0 on end # USB 3.0 Controller device pci 16.0 off end # Management Engine Interface 1 @@ -75,7 +75,7 @@ device pci 16.3 off end # Management Engine KT device pci 19.0 on end # Intel Gigabit Ethernet device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1b.0 on end # HD Audio controller device pci 1c.0 on end # PCIe Port #1 device pci 1c.1 off end # PCIe Port #2 device pci 1c.2 on end # PCIe Port #3 @@ -86,15 +86,14 @@ device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device pci 1f.0 on # LPC bridge chip ec/hp/kbc1126 register "ec_data_port" = "0x62" - register "ec_cmd_port" = "0x66" - register "ec_ctrl_reg" = "0x81" + register "ec_cmd_port" = "0x66" + register "ec_ctrl_reg" = "0x81" register "ec_fan_ctrl_value" = "0x70" device pnp ff.1 off end - end # kbc1126 - + end chip drivers/pc80/tpm device pnp 0c31.0 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/38084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16596a661ee4e56c2cb1d0aef663067ae6159705 Gerrit-Change-Number: 38084 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2020