coreboot-gerrit January 2020

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Change in coreboot[master]: sb/amd/agesa/hudson: Fix typo
by HAOUAS Elyes (Code Review) 10 Jan '20

10 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38260 ) Change subject: sb/amd/agesa/hudson: Fix typo ...................................................................... sb/amd/agesa/hudson: Fix typo Change-Id: I600ca64f7cfdb03ad525b632950cddadf9aab4ae Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/agesa/hudson/early_setup.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/38260/1 diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 090a852..2e3ff30 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -90,7 +90,7 @@ pm_write8(0xec, pm_read8(0xec) | 0x01); dev = PCI_DEV(0, 0x14, 3); - /* Serial port numeration on Hudson: + /* Serial port enumeration on Hudson: * PORT0 - 0x3f8 * PORT1 - 0x2f8 * PORT5 - 0x2e8 -- To view, visit https://review.coreboot.org/c/coreboot/+/38260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I600ca64f7cfdb03ad525b632950cddadf9aab4ae Gerrit-Change-Number: 38260 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: nb/intel/{i945,sandybridge}/bootblock.c: Fix typo
by HAOUAS Elyes (Code Review) 10 Jan '20

10 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38245 ) Change subject: nb/intel/{i945,sandybridge}/bootblock.c: Fix typo ...................................................................... nb/intel/{i945,sandybridge}/bootblock.c: Fix typo Change-Id: I3def16c7bbf9d1997930832185beb8228ae163bd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/bootblock.c M src/northbridge/intel/sandybridge/bootblock.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/38245/1 diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index 38564bd..1f20150 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -26,7 +26,7 @@ * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. + * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 7411496..b6ba395 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -26,7 +26,7 @@ * MCFG. This code also assumes that bootblock_northbridge_init() is * the first thing called in the non-asm boot block code. The final * assumption is that no assembly code is using the - * CONFIG_MMCONF_SUPPORT option to do PCI config acceses. + * CONFIG_MMCONF_SUPPORT option to do PCI config accesses. * * The PCIEXBAR is assumed to live in the memory mapped IO space under * 4GiB. -- To view, visit https://review.coreboot.org/c/coreboot/+/38245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3def16c7bbf9d1997930832185beb8228ae163bd Gerrit-Change-Number: 38245 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: {Documentation,soc/intel}: Fix typo
by HAOUAS Elyes (Code Review) 10 Jan '20

10 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37468 ) Change subject: {Documentation,soc/intel}: Fix typo ...................................................................... {Documentation,soc/intel}: Fix typo Change-Id: I708ab503ece37f44cc38511aad2383ab2cec3368 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Documentation/lib/payloads/fit.md M src/soc/intel/apollolake/chip.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/37468/1 diff --git a/Documentation/lib/payloads/fit.md b/Documentation/lib/payloads/fit.md index 57a1a54..c6ccc7b 100644 --- a/Documentation/lib/payloads/fit.md +++ b/Documentation/lib/payloads/fit.md @@ -58,7 +58,7 @@ The config entries contain a compatible string, that is used to find a matching config. -The following mainboard specific funtions provide the BOARDID and SKUID: +The following mainboard specific functions provide the BOARDID and SKUID: ```c uint32_t board_id(void); diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 6c195bb..2482659 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -267,7 +267,7 @@ devfn = devfn0 + inc; /* - * Increase funtion by 1. + * Increase function by 1. * Then find first enabled device to replace func0 * as that port was move to func0. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I708ab503ece37f44cc38511aad2383ab2cec3368 Gerrit-Change-Number: 37468 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: src/security: Fix typos
by HAOUAS Elyes (Code Review) 10 Jan '20

10 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38198 ) Change subject: src/security: Fix typos ...................................................................... src/security: Fix typos Change-Id: I238fce2d48cf62003a701f972a87974415419538 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/security/tpm/tis.h M src/security/vboot/misc.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/38198/1 diff --git a/src/security/tpm/tis.h b/src/security/tpm/tis.h index c410838..db7d92b 100644 --- a/src/security/tpm/tis.h +++ b/src/security/tpm/tis.h @@ -66,7 +66,7 @@ /* * tis_close() * - * terminate the currect session with the TPM by releasing the locked + * terminate the current session with the TPM by releasing the locked * locality. Returns 0 on success of -1 on failure (in case lock * removal did not succeed). */ diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 0b2c8e5..2d5b084 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -89,7 +89,7 @@ /* If we are in the stage that runs verification, or in the stage that both loads the verstage and is returned to from it afterwards, we - need to check a global to see if verfication has run. */ + need to check a global to see if verification has run. */ if (verification_should_run() || (verstage_should_load() && CONFIG(VBOOT_RETURN_FROM_VERSTAGE))) return vboot_executed; -- To view, visit https://review.coreboot.org/c/coreboot/+/38198 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I238fce2d48cf62003a701f972a87974415419538 Gerrit-Change-Number: 38198 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/variants/helios: Modify DPTF parameters
by Kane Chen (Code Review) 10 Jan '20

10 Jan '20

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38299 ) Change subject: mb/google/hatch/variants/helios: Modify DPTF parameters ...................................................................... mb/google/hatch/variants/helios: Modify DPTF parameters Modify DTRT CPU Throttle Effect on TSR0 change to TSR3. BUG=b:131272830 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I5b4645d7552e795a33c1b86d95c4061da71c65bd --- M src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/38299/1 diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl index a359284..f40d10a 100644 --- a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl @@ -99,8 +99,8 @@ }) Name (DTRT, Package () { - /* CPU Throttle Effect on TSR0 */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + /* CPU Throttle Effect on TSR3 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR3, 100, 60, 0, 0, 0, 0 }, /* Charger Throttle Effect on TSR0 */ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, -- To view, visit https://review.coreboot.org/c/coreboot/+/38299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b4645d7552e795a33c1b86d95c4061da71c65bd Gerrit-Change-Number: 38299 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: asus/am1i-a: fix the blue "USB 3.0" ports for OHCI/EHCI "USB 2.0" mode
by Mike Banon (Code Review) 10 Jan '20

10 Jan '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38241 ) Change subject: asus/am1i-a: fix the blue "USB 3.0" ports for OHCI/EHCI "USB 2.0" mode ...................................................................... asus/am1i-a: fix the blue "USB 3.0" ports for OHCI/EHCI "USB 2.0" mode Set up the proper IRQ routing for OHCI/EHCI devices which appear if XHCI controller is disabled (CONFIG_HUDSON_XHCI_ENABLE is not set). Now both "USB 3.0" ports are working fine at OHCI/EHCI "USB 2.0" mode. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I50a773eeab890627abc963e0a61f781d1cea3259 --- M src/mainboard/asus/am1i-a/Kconfig M src/mainboard/asus/am1i-a/acpi/routing.asl M src/mainboard/asus/am1i-a/devicetree.cb M src/mainboard/asus/am1i-a/irq_tables.c M src/mainboard/asus/am1i-a/mainboard.c M src/mainboard/asus/am1i-a/mptable.c 6 files changed, 27 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/38241/1 diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index a0dae9f..172d808 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -37,7 +37,7 @@ config IRQ_SLOT_COUNT int - default 9 + default 10 config ONBOARD_VGA_IS_PRIMARY bool diff --git a/src/mainboard/asus/am1i-a/acpi/routing.asl b/src/mainboard/asus/am1i-a/acpi/routing.asl index 95881fa..8b21a25 100644 --- a/src/mainboard/asus/am1i-a/acpi/routing.asl +++ b/src/mainboard/asus/am1i-a/acpi/routing.asl @@ -48,8 +48,14 @@ Package(){0x0013FFFF, 0, INTC, 0 }, Package(){0x0013FFFF, 1, INTB, 0 }, - /* Bus 0, Dev 10 Func 0 - USB: XHCI */ + /* Bus 0, Dev 16 Func 0 - USB: OHCI */ + /* Bus 0, Dev 16 Func 2 - USB: EHCI */ + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, /* Bus 0, Dev 11 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, @@ -87,8 +93,14 @@ Package(){0x0013FFFF, 0, 0, 18 }, Package(){0x0013FFFF, 1, 0, 17 }, - /* Bus 0, Dev 10, Func 0 - USB: XHCI */ + /* Bus 0, Dev 16 Func 0 - USB: OHCI */ + /* Bus 0, Dev 16 Func 1 - USB: EHCI */ + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 10 - USB: XHCI func 0, 1 */ Package(){0x0010FFFF, 0, 0, 18 }, + Package(){0x0010FFFF, 1, 0, 17 }, /* Bus 0, Dev 11 - SATA controller */ Package(){0x0011FFFF, 0, 0, 19 }, diff --git a/src/mainboard/asus/am1i-a/devicetree.cb b/src/mainboard/asus/am1i-a/devicetree.cb index 8e44874..2d7265a 100644 --- a/src/mainboard/asus/am1i-a/devicetree.cb +++ b/src/mainboard/asus/am1i-a/devicetree.cb @@ -84,6 +84,8 @@ end end #device pci 14.3 # LPC device pci 14.7 off end # SD - no card reader present + device pci 16.0 on end # OHCI USB + device pci 16.2 on end # EHCI USB end #chip southbridge/amd/agesa/hudson chip northbridge/amd/agesa/family16kb diff --git a/src/mainboard/asus/am1i-a/irq_tables.c b/src/mainboard/asus/am1i-a/irq_tables.c index c8ccbeb..84110d1 100644 --- a/src/mainboard/asus/am1i-a/irq_tables.c +++ b/src/mainboard/asus/am1i-a/irq_tables.c @@ -26,7 +26,7 @@ 0x439d, /* Device */ 0, /* Miniport */ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0xa8, /* Checksum (has to be set to some value that + 0x3b, /* Checksum (has to be set to some value that * would give 0 after the sum of all bytes * for this structure (including checksum). */ @@ -39,6 +39,7 @@ {0x00, (0x12 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, {0x00, (0x13 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, {0x00, (0x14 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0}, + {0x00, (0x16 << 3) | 0x0, {{0x03, 0x9cb8}, {0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, {0x01, (0x00 << 3) | 0x0, {{0x01, 0x9cb8}, {0x02, 0x9cb8}, {0x03, 0x9cb8}, {0x04, 0x9cb8}}, 0x0, 0x0}, {0x02, (0x00 << 3) | 0x0, {{0x02, 0x9cb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, } diff --git a/src/mainboard/asus/am1i-a/mainboard.c b/src/mainboard/asus/am1i-a/mainboard.c index bd6d3a3..65fd79a 100644 --- a/src/mainboard/asus/am1i-a/mainboard.c +++ b/src/mainboard/asus/am1i-a/mainboard.c @@ -34,8 +34,8 @@ [0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F, /* IMC INT0 - 5 */ [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* USB Devs 18/19 INTA-B */ - [0x30] = 0x05,0x04,0x05,0x04,0x1F,0x1F, + /* USB Devs 18/19/22 INTA-B */ + [0x30] = 0x05,0x04,0x05,0x04,0x05,0x04,0x1F,0x1F, /* RSVD, SATA */ [0x40] = 0x1F, 0x07 }; @@ -49,8 +49,8 @@ [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x1F, /* IMC INT0 - 5 */ [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, - /* USB Devs 18/19 INTA-B */ - [0x30] = 0x12,0x11,0x12,0x11,0x1F,0x1F, + /* USB Devs 18/19/22 INTA-B */ + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x1F,0x1F, /* RSVD, SATA */ [0x40] = 0x1F, 0x13 }; @@ -77,6 +77,8 @@ {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ }; diff --git a/src/mainboard/asus/am1i-a/mptable.c b/src/mainboard/asus/am1i-a/mptable.c index 9efcab3..3a6131f 100644 --- a/src/mainboard/asus/am1i-a/mptable.c +++ b/src/mainboard/asus/am1i-a/mptable.c @@ -91,6 +91,8 @@ PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]); PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]); /* Southbridge HD Audio */ PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_HDA]); -- To view, visit https://review.coreboot.org/c/coreboot/+/38241 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50a773eeab890627abc963e0a61f781d1cea3259 Gerrit-Change-Number: 38241 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/t431s/devicetree: Rebalance against t430s one
by Peter Lemenkov (Code Review) 10 Jan '20

10 Jan '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37600 ) Change subject: mb/lenovo/t431s/devicetree: Rebalance against t430s one ...................................................................... mb/lenovo/t431s/devicetree: Rebalance against t430s one Change-Id: Iec40dd20c87b97dbd81ba3c63486cb5e66d99dc6 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb 1 file changed, 2 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/37600/1 diff --git a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb index e3388de..ae95e6c 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb @@ -15,17 +15,14 @@ device domain 0 on subsystemid 0x17aa 0x2208 inherit - device pci 00.0 on end # host bridge device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Integrated Graphics Controller + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH # Enable SATA ports 0 (HDD bay) & 1 (WWAN M.2 SATA) & 4 (dock) register "sata_port_map" = "0x13" # T431s has no Express Card slot. register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - device pci 14.0 on end # USB 3.0 Controller - device pci 1a.0 on end # USB Enhanced Host Controller #2 - device pci 1b.0 on end # High Definition Audio Controller + device pci 1c.0 on # PCIe Port #1 chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x87" @@ -33,10 +30,7 @@ device pci 00.0 on end # Ricoh SD card reader end end - device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN device pci 1c.2 off end # PCIe Port #3 - device pci 1d.0 on end # USB Enhanced Host Controller #1 - device pci 1e.0 off end # PCI bridge device pci 1f.0 on chip ec/lenovo/h8 register "config0" = "0xa6" @@ -47,8 +41,6 @@ register "has_bdc_detection" = "0" end end # LPC Controller - device pci 1f.2 on end # 6 port SATA AHCI Controller - device pci 1f.3 on end # SMBus Controller device pci 1f.6 off end # Thermal end end -- To view, visit https://review.coreboot.org/c/coreboot/+/37600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec40dd20c87b97dbd81ba3c63486cb5e66d99dc6 Gerrit-Change-Number: 37600 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/lenovo/t431s/devicetree: Use subsystemid inheritance
by Peter Lemenkov (Code Review) 10 Jan '20

10 Jan '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37301 ) Change subject: mb/lenovo/t431s/devicetree: Use subsystemid inheritance ...................................................................... mb/lenovo/t431s/devicetree: Use subsystemid inheritance Change-Id: I247129317799d342b28f2c0ed68949ecbe7d9c75 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb 1 file changed, 6 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/37301/1 diff --git a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb index e69f727..1a4b67a 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t431s/overridetree.cb @@ -13,47 +13,26 @@ register "gpu_cpu_backlight" = "0x03d2" device domain 0 on - device pci 00.0 on - subsystemid 0x17aa 0x2208 - end # host bridge + subsystemid 0x17aa 0x2208 inherit + device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on - subsystemid 0x17aa 0x2208 - end # Integrated Graphics Controller + chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH # Enable SATA ports 0 (HDD bay) & 1 (WWAN M.2 SATA) & 4 (dock) register "sata_port_map" = "0x13" # T431s has no Express Card slot. register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" - device pci 14.0 on - subsystemid 0x17aa 0x2208 - end # USB 3.0 Controller - device pci 1a.0 on - subsystemid 0x17aa 0x2208 - end # USB Enhanced Host Controller #2 - device pci 1b.0 on - subsystemid 0x17aa 0x2208 - end # High Definition Audio Controller + device pci 1c.0 on # PCIe Port #1 - subsystemid 0x17aa 0x2208 chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x87" register "sdwppol" = "0" - device pci 00.0 on # Ricoh SD card reader - subsystemid 0x17aa 0x2208 - end + device pci 00.0 on end # Ricoh SD card reader end end - device pci 1c.1 on - subsystemid 0x17aa 0x2208 - end # PCIe Port #2 Integrated Wireless LAN + device pci 1c.2 off end # PCIe Port #3 - device pci 1d.0 on - subsystemid 0x17aa 0x2208 - end # USB Enhanced Host Controller #1 - device pci 1e.0 off end # PCI bridge device pci 1f.0 on - subsystemid 0x17aa 0x2208 chip ec/lenovo/h8 register "config0" = "0xa6" register "config1" = "0x09" @@ -63,12 +42,6 @@ register "has_bdc_detection" = "0" end end # LPC Controller - device pci 1f.2 on - subsystemid 0x17aa 0x2208 - end # 6 port SATA AHCI Controller - device pci 1f.3 on - subsystemid 0x17aa 0x2208 - end # SMBus Controller device pci 1f.6 off end # Thermal end end -- To view, visit https://review.coreboot.org/c/coreboot/+/37301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I247129317799d342b28f2c0ed68949ecbe7d9c75 Gerrit-Change-Number: 37301 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/inteltool: Add MCHBAR dumping support for Ice Lake U systems
by Mimoja (Code Review) 10 Jan '20

10 Jan '20

Mimoja has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38211 ) Change subject: util/inteltool: Add MCHBAR dumping support for Ice Lake U systems ...................................................................... util/inteltool: Add MCHBAR dumping support for Ice Lake U systems According to intels datasheet Document Number: 341078-001 10th Generation Intel® Core™ Processor Families Volume 2 of 2 we can dump the ICL MCHBAR similiar as on 8th / 9th gen CPUs. The difference is that on ICL the MCHBAR address is definited by the bits 38:16 instead of 38:15 giving the constraint that it has to be 64kbit instead of 32kbit aligned. (Section 3.1.13) Change-Id: Ia597a4b3738c11cb48ce5808d8459b4a2a768077 Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> --- M util/inteltool/memory.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/38211/1 diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index e80f1ba..e7523f3 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -232,6 +232,12 @@ mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */ size = 32768; break; + case PCI_DEVICE_ID_INTEL_CORE_10TH_GEN_U: + mchbar_phys = pci_read_long(nb, 0x48); + mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; + mchbar_phys &= 0x0000007fffff0000UL; /* 38:16 */ + size = 32768; + break; default: printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n"); return 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/38211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia597a4b3738c11cb48ce5808d8459b4a2a768077 Gerrit-Change-Number: 38211 Gerrit-PatchSet: 1 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: configs: Build test SPI console
by Patrick Rudolph (Code Review) 10 Jan '20

10 Jan '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38174 ) Change subject: configs: Build test SPI console ...................................................................... configs: Build test SPI console Change-Id: I70467862b238f8be62eafb5532ede9882dd2f41a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- R configs/config.up_squared.vboot_spi_flash_console 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/38174/1 diff --git a/configs/config.up_squared.vboot b/configs/config.up_squared.vboot_spi_flash_console similarity index 62% rename from configs/config.up_squared.vboot rename to configs/config.up_squared.vboot_spi_flash_console index 130c02f..a73dfee 100644 --- a/configs/config.up_squared.vboot +++ b/configs/config.up_squared.vboot_spi_flash_console @@ -1,2 +1,3 @@ CONFIG_VENDOR_UP=y CONFIG_VBOOT=y +CONSOLE_SPI_FLASH=y -- To view, visit https://review.coreboot.org/c/coreboot/+/38174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70467862b238f8be62eafb5532ede9882dd2f41a Gerrit-Change-Number: 38174 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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