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Change in coreboot[master]: soc/intel: Fix ACPI device operations initialization
by Karthik Ramasubramanian (Code Review) 12 Jan '20

12 Jan '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38309 ) Change subject: soc/intel: Fix ACPI device operations initialization ...................................................................... soc/intel: Fix ACPI device operations initialization Initialize ACPI device operations only when CONFIG_HAVE_ACPI_TABLES is enabled. BUG=None TEST=Build Test Change-Id: I5c5266885d8b08338d17a87bb95110765882120e Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/tigerlake/chip.c 4 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/38309/1 diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 90931eb..9873059 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -117,7 +117,9 @@ .enable_resources = pci_dev_enable_resources, .init = graphics_soc_init, .ops_pci = &pci_dev_ops_pci, +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = graphics_soc_write_acpi_opregion, +#endif .scan_bus = scan_generic_bus, }; diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 70f2c21..ffcc4a6 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -183,7 +183,9 @@ .ops_i2c_bus = &dw_i2c_bus_ops, .ops_pci = &pci_dev_ops_pci, .init = dw_i2c_device_init, +#if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = dw_i2c_acpi_fill_ssdt, +#endif }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 258975c..9e86486 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -112,8 +112,10 @@ .read_resources = pch_lpc_read_resources, .set_resources = pch_lpc_set_resources, .enable_resources = pci_dev_enable_resources, +#if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = southbridge_write_acpi_tables, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, +#endif .init = lpc_soc_init, .scan_bus = scan_static_bus, .ops_pci = &pci_dev_ops_pci, diff --git a/src/soc/intel/tigerlake/chip.c b/src/soc/intel/tigerlake/chip.c index 530893c..d05fbdf 100644 --- a/src/soc/intel/tigerlake/chip.c +++ b/src/soc/intel/tigerlake/chip.c @@ -156,7 +156,9 @@ .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = DEVICE_NOOP, +#if CONFIG(HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = generate_cpu_entries, +#endif }; static void soc_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/38309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c5266885d8b08338d17a87bb95110765882120e Gerrit-Change-Number: 38309 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/e7505: Always enable DIMM compabitility checks
by Kyösti Mälkki (Code Review) 12 Jan '20

12 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38295 ) Change subject: intel/e7505: Always enable DIMM compabitility checks ...................................................................... intel/e7505: Always enable DIMM compabitility checks Change-Id: I4862b4f0a029f6f4a1ff7e66cf814fa8f5686d3f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/e7505/raminit.c 1 file changed, 2 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/38295/1 diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 517ba6f..72f630d 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -48,11 +48,6 @@ Definitions: -----------------------------------------------------------------------------*/ -// Uncomment this to enable run-time checking of DIMM parameters -// for dual-channel operation -// Unfortunately the code seems to chew up several K of space. -//#define VALIDATE_DIMM_COMPATIBILITY - #if CONFIG(DEBUG_RAM_SETUP) #define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x) #define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x) @@ -115,7 +110,6 @@ #define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1) -#ifdef VALIDATE_DIMM_COMPATIBILITY // SPD parameters that must match for dual-channel operation static const uint8_t dual_channel_parameters[] = { SPD_MEMORY_TYPE, @@ -126,7 +120,6 @@ SPD_PRIMARY_SDRAM_WIDTH, SPD_NUM_BANKS_PER_SDRAM }; -#endif /* VALIDATE_DIMM_COMPATIBILITY */ /* Comments here are remains of e7501 or even 855PM. * They might be partially (in)correct for e7505. @@ -465,8 +458,6 @@ return sz; } -#ifdef VALIDATE_DIMM_COMPATIBILITY - /** * Determine whether two DIMMs have the same value for an SPD parameter. * @@ -490,7 +481,6 @@ return bEqual; } -#endif /** * Scan for compatible DIMMs. @@ -527,10 +517,8 @@ uint16_t channel0_dimm = ctrl->channel0[i]; uint16_t channel1_dimm = ctrl->channel1[i]; uint8_t bDualChannel = 1; -#ifdef VALIDATE_DIMM_COMPATIBILITY struct dimm_size page_size; struct dimm_size sdram_width; -#endif int spd_value; if (channel0_dimm == 0) @@ -540,7 +528,6 @@ SPD_MEMORY_TYPE_SDRAM_DDR) continue; -#ifdef VALIDATE_DIMM_COMPATIBILITY if (smbus_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) != SPD_VOLTAGE_SSTL2) continue; // Unsupported voltage @@ -586,7 +573,7 @@ && (sdram_width.side2 != 8)) continue; } -#endif + // Channel 0 DIMM looks compatible. // Now see if it is paired with the proper DIMM on channel 1. @@ -599,7 +586,7 @@ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n"); continue; } -#ifdef VALIDATE_DIMM_COMPATIBILITY + spd_value = smbus_read_byte(channel1_dimm, SPD_SUPPORTED_BURST_LENGTHS); if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0)) @@ -615,7 +602,6 @@ break; } } -#endif /* VALIDATE_DIMM_COMPATIBILITY */ if (bDualChannel) { // This DIMM pair is usable -- To view, visit https://review.coreboot.org/c/coreboot/+/38295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4862b4f0a029f6f4a1ff7e66cf814fa8f5686d3f Gerrit-Change-Number: 38295 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/e7505: Remove commented out suspicious code
by Kyösti Mälkki (Code Review) 12 Jan '20

12 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38294 ) Change subject: intel/e7505: Remove commented out suspicious code ...................................................................... intel/e7505: Remove commented out suspicious code Change-Id: I566f016eb4fb710a5246be8b088ab0d2ed00041c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/e7505/raminit.c 1 file changed, 0 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/38294/1 diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 7953aca..517ba6f 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -1257,21 +1257,6 @@ refresh_frequency[system_refresh_mode]) system_refresh_mode = dimm_refresh_mode; -#ifdef SUSPICIOUS_LOOKING_CODE -// SJM NOTE: This code doesn't look right. SPD values are an order of magnitude smaller -// than the clock period of the memory controller. Also, no other northbridge -// looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME. - - // Switch to 2 clocks for address/command if required by any one of the DIMMs - // NOTE: At 133 MHz, 1 clock == 7.52 ns - value = smbus_read_byte(dimm_socket_address, - SPD_CMD_SIGNAL_INPUT_HOLD_TIME); - die_on_spd_error(value); - if (value >= 0xa0) { /* At 133MHz this constant should be 0x75 */ - controller_mode &= ~(1 << 16); /* Use two clock cycles instead of one */ - } -#endif - /* go to the next DIMM */ } @@ -1724,17 +1709,6 @@ byte &= ~0x60; pci_write_config8(MCHDEV, 0xd9, byte); -#ifdef SUSPICIOUS_LOOKING_CODE - /* This will access D2:F0:0x50, is this correct?? - * Vendor BIOS reads Device ID before this is set. - * Undocumented in the p64h2 PCI-X bridge datasheet. - */ - byte = pci_read_config8(PCI_DEV(0,2,0), 0x50); - byte &= 0xcf; - byte |= 0x30 - pci_write_config8(PCI_DEV(0,2,0), 0x50, byte); -#endif - uint8_t revision = pci_read_config8(MCHDEV, 0x08); if (revision >= 3) d060_control(D060_CMD_1); -- To view, visit https://review.coreboot.org/c/coreboot/+/38294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I566f016eb4fb710a5246be8b088ab0d2ed00041c Gerrit-Change-Number: 38294 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/e7505,i82801dx: Refactor raminit
by Kyösti Mälkki (Code Review) 12 Jan '20

12 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38267 ) Change subject: intel/e7505,i82801dx: Refactor raminit ...................................................................... intel/e7505,i82801dx: Refactor raminit Change-Id: I077e455242db9fc0f86432bd1afab75cb6fb6f4c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/e7505/raminit.h M src/northbridge/intel/e7505/romstage.c M src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801dx/i82801dx.h 5 files changed, 43 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/38267/1 diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 6b7a041..9d82634 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -1759,28 +1759,38 @@ d060_control(D060_CMD_1); } -/** - * - * - */ -void e7505_mch_init(const struct mem_controller *memctrl) -{ - timestamp_add_now(TS_BEFORE_INITRAM); - - sdram_set_registers(memctrl); - sdram_set_spd_registers(memctrl); - sdram_enable(memctrl); -} - -void e7505_mch_done(const struct mem_controller *memctrl) -{ - sdram_post_ecc(memctrl); - - timestamp_add_now(TS_AFTER_INITRAM); -} - -int e7505_mch_is_ready(void) +static int e7505_mch_is_ready(void) { uint32_t dword = pci_read_config32(MCHDEV, DRC); return !!(dword & DRC_DONE); } + +void sdram_initialize(void) +{ + static const struct mem_controller memctrl[] = { + { + .d0 = PCI_DEV(0, 0, 0), + .d0f1 = PCI_DEV(0, 0, 1), + .channel0 = { 0x50, 0x52, 0, 0 }, + .channel1 = { 0x51, 0x53, 0, 0 }, + }, + }; + + /* If this is a warm boot, some initialization can be skipped */ + if (!e7505_mch_is_ready()) { + + /* The real MCH initialisation. */ + timestamp_add_now(TS_BEFORE_INITRAM); + + sdram_set_registers(memctrl); + sdram_set_spd_registers(memctrl); + sdram_enable(memctrl); + + /* Hook for post ECC scrub settings and debug. */ + sdram_post_ecc(memctrl); + + timestamp_add_now(TS_AFTER_INITRAM); + } + + printk(BIOS_DEBUG, "SDRAM is up.\n"); +} diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index c65675f..9aa6eb4 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -30,8 +30,6 @@ uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL]; }; -void e7505_mch_init(const struct mem_controller *memctrl); -void e7505_mch_done(const struct mem_controller *memctrl); -int e7505_mch_is_ready(void); +void sdram_initialize(void); #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/e7505/romstage.c b/src/northbridge/intel/e7505/romstage.c index 6c74c1f..f506bf4 100644 --- a/src/northbridge/intel/e7505/romstage.c +++ b/src/northbridge/intel/e7505/romstage.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#include <stdint.h> #include <cbmem.h> -#include <console/console.h> #include <arch/romstage.h> #include <southbridge/intel/i82801dx/i82801dx.h> @@ -23,27 +21,12 @@ void mainboard_romstage_entry(void) { - static const struct mem_controller memctrl[] = { - { - .d0 = PCI_DEV(0, 0, 0), - .d0f1 = PCI_DEV(0, 0, 1), - .channel0 = { 0x50, 0x52, 0, 0 }, - .channel1 = { 0x51, 0x53, 0, 0 }, - }, - }; + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + i82801dx_early_init(); - /* If this is a warm boot, some initialization can be skipped */ - if (!e7505_mch_is_ready()) { - enable_smbus(); - - /* The real MCH initialisation. */ - e7505_mch_init(memctrl); - - /* Hook for post ECC scrub settings and debug. */ - e7505_mch_done(memctrl); - } - - printk(BIOS_DEBUG, "SDRAM is up.\n"); + sdram_initialize(); cbmem_recovery(0); } diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index 77b0aa0..de0bc93 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -21,6 +21,11 @@ #include "i82801dx.h" +void i82801dx_early_init(void) +{ + enable_smbus(); +} + void enable_smbus(void) { pci_devfn_t dev = PCI_DEV(0x0, 0x1f, 0x3); diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 50122d8..8717e59 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -35,6 +35,7 @@ #include "chip.h" void i82801dx_enable(struct device *dev); +void i82801dx_early_init(void); void enable_smbus(void); int smbus_read_byte(unsigned int device, unsigned int address); void aseg_smm_lock(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/38267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I077e455242db9fc0f86432bd1afab75cb6fb6f4c Gerrit-Change-Number: 38267 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: aopen/dxplplusu,intel/e7505: Move mainboard_romstage_entry()
by Kyösti Mälkki (Code Review) 12 Jan '20

12 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38266 ) Change subject: aopen/dxplplusu,intel/e7505: Move mainboard_romstage_entry() ...................................................................... aopen/dxplplusu,intel/e7505: Move mainboard_romstage_entry() Change-Id: I15aaefdf0c81f58adfeb6f4dde2f05b3c06fd145 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/e7505/Makefile.inc R src/northbridge/intel/e7505/romstage.c 2 files changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/38266/1 diff --git a/src/northbridge/intel/e7505/Makefile.inc b/src/northbridge/intel/e7505/Makefile.inc index 9b68e13..29ac437 100644 --- a/src/northbridge/intel/e7505/Makefile.inc +++ b/src/northbridge/intel/e7505/Makefile.inc @@ -3,6 +3,7 @@ ramstage-y += northbridge.c ramstage-y += memmap.c +romstage-y += romstage.c romstage-y += raminit.c romstage-y += memmap.c diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/northbridge/intel/e7505/romstage.c similarity index 100% rename from src/mainboard/aopen/dxplplusu/romstage.c rename to src/northbridge/intel/e7505/romstage.c -- To view, visit https://review.coreboot.org/c/coreboot/+/38266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15aaefdf0c81f58adfeb6f4dde2f05b3c06fd145 Gerrit-Change-Number: 38266 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/e7505,i82801dx: Remove wrapper spd_read_byte()
by Kyösti Mälkki (Code Review) 12 Jan '20

12 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38235 ) Change subject: intel/e7505,i82801dx: Remove wrapper spd_read_byte() ...................................................................... intel/e7505,i82801dx: Remove wrapper spd_read_byte() Change-Id: I4a2d3043f77c9aa9c93b4718c5742fbd8d69b79f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/aopen/dxplplusu/romstage.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/e7505/raminit.h 3 files changed, 30 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/38235/1 diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index c647f96..0df6410 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -17,16 +17,10 @@ #include <cbmem.h> #include <console/console.h> #include <device/pci_type.h> -#include <device/smbus_host.h> #include <arch/romstage.h> #include <northbridge/intel/e7505/raminit.h> -int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - void mainboard_romstage_entry(void) { static const struct mem_controller memctrl[] = { @@ -40,7 +34,6 @@ /* If this is a warm boot, some initialization can be skipped */ if (!e7505_mch_is_ready()) { - enable_smbus(); /* The real MCH initialisation. */ e7505_mch_init(memctrl); diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 051b206..d8abc22 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -29,6 +29,7 @@ #include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> +#include <device/smbus_host.h> #include <lib.h> #include <commonlib/helpers.h> #include <console/console.h> @@ -338,20 +339,20 @@ pgsz.side2 = 0; // Side 1 - value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); + value = smbus_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); if (value < 0) goto hw_err; pgsz.side1 = value & 0xf; // # columns in bank 1 /* Get the module data width and convert it to a power of two */ value = - spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB); + smbus_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB); if (value < 0) goto hw_err; module_data_width = (value & 0xff) << 8; value = - spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB); + smbus_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB); if (value < 0) goto hw_err; module_data_width |= (value & 0xff); @@ -359,7 +360,7 @@ pgsz.side1 += log2(module_data_width); /* side two */ - value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); + value = smbus_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); if (value < 0) goto hw_err; if (value > 2) @@ -368,7 +369,7 @@ pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently value = - spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); + smbus_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); if (value < 0) goto hw_err; if ((value & 0xf0) != 0) { @@ -400,7 +401,7 @@ width.side2 = 0; value = - spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH); + smbus_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH); die_on_spd_error(value); width.side1 = value & 0x7f; // Mask off bank 2 flag @@ -410,7 +411,7 @@ } else { // If bank 2 exists, it's the same width as bank 1 value = - spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); + smbus_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); die_on_spd_error(value); if (value == 2) @@ -442,7 +443,7 @@ if (sz.side1 > 0) { - value = spd_read_byte(dimm_socket_address, SPD_NUM_ROWS); + value = smbus_read_byte(dimm_socket_address, SPD_NUM_ROWS); die_on_spd_error(value); sz.side1 += value & 0xf; @@ -457,7 +458,7 @@ } value = - spd_read_byte(dimm_socket_address, + smbus_read_byte(dimm_socket_address, SPD_NUM_BANKS_PER_SDRAM); die_on_spd_error(value); @@ -486,8 +487,8 @@ uint16_t dimm1_address) { uint8_t bEqual = 0; - int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number); - int dimm1_value = spd_read_byte(dimm1_address, spd_byte_number); + int dimm0_value = smbus_read_byte(dimm0_address, spd_byte_number); + int dimm1_value = smbus_read_byte(dimm1_address, spd_byte_number); if ((dimm0_value >= 0) && (dimm1_value >= 0) && (dimm0_value == dimm1_value)) @@ -541,25 +542,25 @@ if (channel0_dimm == 0) continue; // No such socket on this mainboard - if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != + if (smbus_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR) continue; #ifdef VALIDATE_DIMM_COMPATIBILITY - if (spd_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) != + if (smbus_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) != SPD_VOLTAGE_SSTL2) continue; // Unsupported voltage // E7501 does not support unregistered DIMMs spd_value = - spd_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES); + smbus_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES); if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) continue; // Must support burst = 4 for dual-channel operation on E7501 // NOTE: for single-channel, burst = 8 is required spd_value = - spd_read_byte(channel0_dimm, + smbus_read_byte(channel0_dimm, SPD_SUPPORTED_BURST_LENGTHS); if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0)) continue; @@ -601,7 +602,7 @@ // NOTE: unpopulated DIMMs cause read to fail spd_value = - spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES); + smbus_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES); if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) { printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n"); @@ -609,7 +610,7 @@ } #ifdef VALIDATE_DIMM_COMPATIBILITY spd_value = - spd_read_byte(channel1_dimm, + smbus_read_byte(channel1_dimm, SPD_SUPPORTED_BURST_LENGTHS); if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0)) continue; @@ -943,7 +944,7 @@ ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL]; value = - spd_read_byte(dimm_socket_address, + smbus_read_byte(dimm_socket_address, SPD_MIN_ROW_PRECHARGE_TIME); if (value < 0) goto hw_err; @@ -951,7 +952,7 @@ slowest_row_precharge = value; value = - spd_read_byte(dimm_socket_address, + smbus_read_byte(dimm_socket_address, SPD_MIN_RAS_TO_CAS_DELAY); if (value < 0) goto hw_err; @@ -959,7 +960,7 @@ slowest_ras_cas_delay = value; value = - spd_read_byte(dimm_socket_address, + smbus_read_byte(dimm_socket_address, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); if (value < 0) goto hw_err; @@ -1076,7 +1077,7 @@ ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL]; value = - spd_read_byte(dimm_socket_address, + smbus_read_byte(dimm_socket_address, SPD_ACCEPTABLE_CAS_LATENCIES); if (value < 0) goto hw_err; @@ -1087,7 +1088,7 @@ // Can we support the highest CAS# latency? value = - spd_read_byte(dimm_socket_address, + smbus_read_byte(dimm_socket_address, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); if (value < 0) goto hw_err; @@ -1103,7 +1104,7 @@ current_cas_latency >>= 1; if (current_cas_latency != 0) { value = - spd_read_byte(dimm_socket_address, + smbus_read_byte(dimm_socket_address, SPD_SDRAM_CYCLE_TIME_2ND); if (value < 0) goto hw_err; @@ -1115,7 +1116,7 @@ current_cas_latency >>= 1; if (current_cas_latency != 0) { value = - spd_read_byte(dimm_socket_address, + smbus_read_byte(dimm_socket_address, SPD_SDRAM_CYCLE_TIME_3RD); if (value < 0) goto hw_err; @@ -1248,14 +1249,14 @@ // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported. value = - spd_read_byte(dimm_socket_address, + smbus_read_byte(dimm_socket_address, SPD_DIMM_CONFIG_TYPE); die_on_spd_error(value); if (value != ERROR_SCHEME_ECC) { controller_mode &= ~(3 << 20); } - value = spd_read_byte(dimm_socket_address, SPD_REFRESH); + value = smbus_read_byte(dimm_socket_address, SPD_REFRESH); die_on_spd_error(value); value &= 0x7f; // Mask off self-refresh bit if (value > MAX_SPD_REFRESH_RATE) { @@ -1282,7 +1283,7 @@ // Switch to 2 clocks for address/command if required by any one of the DIMMs // NOTE: At 133 MHz, 1 clock == 7.52 ns value = - spd_read_byte(dimm_socket_address, + smbus_read_byte(dimm_socket_address, SPD_CMD_SIGNAL_INPUT_HOLD_TIME); die_on_spd_error(value); if (value >= 0xa0) { /* At 133MHz this constant should be 0x75 */ @@ -1766,6 +1767,8 @@ { timestamp_add_now(TS_BEFORE_INITRAM); + enable_smbus(); + sdram_set_registers(memctrl); sdram_set_spd_registers(memctrl); sdram_enable(memctrl); diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index f3fc264..c65675f 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -34,8 +34,4 @@ void e7505_mch_done(const struct mem_controller *memctrl); int e7505_mch_is_ready(void); - -/* Mainboard exports this. */ -int spd_read_byte(unsigned int device, unsigned int address); - #endif /* RAMINIT_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a2d3043f77c9aa9c93b4718c5742fbd8d69b79f Gerrit-Change-Number: 38235 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: asus/p2b-x,p3b,intel/i440bx: Move mainboard_romstage_entry()
by Kyösti Mälkki (Code Review) 12 Jan '20

12 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38255 ) Change subject: asus/p2b-x,p3b,intel/i440bx: Move mainboard_romstage_entry() ...................................................................... asus/p2b-x,p3b,intel/i440bx: Move mainboard_romstage_entry() Change-Id: I3598f548c2d122906fda09c85b5a1c82b0da993b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/asus/p2b-ds/romstage.c M src/mainboard/asus/p2b-ls/romstage.c M src/mainboard/asus/p2b/romstage.c M src/mainboard/asus/p3b-f/romstage.c M src/northbridge/intel/i440bx/Makefile.inc M src/northbridge/intel/i440bx/raminit.c M src/northbridge/intel/i440bx/raminit.h A src/northbridge/intel/i440bx/romstage.c M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82371eb/i82371eb.h 10 files changed, 46 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/38255/1 diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index 36f45a0..d0456e5 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -14,22 +14,13 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <arch/romstage.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> -#include <cbmem.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -void mainboard_romstage_entry(void) +void mainboard_enable_serial(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - enable_smbus(); - sdram_initialize(); - cbmem_initialize_empty(); } diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index 87cb753..b79ac82 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -14,23 +14,14 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <arch/romstage.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ #include <superio/winbond/w83977tf/w83977tf.h> -#include <cbmem.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -void mainboard_romstage_entry(void) +void mainboard_enable_serial(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - enable_smbus(); - sdram_initialize(); - cbmem_initialize_empty(); } diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 8cbc596..fbd7124 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -14,22 +14,13 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <arch/romstage.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> -#include <cbmem.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -void mainboard_romstage_entry(void) +void mainboard_enable_serial(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - enable_smbus(); - sdram_initialize(); - cbmem_initialize_empty(); } diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index e9c41b1..209dd96 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -15,14 +15,11 @@ */ #include <arch/io.h> -#include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include <arch/romstage.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ #include <superio/winbond/w83977tf/w83977tf.h> -#include <cbmem.h> /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) @@ -58,16 +55,7 @@ outb(0x67, PM_IO_BASE + 0x37); } -void mainboard_romstage_entry(void) +void mainboard_enable_serial(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - - enable_smbus(); - enable_pm(); - - - sdram_initialize(); - - cbmem_initialize_empty(); } diff --git a/src/northbridge/intel/i440bx/Makefile.inc b/src/northbridge/intel/i440bx/Makefile.inc index 355d9b2..5702585 100644 --- a/src/northbridge/intel/i440bx/Makefile.inc +++ b/src/northbridge/intel/i440bx/Makefile.inc @@ -19,6 +19,7 @@ ramstage-y += northbridge.c romstage-y += raminit.c +romstage-y += romstage.c romstage-$(CONFIG_DEBUG_RAM_SETUP) += debug.c romstage-y += memmap.c diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 0801988..597ba94 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -667,7 +667,7 @@ Public interface. -----------------------------------------------------------------------------*/ -void sdram_set_registers(void) +static void sdram_set_registers(void) { int i, max; uint8_t reg; @@ -977,7 +977,7 @@ PRINT_DEBUG("DRAMC has been set to 0x%02x\n", value); } -void sdram_set_spd_registers(void) +static void sdram_set_spd_registers(void) { /* Setup DRAM row boundary registers and other attributes. */ set_dram_row_attributes(); @@ -993,7 +993,7 @@ pci_write_config8(NB, DRAMT, 0x03); } -void sdram_enable(void) +static void sdram_enable(void) { int i; diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index 347c1fe..1e9f25b 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -22,13 +22,8 @@ void enable_spd(void); void disable_spd(void); - -/* Function prototypes. */ -void sdram_set_registers(void); -void sdram_set_spd_registers(void); -void sdram_enable(void); -/* A merger of above functions */ void sdram_initialize(void); +void mainboard_enable_serial(void); /* Debug */ #if CONFIG(DEBUG_RAM_SETUP) diff --git a/src/northbridge/intel/i440bx/romstage.c b/src/northbridge/intel/i440bx/romstage.c new file mode 100644 index 0000000..1dee03a --- /dev/null +++ b/src/northbridge/intel/i440bx/romstage.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/romstage.h> +#include <cbmem.h> +#include <console/console.h> +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> + +void mainboard_romstage_entry(void) +{ + mainboard_enable_serial(); + console_init(); + + i82371eb_early_init(); + + sdram_initialize(); + cbmem_initialize_empty(); +} diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index 917a3b4..f69cb93 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -23,6 +23,12 @@ #include <device/smbus_host.h> #include "i82371eb.h" +void i82371eb_early_init(void) +{ + enable_smbus(); + enable_pm(); +} + void enable_smbus(void) { pci_devfn_t dev; diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 55242ef..b292beb 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -21,6 +21,7 @@ void enable_smbus(void); void enable_pm(void); +void i82371eb_early_init(void); #if ENV_ROMSTAGE int smbus_read_byte(u8 device, u8 address); -- To view, visit https://review.coreboot.org/c/coreboot/+/38255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3598f548c2d122906fda09c85b5a1c82b0da993b Gerrit-Change-Number: 38255 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: intel/i440bx,i82371: Remove wrapper spd_read_byte()
by Kyösti Mälkki (Code Review) 12 Jan '20

12 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38234 ) Change subject: intel/i440bx,i82371: Remove wrapper spd_read_byte() ...................................................................... intel/i440bx,i82371: Remove wrapper spd_read_byte() Change-Id: Ib94ce73eb22c5b4b489dbd871279e8cd9a7010a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/asus/p2b-ds/romstage.c M src/mainboard/asus/p2b-ls/romstage.c M src/mainboard/asus/p2b/romstage.c M src/mainboard/asus/p3b-f/romstage.c M src/northbridge/intel/i440bx/raminit.c M src/northbridge/intel/i440bx/raminit.h 6 files changed, 14 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/38234/1 diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index 5fed7c5..80435bf 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -15,7 +15,6 @@ */ #include <console/console.h> -#include <device/smbus_host.h> #include <northbridge/intel/i440bx/raminit.h> #include <arch/romstage.h> #include <superio/winbond/common/winbond.h> @@ -24,17 +23,11 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - void mainboard_romstage_entry(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); - enable_smbus(); sdram_initialize(); cbmem_initialize_empty(); } diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index 4e5c355..e5d0317 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -15,7 +15,6 @@ */ #include <console/console.h> -#include <device/smbus_host.h> #include <northbridge/intel/i440bx/raminit.h> #include <arch/romstage.h> #include <superio/winbond/common/winbond.h> @@ -25,17 +24,11 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - void mainboard_romstage_entry(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); - enable_smbus(); sdram_initialize(); cbmem_initialize_empty(); } diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 971255a4..ac98331 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -15,7 +15,6 @@ */ #include <console/console.h> -#include <device/smbus_host.h> #include <northbridge/intel/i440bx/raminit.h> #include <arch/romstage.h> #include <superio/winbond/common/winbond.h> @@ -24,17 +23,11 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - void mainboard_romstage_entry(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); - enable_smbus(); sdram_initialize(); cbmem_initialize_empty(); } diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 4645450..9d6c609 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -16,7 +16,6 @@ #include <arch/io.h> #include <console/console.h> -#include <device/smbus_host.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include <arch/romstage.h> @@ -28,11 +27,6 @@ /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - /* * ASUS P3B-F specific SPD enable magic. * @@ -69,7 +63,6 @@ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); - enable_smbus(); enable_pm(); enable_spd(); diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 0f9f2f6..c90202e 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -21,6 +21,7 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <device/pci_def.h> +#include <device/smbus_host.h> #include <console/console.h> #include "i440bx.h" #include "raminit.h" @@ -650,7 +651,7 @@ reg = pci_read_config8(NB, DRAMC); for (i = 0; i < DIMM_SOCKETS; i++) { - value = spd_read_byte(DIMM0 + i, SPD_REFRESH); + value = smbus_read_byte(DIMM0 + i, SPD_REFRESH); if (value < 0) continue; reg = (reg & 0xf8) | refresh_rate_map[(value & 0x7f)]; @@ -694,8 +695,8 @@ struct dimm_size sz; int i, module_density, dimm_banks; sz.side1 = 0; - module_density = spd_read_byte(device, SPD_DENSITY_OF_EACH_ROW_ON_MODULE); - dimm_banks = spd_read_byte(device, SPD_NUM_DIMM_BANKS); + module_density = smbus_read_byte(device, SPD_DENSITY_OF_EACH_ROW_ON_MODULE); + dimm_banks = smbus_read_byte(device, SPD_NUM_DIMM_BANKS); /* Find the size of side1. */ /* Find the larger value. The larger value is always side1. */ @@ -780,7 +781,7 @@ nbxecc >>= 2; /* First check if a DIMM is actually present. */ - value = spd_read_byte(device, SPD_MEMORY_TYPE); + value = smbus_read_byte(device, SPD_MEMORY_TYPE); /* This is 440BX! We do EDO too! */ if (value == SPD_MEMORY_TYPE_EDO || value == SPD_MEMORY_TYPE_SDRAM) { @@ -801,21 +802,21 @@ dra = 0; /* Columns */ - col = spd_read_byte(device, SPD_NUM_COLUMNS); + col = smbus_read_byte(device, SPD_NUM_COLUMNS); /* * Is this an ECC DIMM? Actually will be a 2 if so. * TODO: Other register than NBXCFG also needs this * ECC information. */ - value = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE); + value = smbus_read_byte(device, SPD_DIMM_CONFIG_TYPE); /* Data width */ - width = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); + width = smbus_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); /* Exclude error checking data width from page size calculations */ if (value) { - value = spd_read_byte(device, + value = smbus_read_byte(device, SPD_ERROR_CHECKING_SDRAM_WIDTH); width -= value; /* ### ECC */ @@ -831,7 +832,7 @@ * By registered, only the address and control lines need to be, which * we can tell by reading SPD byte 21, bit 1. */ - value = spd_read_byte(device, SPD_MODULE_ATTRIBUTES); + value = smbus_read_byte(device, SPD_MODULE_ATTRIBUTES); PRINT_DEBUG("DIMM is "); if ((value & MODULE_REGISTERED) == 0) { @@ -847,12 +848,12 @@ dra = (value >> 13); /* Number of banks of DIMM (single or double sided). */ - value = spd_read_byte(device, SPD_NUM_DIMM_BANKS); + value = smbus_read_byte(device, SPD_NUM_DIMM_BANKS); /* Once we have dra, col is done and can be reused. * So it's reused for number of banks. */ - col = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); + col = smbus_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); if (value == 1) { /* @@ -1037,6 +1038,8 @@ void sdram_initialize(void) { + enable_smbus(); + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index 448f8d6..d490648 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -21,7 +21,6 @@ #define DIMM_SOCKETS 4 /* Function prototypes. */ -int spd_read_byte(unsigned int device, unsigned int address); void sdram_set_registers(void); void sdram_set_spd_registers(void); void sdram_enable(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/38234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib94ce73eb22c5b4b489dbd871279e8cd9a7010a7 Gerrit-Change-Number: 38234 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: asus/p3b-f,intel/i440bx: Move enable/disable_spd() call
by Kyösti Mälkki (Code Review) 12 Jan '20

12 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38254 ) Change subject: asus/p3b-f,intel/i440bx: Move enable/disable_spd() call ...................................................................... asus/p3b-f,intel/i440bx: Move enable/disable_spd() call Change-Id: I4a324dcebcd53439206205e64c5bbb7c6eac4fb2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/asus/p3b-f/romstage.c M src/northbridge/intel/i440bx/raminit.c M src/northbridge/intel/i440bx/raminit.h 3 files changed, 13 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/38254/1 diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index e9630bf..8e254ba 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -49,7 +49,7 @@ * 24-30 of the PIIX4E (bit 31 is reserved). Thus, GPIOs 27 and 28 * control which SMBus/I2C offsets can be accessed. */ -static void enable_spd(void) +void enable_spd(void) { outb(0x6f, PM_IO_BASE + 0x37); } @@ -58,7 +58,7 @@ * Disable SPD access after RAM init to allow access to SMBus/I2C offsets * 0x48/0x49/0x2d, which is required e.g. by lm-sensors. */ -static void disable_spd(void) +void disable_spd(void) { outb(0x67, PM_IO_BASE + 0x37); } @@ -71,10 +71,8 @@ enable_smbus(); enable_pm(); - enable_spd(); sdram_initialize(); - disable_spd(); cbmem_initialize_empty(); } diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 0f9f2f6..28b22ec 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -1035,10 +1035,18 @@ DUMPNORTH(); } +/* Implemented under mainboard. */ +void __weak enable_spd(void) { } +void __weak disable_spd(void) { } + void sdram_initialize(void) { + enable_spd(); + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); + + disable_spd(); } diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index 448f8d6..23299d1 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -20,6 +20,9 @@ /* The 440BX supports up to four (single- or double-sided) DIMMs. */ #define DIMM_SOCKETS 4 +void enable_spd(void); +void disable_spd(void); + /* Function prototypes. */ int spd_read_byte(unsigned int device, unsigned int address); void sdram_set_registers(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/38254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a324dcebcd53439206205e64c5bbb7c6eac4fb2 Gerrit-Change-Number: 38254 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/common: Move SMBUS register layout outside header
by Kyösti Mälkki (Code Review) 12 Jan '20

12 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38231 ) Change subject: sb/intel/common: Move SMBUS register layout outside header ...................................................................... sb/intel/common: Move SMBUS register layout outside header Change-Id: I841cc3bd636414c59af15d64d3f96b9be158af98 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/common/smbus.c D src/southbridge/intel/common/smbus.h 2 files changed, 16 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/38231/1 diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index 1085cbd..374eea6 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -22,15 +22,28 @@ #include <device/smbus_host.h> #include <types.h> -#include "smbus.h" - - #if CONFIG(DEBUG_SMBUS) #define dprintk(args...) printk(BIOS_DEBUG, ##args) #else #define dprintk(args...) do {} while (0) #endif +/* SMBus register offsets. */ +#define SMBHSTSTAT 0x0 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf +#define SMBSLVCMD 0x11 + +#define SMB_RCV_SLVA SMBTRNSADD + /* I801 command constants */ #define I801_QUICK (0 << 2) #define I801_BYTE (1 << 2) diff --git a/src/southbridge/intel/common/smbus.h b/src/southbridge/intel/common/smbus.h deleted file mode 100644 index e72203e4..0000000 --- a/src/southbridge/intel/common/smbus.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Yinghai Lu <yinghailu(a)gmail.com> - * Copyright (C) 2009 coresystems GmbH - * Copyright (C) 2013 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef INTEL_COMMON_SMBUS_H -#define INTEL_COMMON_SMBUS_H - -/* SMBus register offsets. */ -#define SMBHSTSTAT 0x0 -#define SMBHSTCTL 0x2 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBBLKDAT 0x7 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf -#define SMBSLVCMD 0x11 - -#define SMB_RCV_SLVA SMBTRNSADD - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/38231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I841cc3bd636414c59af15d64d3f96b9be158af98 Gerrit-Change-Number: 38231 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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