coreboot-gerrit January 2020

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Change in coreboot[master]: mb/asrock/g41c-gs/acpi_tables.c: Remove unneeded includes
by Nico Huber (Code Review) 13 Jan '20

13 Jan '20

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/26900 ) Change subject: mb/asrock/g41c-gs/acpi_tables.c: Remove unneeded includes ...................................................................... mb/asrock/g41c-gs/acpi_tables.c: Remove unneeded includes Change-Id: Icd9efdf5fb4d57756704c62b5f575a3835a8ce11 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26900 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/g41c-gs/acpi_tables.c 1 file changed, 0 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/asrock/g41c-gs/acpi_tables.c b/src/mainboard/asrock/g41c-gs/acpi_tables.c index d90dbc4..dede317 100644 --- a/src/mainboard/asrock/g41c-gs/acpi_tables.c +++ b/src/mainboard/asrock/g41c-gs/acpi_tables.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <string.h> #include <southbridge/intel/i82801gx/nvs.h> void acpi_create_gnvs(global_nvs_t *gnvs) -- To view, visit https://review.coreboot.org/c/coreboot/+/26900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd9efdf5fb4d57756704c62b5f575a3835a8ce11 Gerrit-Change-Number: 26900 Gerrit-PatchSet: 6 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/asus/p8z77-m_pro: Fix typos
by HAOUAS Elyes (Code Review) 13 Jan '20

13 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38364 ) Change subject: mb/asus/p8z77-m_pro: Fix typos ...................................................................... mb/asus/p8z77-m_pro: Fix typos Change-Id: I3c63ca745bf10ec0b0c4cef898db3f7ebfee5bde Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asus/p8z77-m_pro/early_init.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/38364/1 diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c index e60f2f3..800d975 100644 --- a/src/mainboard/asus/p8z77-m_pro/early_init.c +++ b/src/mainboard/asus/p8z77-m_pro/early_init.c @@ -44,8 +44,8 @@ { 1, 2, 4 }, /* Port 9: USB2 internal header USB910, bottom */ { 1, 2, 6 }, /* Port 10: USB2 internal header USB1112, top */ { 1, 2, 5 }, /* Port 11: USB2 internal header USB1112, bottom */ - { 0, 2, 5 }, /* Port 12: Unused. Asus propietary DEBUG_PORT ??? */ - { 0, 2, 6 } /* Port 13: Unused. Asus propietary DEBUG_PORT ??? */ + { 0, 2, 5 }, /* Port 12: Unused. Asus proprietary DEBUG_PORT ??? */ + { 0, 2, 6 } /* Port 13: Unused. Asus proprietary DEBUG_PORT ??? */ }; void bootblock_mainboard_early_init(void) @@ -157,7 +157,7 @@ /* ASUS P8Z77-M Pro manual says 1.35v DIMMs are supported */ .ddr3lv_support = 1, /* PCIe 3.0 support. As we use Ivy Bridge, let's enable it, - * but might cause some system inestability ! + * but might cause some system instability ! */ .pcie_init = 1, /* Command Rate. 0=Auto; 1=1N; 2=2N. -- To view, visit https://review.coreboot.org/c/coreboot/+/38364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c63ca745bf10ec0b0c4cef898db3f7ebfee5bde Gerrit-Change-Number: 38364 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/asrock/imb-a180: Fix typo
by HAOUAS Elyes (Code Review) 13 Jan '20

13 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38360 ) Change subject: mb/asrock/imb-a180: Fix typo ...................................................................... mb/asrock/imb-a180: Fix typo Change-Id: Iff032a321301772789a42f29cfc187c446b4cfa1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/asrock/imb-a180/BiosCallOuts.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/38360/1 diff --git a/src/mainboard/asrock/imb-a180/BiosCallOuts.c b/src/mainboard/asrock/imb-a180/BiosCallOuts.c index 983f9a8..1cadd6b 100644 --- a/src/mainboard/asrock/imb-a180/BiosCallOuts.c +++ b/src/mainboard/asrock/imb-a180/BiosCallOuts.c @@ -111,6 +111,6 @@ void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) { - /* Azalia Controller OEM Cqodec Table Pointer */ + /* Azalia Controller OEM Codec Table Pointer */ FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST*)CodecTableList; } -- To view, visit https://review.coreboot.org/c/coreboot/+/38360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff032a321301772789a42f29cfc187c446b4cfa1 Gerrit-Change-Number: 38360 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: arch/x86/cf9_reset: Fix typo
by HAOUAS Elyes (Code Review) 13 Jan '20

13 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38311 ) Change subject: arch/x86/cf9_reset: Fix typo ...................................................................... arch/x86/cf9_reset: Fix typo Change-Id: I4a8d29ab647837965e5341d019664f0ed401639a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/cf9_reset.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/38311/1 diff --git a/src/arch/x86/cf9_reset.c b/src/arch/x86/cf9_reset.c index ccfaa7d..d93bed7 100644 --- a/src/arch/x86/cf9_reset.c +++ b/src/arch/x86/cf9_reset.c @@ -35,7 +35,7 @@ * A full reset in terms of the CF9 register triggers a power cycle * (i.e. S0 -> S5 -> S0 transition). Thus, it could be called a * "cold reset". - * Note: Not all x86 implementations comply with this defitinion, + * Note: Not all x86 implementations comply with this definition, * some may require additional configuration to power cycle. */ void do_full_reset(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/38311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a8d29ab647837965e5341d019664f0ed401639a Gerrit-Change-Number: 38311 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: arch/x86: Fix typos
by HAOUAS Elyes (Code Review) 13 Jan '20

13 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38310 ) Change subject: arch/x86: Fix typos ...................................................................... arch/x86: Fix typos Change-Id: I944b9bf8f518eff9b539769825174bf1544e6b34 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/acpi_device.c M src/arch/x86/acpigen.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/38310/1 diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index 1d79170..d512789 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -176,7 +176,7 @@ return buf; } -/* Concatentate the device path and provided name suffix */ +/* Concatenate the device path and provided name suffix */ const char *acpi_device_path_join(const struct device *dev, const char *name) { static char buf[DEVICE_PATH_MAX] = {}; diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 493131e..2e60783 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -1006,7 +1006,7 @@ acpigen_emit_byte(WORD_PREFIX); len_stack[ltop++] = acpigen_get_current(); /* Add 2 dummy bytes for the ACPI word (keep aligned with - the calclulation in acpigen_write_resourcetemplate() below). */ + the calculation in acpigen_write_resourcetemplate() below). */ acpigen_emit_byte(0x00); acpigen_emit_byte(0x00); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I944b9bf8f518eff9b539769825174bf1544e6b34 Gerrit-Change-Number: 38310 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/facebook/monolith: Enable Speed Step and dptf
by Wim Vervoorn (Code Review) 13 Jan '20

13 Jan '20

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38131 ) Change subject: mb/facebook/monolith: Enable Speed Step and dptf ...................................................................... mb/facebook/monolith: Enable Speed Step and dptf Enable Speed Step and dptf. BUG=N/A TEST=tested using fwts on facebook monolith. Change-Id: Ia3dd195f887055448d42a7584e2c88322f0ec44b Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/mainboard/facebook/monolith/devicetree.cb 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/38131/1 diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index dbe36f0..39aac47 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -21,11 +21,14 @@ # LPC serial IRQ register "serirq_mode" = "SERIRQ_CONTINUOUS" + # Enable "Intel Speed Step Technology" + register "eist_enable" = "1" + # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" # Enable DPTF - register "dptf_enable" = "0" + register "dptf_enable" = "1" # FSP Configuration register "EnableAzalia" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/38131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3dd195f887055448d42a7584e2c88322f0ec44b Gerrit-Change-Number: 38131 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: util/lint: Enforce SPDX licenses only in src/acpi directory
by Martin Roth (Code Review) 13 Jan '20

13 Jan '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36177 ) Change subject: util/lint: Enforce SPDX licenses only in src/acpi directory ...................................................................... util/lint: Enforce SPDX licenses only in src/acpi directory Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I9241f96eed652c8ca72d4f4a94f860a875e55680 --- M util/lint/lint-stable-000-license-headers 1 file changed, 5 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/36177/1 diff --git a/util/lint/lint-stable-000-license-headers b/util/lint/lint-stable-000-license-headers index 441e679..fcaf32c 100755 --- a/util/lint/lint-stable-000-license-headers +++ b/util/lint/lint-stable-000-license-headers @@ -1,22 +1,14 @@ #!/bin/sh +# SPDX-License-Identifier: GPL-2.0-only # This file is part of the coreboot project. # -# Copyright (C) 2016 Google Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# # DESCR: Check that files have license headers +# Directories requiring SPDX Identifiers only +util/lint/lint-000-license-headers "src/acpi" SPDX_ONLY + # Top level -util/lint/lint-000-license-headers "src/acpi src/arch src/commonlib src/console \ +util/lint/lint-000-license-headers "src/arch src/commonlib src/console \ src/cpu src/device src/ec src/mainboard src/northbridge src/soc \ src/southbridge src/superio" -- To view, visit https://review.coreboot.org/c/coreboot/+/36177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9241f96eed652c8ca72d4f4a94f860a875e55680 Gerrit-Change-Number: 36177 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Make FSP Headers Consumable out of Box
by Nico Huber (Code Review) 13 Jan '20

13 Jan '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/16308 ) Change subject: drivers/intel/fsp2_0: Make FSP Headers Consumable out of Box ...................................................................... Patch Set 15: (1 comment) https://review.coreboot.org/c/coreboot/+/16308/15/src/drivers/intel/fsp2_0/… File src/drivers/intel/fsp2_0/include/fsp/soc_binding.h: https://review.coreboot.org/c/coreboot/+/16308/15/src/drivers/intel/fsp2_0/… PS15, Line 20: /* : * This file is a implementation specific header. i.e. different : * FSP implementations for different chipsets. : */ > This sounds like something I wrote, but I think this was copied from a different approach. […] Thanks, that's roughly what I imagined. I was asking because in another change (CB:37579) some more includes sneaked between the comment and `Base.h`. -- To view, visit https://review.coreboot.org/c/coreboot/+/16308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7 Gerrit-Change-Number: 16308 Gerrit-PatchSet: 15 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Mon, 13 Jan 2020 10:10:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{apl,cnl,icl,skl,tgl}: Clean up SA ASL code
by Subrata Banik (Code Review) 13 Jan '20

13 Jan '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38154 ) Change subject: soc/intel/{apl,cnl,icl,skl,tgl}: Clean up SA ASL code ...................................................................... soc/intel/{apl,cnl,icl,skl,tgl}: Clean up SA ASL code List of changes in this patch 1. Removed unused variables 2. Make use of absolute path 3. Define macros and use inside SA ASL 4. Rearranged code in nothbridge.asl to move MCRS object under _CRS Change-Id: Id74269ec5a96b087562ccdf2141233db5585ae59 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/acpi/northbridge.asl M src/soc/intel/cannonlake/acpi/northbridge.asl M src/soc/intel/icelake/acpi/northbridge.asl M src/soc/intel/skylake/acpi/systemagent.asl M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/tigerlake/acpi/northbridge.asl 6 files changed, 727 insertions(+), 792 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/38154/1 diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 2f2a064..027e2a6 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -15,112 +15,113 @@ * GNU General Public License for more details. */ - Name(_HID, EISAID("PNP0A08")) /* PCIe */ - Name(_CID, EISAID("PNP0A03")) /* PCI */ - Name(_BBN, 0) +#define BASE_64GB 0x1000000000 + +Name(_HID, EISAID("PNP0A08")) /* PCIe */ +Name(_CID, EISAID("PNP0A03")) /* PCI */ Device (MCHC) { Name (_ADR, 0x00000000) /*Dev0 Func0 */ - OperationRegion (MCHP, PCI_Config, 0x00, 0x100) - Field (MCHP, DWordAcc, NoLock, Preserve) - { - Offset(0x60), - MCNF, 32, /* PCI MMCONF base */ - Offset (0xA8), - TUUD, 64, /* Top of Upper Used Memory */ - Offset(0xB4), - BGSM, 32, /* Base of Graphics Stolen Memory */ - Offset(0xBC), - TLUD, 32, /* Top of Low Useable DRAM */ - } + OperationRegion (MCHP, PCI_Config, 0x00, 0x100) + Field (MCHP, DWordAcc, NoLock, Preserve) + { + Offset(0x60), + MCNF, 32, /* PCI MMCONF base */ + Offset (0xA8), + TUUD, 64, /* Top of Upper Used Memory */ + Offset(0xB4), + BGSM, 32, /* Base of Graphics Stolen Memory */ + Offset(0xBC), + TLUD, 32, /* Top of Low Useable DRAM */ + } } -Name (MCRS, ResourceTemplate() -{ - /* Bus Numbers */ - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,) - - /* IO Region 0 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,) - - /* PCI Config Space */ - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - /* IO Region 1 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,) - - /* VGA memory (0xa0000-0xbffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,,) - - /* Data and GFX stolen memory */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x3be00000, 0x3fffffff, 0x00000000, - 0x04200000,,, STOM) - - /* - * PCI MMIO Region (TOLUD - PCI extended base MMCONF) - * This assumes that MMCONF is placed after PCI config space, - * and that no resources are allocated after the MMCONF region. - * This works, sicne MMCONF is hardcoded to 0xe00000000. - */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PM01) - - /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */ - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x10000, 0x1ffff, 0x00000000, - 0x10000,,, PM02) -}) /* Current Resource Settings */ Method (_CRS, 0, Serialized) { + Name (MCRS, ResourceTemplate() + { + /* Bus Numbers */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,) + + /* PCI Config Space */ + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,,) + + /* Data and GFX stolen memory */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x3be00000, 0x3fffffff, 0x00000000, + 0x04200000,,, STOM) + + /* + * PCI MMIO Region (TOLUD - PCI extended base MMCONF) + * This assumes that MMCONF is placed after PCI config space, + * and that no resources are allocated after the MMCONF region. + * This works, sicne MMCONF is hardcoded to 0xe00000000. + */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PM01) + + /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x10000, 0x1ffff, 0x00000000, + 0x10000,,, PM02) + }) /* Find PCI resource area in MCRS */ - CreateDwordField (MCRS, ^PM01._MIN, PMIN) - CreateDwordField (MCRS, ^PM01._MAX, PMAX) - CreateDwordField (MCRS, ^PM01._LEN, PLEN) + CreateDwordField (MCRS, PM01._MIN, PMIN) + CreateDwordField (MCRS, PM01._MAX, PMAX) + CreateDwordField (MCRS, PM01._LEN, PLEN) /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ - And(^MCHC.TLUD, 0xFFF00000, PMIN) + And(\_SB.PCI0.MCHC.TLUD, 0xFFF00000, PMIN) /* Read MMCONF base */ - And(^MCHC.MCNF, 0xF0000000, PMAX) + And(\_SB.PCI0.MCHC.MCNF, 0xF0000000, PMAX) /* Calculate PCI MMIO Length */ Add(Subtract(PMAX, PMIN), 1, PLEN) /* Find GFX resource area in GCRS */ - CreateDwordField(MCRS, ^STOM._MIN, GMIN) - CreateDwordField(MCRS, ^STOM._MAX, GMAX) - CreateDwordField(MCRS, ^STOM._LEN, GLEN) + CreateDwordField(MCRS, STOM._MIN, GMIN) + CreateDwordField(MCRS, STOM._MAX, GMAX) + CreateDwordField(MCRS, STOM._LEN, GLEN) /* Read BGSM */ - And(^MCHC.BGSM, 0xFFF00000, GMIN) + And(\_SB.PCI0.MCHC.BGSM, 0xFFF00000, GMIN) /* Read TOLUD */ - And(^MCHC.TLUD, 0xFFF00000, GMAX) + And(\_SB.PCI0.MCHC.TLUD, 0xFFF00000, GMAX) Decrement(GMAX) Add(Subtract(GMAX, GMIN), 1, GLEN) /* Patch PM02 range based on Memory Size */ - CreateQwordField (MCRS, ^PM02._MIN, MMIN) - CreateQwordField (MCRS, ^PM02._MAX, MMAX) - CreateQwordField (MCRS, ^PM02._LEN, MLEN) + CreateQwordField (MCRS, PM02._MIN, MMIN) + CreateQwordField (MCRS, PM02._MAX, MMAX) + CreateQwordField (MCRS, PM02._LEN, MLEN) - Store (^MCHC.TUUD, Local0) + Store (\_SB.PCI0.MCHC.TUUD, Local0) - If (LLessEqual (Local0, 0x1000000000)) + If (LLessEqual (Local0, BASE_64GB)) { Store (0, MMIN) Store (0, MLEN) diff --git a/src/soc/intel/cannonlake/acpi/northbridge.asl b/src/soc/intel/cannonlake/acpi/northbridge.asl index 2529116..ead5c02 100644 --- a/src/soc/intel/cannonlake/acpi/northbridge.asl +++ b/src/soc/intel/cannonlake/acpi/northbridge.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. + * Copyright (C) 2017-2020 Intel Corp. * (Written by Bora Guvendik <bora.guvendik(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -62,154 +62,154 @@ } } -Name (MCRS, ResourceTemplate () -{ - /* Bus Numbers */ - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100) - - /* IO Region 0 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, - EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8) - - /* PCI Config Space */ - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - /* IO Region 1 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, - EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300) - - /* VGA memory (0xa0000-0xbffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000) - - /* OPROM reserved (0xc0000-0xc3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xc4000-0xc7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xc8000-0xcbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xcc000-0xcffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd0000-0xd3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd4000-0xd7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd8000-0xdbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xdc000-0xdffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe0000-0xe3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe4000-0xe7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe8000-0xebfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xec000-0xeffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000) - - /* System BIOS (0xf0000-0xfffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000) - - /* PCI Memory Region (TLUD - 0xdfffffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, - 0xE0000000,,, PM01) - - /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */ - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x10000, 0x1ffff, 0x00000000, - 0x10000,,, PM02) - - /* PCH reserved resource (0xfc800000-0xfe7fffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff, - 0x00000000, PCH_PRESERVED_BASE_SIZE) - - /* TPM Area (0xfed40000-0xfed47fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000, - 0x00008000) -}) - Method (_CRS, 0, Serialized) { + Name (MCRS, ResourceTemplate () + { + /* Bus Numbers */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8) + + /* PCI Config Space */ + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000) + + /* OPROM reserved (0xc0000-0xc3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xc4000-0xc7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xc8000-0xcbfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xcc000-0xcffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd0000-0xd3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd4000-0xd7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd8000-0xdbfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xdc000-0xdffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe0000-0xe3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe4000-0xe7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe8000-0xebfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xec000-0xeffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000) + + /* System BIOS (0xf0000-0xfffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000) + + /* PCI Memory Region (TLUD - 0xdfffffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, + 0xE0000000,,, PM01) + + /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x10000, 0x1ffff, 0x00000000, + 0x10000,,, PM02) + + /* PCH reserved resource (0xfc800000-0xfe7fffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff, + 0x00000000, PCH_PRESERVED_BASE_SIZE) + + /* TPM Area (0xfed40000-0xfed47fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000, + 0x00008000) + }) + /* Find PCI resource area in MCRS */ - CreateDwordField (^MCRS, ^PM01._MIN, PMIN) - CreateDwordField (^MCRS, ^PM01._MAX, PMAX) - CreateDwordField (^MCRS, ^PM01._LEN, PLEN) + CreateDwordField (MCRS, PM01._MIN, PMIN) + CreateDwordField (MCRS, PM01._MAX, PMAX) + CreateDwordField (MCRS, PM01._LEN, PLEN) /* * Fix up PCI memory region * Start with Top of Lower Usable DRAM */ - Store (^MCHC.TLUD, PMIN) + Store (\_SB.PCI0.MCHC.TLUD, PMIN) Add (Subtract (PMAX, PMIN), 1, PLEN) /* Patch PM02 range based on Memory Size */ - CreateQwordField (^MCRS, ^PM02._MIN, MMIN) - CreateQwordField (^MCRS, ^PM02._MAX, MMAX) - CreateQwordField (^MCRS, ^PM02._LEN, MLEN) + CreateQwordField (MCRS, PM02._MIN, MMIN) + CreateQwordField (MCRS, PM02._MAX, MMAX) + CreateQwordField (MCRS, PM02._LEN, MLEN) - Store (^MCHC.TUUD, Local0) + Store (\_SB.PCI0.MCHC.TUUD, Local0) If (LLessEqual (Local0, BASE_32GB)) { Store (BASE_32GB, MMIN) @@ -220,58 +220,42 @@ } Subtract (Add (MMIN, MLEN), 1, MMAX) - Return (^MCRS) + Return (MCRS) } -Name (EP_B, 0) /* to store EP BAR */ -Name (MH_B, 0) /* to store MCH BAR */ -Name (PC_B, 0) /* to store PCIe BAR */ -Name (PC_L, 0) /* to store PCIe BAR Length */ -Name (DM_B, 0) /* to store DMI BAR */ - /* Get MCH BAR */ Method (GMHB, 0, Serialized) { - If (LEqual (MH_B, 0)) { - ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, MH_B) - } - Return (MH_B) + ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, Local0) + Return (Local0) } /* Get EP BAR */ Method (GEPB, 0, Serialized) { - If (LEqual (EP_B, 0)) { - ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, EP_B) - } - Return (EP_B) + ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, Local0) + Return (Local0) } /* Get PCIe BAR */ Method (GPCB, 0, Serialized) { - If (LEqual (PC_B, 0)) { - ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, PC_B) - } - Return (PC_B) + ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, Local0) + Return (Local0) } /* Get PCIe Length */ Method (GPCL, 0, Serialized) { - If (LEqual (PC_L, 0)) { - ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, PC_L) - } - Return (PC_L) + ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0) + Return (Local0) } /* Get DMI BAR */ Method (GDMB, 0, Serialized) { - If (LEqual (DM_B, 0)) { - ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, DM_B) - } - Return (DM_B) + ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, Local0) + Return (Local0) } /* PCI Device Resource Consumption */ @@ -280,59 +264,61 @@ Name (_HID, EISAID ("PNP0C02")) Name (_UID, 1) - Name (BUF0, ResourceTemplate () - { - /* MCH BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.48h - */ - Memory32Fixed (ReadWrite, 0, 0x08000, MCHB) - - /* DMI BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.68h - */ - Memory32Fixed (ReadWrite, 0, 0x01000, DMIB) - - /* EP BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.40h - */ - Memory32Fixed (ReadWrite, 0, 0x01000, EGPB) - - /* PCI Express BAR _BAS and _LEN will be updated in - * _CRS below according to B0:D0:F0:Reg.60h - */ - Memory32Fixed (ReadWrite, 0, 0, PCIX) - - /* VTD engine memory range. - */ - Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) - - /* FLASH range */ - Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000, FIOH) - - /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ - Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH) - - /* HPET address decode range */ - Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) - }) - Method (_CRS, 0, Serialized) { - CreateDwordField (BUF0, ^MCHB._BAS, MBR0) + Name (BUF0, ResourceTemplate () + { + /* MCH BAR _BAS will be updated in _CRS below according to + * B0:D0:F0:Reg.48h + */ + Memory32Fixed (ReadWrite, 0, 0x08000, MCHB) + + /* DMI BAR _BAS will be updated in _CRS below according to + * B0:D0:F0:Reg.68h + */ + Memory32Fixed (ReadWrite, 0, 0x01000, DMIB) + + /* EP BAR _BAS will be updated in _CRS below according to + * B0:D0:F0:Reg.40h + */ + Memory32Fixed (ReadWrite, 0, 0x01000, EGPB) + + /* PCI Express BAR _BAS and _LEN will be updated in + * _CRS below according to B0:D0:F0:Reg.60h + */ + Memory32Fixed (ReadWrite, 0, 0, PCIX) + + /* VTD engine memory range. */ + Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) + + /* FLASH range */ + Memory32Fixed (ReadOnly, 0, CONFIG_ROM_SIZE, FIOH) + + /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ + Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) + + /* HPET address decode range */ + Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) + }) + + CreateDwordField (BUF0, MCHB._BAS, MBR0) Store (\_SB.PCI0.GMHB (), MBR0) - CreateDwordField (BUF0, ^DMIB._BAS, DBR0) + CreateDwordField (BUF0, DMIB._BAS, DBR0) Store (\_SB.PCI0.GDMB (), DBR0) - CreateDwordField (BUF0, ^EGPB._BAS, EBR0) + CreateDwordField (BUF0, EGPB._BAS, EBR0) Store (\_SB.PCI0.GEPB (), EBR0) - CreateDwordField (BUF0, ^PCIX._BAS, XBR0) + CreateDwordField (BUF0, PCIX._BAS, XBR0) Store (\_SB.PCI0.GPCB (), XBR0) - CreateDwordField (BUF0, ^PCIX._LEN, XSZ0) + CreateDwordField (BUF0, PCIX._LEN, XSZ0) Store (\_SB.PCI0.GPCL (), XSZ0) + CreateDwordField (BUF0, FIOH._BAS, FBR0) + Subtract(0x100000000, CONFIG_ROM_SIZE, FBR0) + Return (BUF0) } } diff --git a/src/soc/intel/icelake/acpi/northbridge.asl b/src/soc/intel/icelake/acpi/northbridge.asl index 68c7f9e..6842021 100644 --- a/src/soc/intel/icelake/acpi/northbridge.asl +++ b/src/soc/intel/icelake/acpi/northbridge.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2018-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -52,165 +52,163 @@ , 11, DIBR, 20, /* DMIBAR [31:12] */ - Offset (0xa0), /* Top of Used Memory */ - TOM, 64, - - Offset (0xa8), /* Top of Upper Used Memory */ - TUUD, 64, + Offset (0xa0), + TOM, 64, /* Top of Used Memory */ + TUUD, 64, /* Top of Upper Used Memory */ Offset (0xbc), /* Top of Low Used Memory */ TLUD, 32, } } -Name (MCRS, ResourceTemplate () -{ - /* Bus Numbers */ - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100) - - /* IO Region 0 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, - EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8) - - /* PCI Config Space */ - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - /* IO Region 1 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, - EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300) - - /* VGA memory (0xa0000-0xbffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000) - - /* OPROM reserved (0xc0000-0xc3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xc4000-0xc7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xc8000-0xcbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xcc000-0xcffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd0000-0xd3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd4000-0xd7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd8000-0xdbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xdc000-0xdffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe0000-0xe3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe4000-0xe7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe8000-0xebfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xec000-0xeffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000) - - /* System BIOS (0xf0000-0xfffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000) - - /* PCI Memory Region (TLUD - 0xdfffffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, - 0xE0000000,,, PM01) - - /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */ - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x10000, 0x1ffff, 0x00000000, - 0x10000,,, PM02) - - /* PCH reserved resource (0xfc800000-0xfe7fffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff, - 0x00000000, PCH_PRESERVED_BASE_SIZE) - - /* TPM Area (0xfed40000-0xfed47fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000, - 0x00008000) -}) - Method (_CRS, 0, Serialized) { + Name (MCRS, ResourceTemplate () + { + /* Bus Numbers */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8) + + /* PCI Config Space */ + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000) + + /* OPROM reserved (0xc0000-0xc3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xc4000-0xc7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xc8000-0xcbfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xcc000-0xcffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd0000-0xd3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd4000-0xd7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd8000-0xdbfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xdc000-0xdffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe0000-0xe3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe4000-0xe7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe8000-0xebfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xec000-0xeffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000) + + /* System BIOS (0xf0000-0xfffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000) + + /* PCI Memory Region (TLUD - 0xdfffffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, + 0xE0000000,,, PM01) + + /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x10000, 0x1ffff, 0x00000000, + 0x10000,,, PM02) + + /* PCH reserved resource (0xfc800000-0xfe7fffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff, + 0x00000000, PCH_PRESERVED_BASE_SIZE) + + /* TPM Area (0xfed40000-0xfed47fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000, + 0x00008000) + }) + /* Find PCI resource area in MCRS */ - CreateDwordField (^MCRS, ^PM01._MIN, PMIN) - CreateDwordField (^MCRS, ^PM01._MAX, PMAX) - CreateDwordField (^MCRS, ^PM01._LEN, PLEN) + CreateDwordField (MCRS, PM01._MIN, PMIN) + CreateDwordField (MCRS, PM01._MAX, PMAX) + CreateDwordField (MCRS, PM01._LEN, PLEN) /* * Fix up PCI memory region * Start with Top of Lower Usable DRAM */ - Store (^MCHC.TLUD, PMIN) + Store (\_SB.PCI0.MCHC.TLUD, PMIN) Add (Subtract (PMAX, PMIN), 1, PLEN) /* Patch PM02 range based on Memory Size */ - CreateQwordField (^MCRS, ^PM02._MIN, MMIN) - CreateQwordField (^MCRS, ^PM02._MAX, MMAX) - CreateQwordField (^MCRS, ^PM02._LEN, MLEN) + CreateQwordField (MCRS, PM02._MIN, MMIN) + CreateQwordField (MCRS, PM02._MAX, MMAX) + CreateQwordField (MCRS, PM02._LEN, MLEN) - Store (^MCHC.TUUD, Local0) + Store (\_SB.PCI0.MCHC.TUUD, Local0) If (LLessEqual (Local0, BASE_32GB)) { Store (BASE_32GB, MMIN) @@ -221,58 +219,42 @@ } Subtract (Add (MMIN, MLEN), 1, MMAX) - Return (^MCRS) + Return (MCRS) } -Name (EP_B, 0) /* to store EP BAR */ -Name (MH_B, 0) /* to store MCH BAR */ -Name (PC_B, 0) /* to store PCIe BAR */ -Name (PC_L, 0) /* to store PCIe BAR Length */ -Name (DM_B, 0) /* to store DMI BAR */ - /* Get MCH BAR */ Method (GMHB, 0, Serialized) { - If (LEqual (MH_B, 0)) { - ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, MH_B) - } - Return (MH_B) + ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, Local0) + Return (Local0) } /* Get EP BAR */ Method (GEPB, 0, Serialized) { - If (LEqual (EP_B, 0)) { - ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, EP_B) - } - Return (EP_B) + ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, Local0) + Return (Local0) } /* Get PCIe BAR */ Method (GPCB, 0, Serialized) { - If (LEqual (PC_B, 0)) { - ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, PC_B) - } - Return (PC_B) + ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, Local0) + Return (Local0) } /* Get PCIe Length */ Method (GPCL, 0, Serialized) { - If (LEqual (PC_L, 0)) { - ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, PC_L) - } - Return (PC_L) + ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0) + Return (Local0) } /* Get DMI BAR */ Method (GDMB, 0, Serialized) { - If (LEqual (DM_B, 0)) { - ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, DM_B) - } - Return (DM_B) + ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, Local0) + Return (Local0) } /* PCI Device Resource Consumption */ @@ -281,59 +263,61 @@ Name (_HID, EISAID ("PNP0C02")) Name (_UID, 1) - Name (BUF0, ResourceTemplate () - { - /* MCH BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.48h - */ - Memory32Fixed (ReadWrite, 0, 0x08000, MCHB) - - /* DMI BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.68h - */ - Memory32Fixed (ReadWrite, 0, 0x01000, DMIB) - - /* EP BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.40h - */ - Memory32Fixed (ReadWrite, 0, 0x01000, EGPB) - - /* PCI Express BAR _BAS and _LEN will be updated in - * _CRS below according to B0:D0:F0:Reg.60h - */ - Memory32Fixed (ReadWrite, 0, 0, PCIX) - - /* VTD engine memory range. - */ - Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) - - /* FLASH range */ - Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000, FIOH) - - /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ - Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH) - - /* HPET address decode range */ - Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) - }) - Method (_CRS, 0, Serialized) { - CreateDwordField (BUF0, ^MCHB._BAS, MBR0) + Name (BUF0, ResourceTemplate () + { + /* MCH BAR _BAS will be updated in _CRS below according to + * B0:D0:F0:Reg.48h + */ + Memory32Fixed (ReadWrite, 0, 0x08000, MCHB) + + /* DMI BAR _BAS will be updated in _CRS below according to + * B0:D0:F0:Reg.68h + */ + Memory32Fixed (ReadWrite, 0, 0x01000, DMIB) + + /* EP BAR _BAS will be updated in _CRS below according to + * B0:D0:F0:Reg.40h + */ + Memory32Fixed (ReadWrite, 0, 0x01000, EGPB) + + /* PCI Express BAR _BAS and _LEN will be updated in + * _CRS below according to B0:D0:F0:Reg.60h + */ + Memory32Fixed (ReadWrite, 0, 0, PCIX) + + /* VTD engine memory range. */ + Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) + + /* FLASH range */ + Memory32Fixed (ReadOnly, 0, CONFIG_ROM_SIZE, FIOH) + + /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ + Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) + + /* HPET address decode range */ + Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) + }) + + CreateDwordField (BUF0, MCHB._BAS, MBR0) Store (\_SB.PCI0.GMHB (), MBR0) - CreateDwordField (BUF0, ^DMIB._BAS, DBR0) + CreateDwordField (BUF0, DMIB._BAS, DBR0) Store (\_SB.PCI0.GDMB (), DBR0) - CreateDwordField (BUF0, ^EGPB._BAS, EBR0) + CreateDwordField (BUF0, EGPB._BAS, EBR0) Store (\_SB.PCI0.GEPB (), EBR0) - CreateDwordField (BUF0, ^PCIX._BAS, XBR0) + CreateDwordField (BUF0, PCIX._BAS, XBR0) Store (\_SB.PCI0.GPCB (), XBR0) - CreateDwordField (BUF0, ^PCIX._LEN, XSZ0) + CreateDwordField (BUF0, PCIX._LEN, XSZ0) Store (\_SB.PCI0.GPCL (), XSZ0) + CreateDwordField (BUF0, FIOH._BAS, FBR0) + Subtract(0x100000000, CONFIG_ROM_SIZE, FBR0) + Return (BUF0) } } diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl index e7b2d90..589fcc1 100644 --- a/src/soc/intel/skylake/acpi/systemagent.asl +++ b/src/soc/intel/skylake/acpi/systemagent.asl @@ -23,8 +23,6 @@ Name (_HID, EISAID ("PNP0A08")) /* PCIe */ Name (_CID, EISAID ("PNP0A03")) /* PCI */ -Name (_BBN, 0) - Device (MCHC) { Name (_ADR, 0x00000000) @@ -55,175 +53,172 @@ Offset (0x70), /* ME Base Address */ MEBA, 64, - - Offset (0xa0), /* Top of Used Memory */ - TOM, 64, - - Offset (0xa8), /* Top of Upper Used Memory */ - TUUD, 64, + Offset (0xa0), + TOM, 64, /* Top of Used Memory */ + TUUD, 64, /* Top of Upper Used Memory */ Offset (0xbc), /* Top of Low Used Memory */ TLUD, 32, } } -Name (MCRS, ResourceTemplate () -{ - /* Bus Numbers */ - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100) - - /* IO Region 0 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, - EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8) - - /* PCI Config Space */ - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - /* IO Region 1 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, - EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300) - - /* VGA memory (0xa0000-0xbffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000) - - /* OPROM reserved (0xc0000-0xc3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xc4000-0xc7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xc8000-0xcbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xcc000-0xcffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd0000-0xd3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd4000-0xd7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd8000-0xdbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xdc000-0xdffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe0000-0xe3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe4000-0xe7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe8000-0xebfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xec000-0xeffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000) - - /* System BIOS (0xf0000-0xfffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000) - - /* PCI Memory Region (TOLUD - 0xdfffffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, - 0xE0000000,,, PM01) - - /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */ - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x10000, 0x1ffff, 0x00000000, - 0x10000,,, PM02) - - /* PCH reserved resource (0xfd000000-0xfe7fffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfd000000, 0xfe7fffff, 0x00000000, - 0x1800000) - - /* TPM Area (0xfed40000-0xfed44fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000) -}) - Method (_CRS, 0, Serialized) { + Name (MCRS, ResourceTemplate () + { + /* Bus Numbers */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8) + + /* PCI Config Space */ + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000) + + /* OPROM reserved (0xc0000-0xc3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xc4000-0xc7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xc8000-0xcbfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xcc000-0xcffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd0000-0xd3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd4000-0xd7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd8000-0xdbfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xdc000-0xdffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe0000-0xe3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe4000-0xe7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe8000-0xebfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xec000-0xeffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000) + + /* System BIOS (0xf0000-0xfffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000) + + /* PCI Memory Region (TLUD - 0xdfffffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, + 0xE0000000,,, PM01) + + /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x10000, 0x1ffff, 0x00000000, + 0x10000,,, PM02) + + /* PCH reserved resource (0xfc800000-0xfe7fffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff, + 0x00000000, PCH_PRESERVED_BASE_SIZE) + + /* TPM Area (0xfed40000-0xfed44fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000) +}) + /* Find PCI resource area in MCRS */ - CreateDwordField (^MCRS, ^PM01._MIN, PMIN) - CreateDwordField (^MCRS, ^PM01._MAX, PMAX) - CreateDwordField (^MCRS, ^PM01._LEN, PLEN) + CreateDwordField (MCRS, PM01._MIN, PMIN) + CreateDwordField (MCRS, PM01._MAX, PMAX) + CreateDwordField (MCRS, PM01._LEN, PLEN) /* * Fix up PCI memory region * Start with Top of Lower Usable DRAM */ - Store (^MCHC.TLUD, Local0) - Store (^MCHC.MEBA, Local1) + Store (\_SB.PCI0.MCHC.TLUD, Local0) + Store (\_SB.PCI0.MCHC.MEBA, Local1) /* Check if ME base is equal */ If (LEqual (Local0, Local1)) { /* Use Top Of Memory instead */ - Store (^MCHC.TOM, Local0) + Store (\_SB.PCI0.MCHC.TOM, Local0) } Store (Local0, PMIN) Add (Subtract (PMAX, PMIN), 1, PLEN) /* Patch PM02 range based on Memory Size */ - CreateQwordField (^MCRS, ^PM02._MIN, MMIN) - CreateQwordField (^MCRS, ^PM02._MAX, MMAX) - CreateQwordField (^MCRS, ^PM02._LEN, MLEN) + CreateQwordField (MCRS, PM02._MIN, MMIN) + CreateQwordField (MCRS, PM02._MAX, MMAX) + CreateQwordField (MCRS, PM02._LEN, MLEN) - Store (^MCHC.TUUD, Local0) + Store (\_SB.PCI0.MCHC.TUUD, Local0) If (LLessEqual (Local0, BASE_32GB)) { Store (BASE_32GB, MMIN) @@ -234,58 +229,42 @@ } Subtract (Add (MMIN, MLEN), 1, MMAX) - Return (^MCRS) + Return (MCRS) } -Name (EP_B, 0) /* to store EP BAR */ -Name (MH_B, 0) /* to store MCH BAR */ -Name (PC_B, 0) /* to store PCIe BAR */ -Name (PC_L, 0) /* to store PCIe BAR Length */ -Name (DM_B, 0) /* to store DMI BAR */ - /* Get MCH BAR */ Method (GMHB, 0, Serialized) { - If (LEqual (MH_B, 0)) { - ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, MH_B) - } - Return (MH_B) + ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, Local0) + Return (Local0) } /* Get EP BAR */ Method (GEPB, 0, Serialized) { - If (LEqual (EP_B, 0)) { - ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, EP_B) - } - Return (EP_B) + ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, Local0) + Return (Local0) } /* Get PCIe BAR */ Method (GPCB, 0, Serialized) { - If (LEqual (PC_B, 0)) { - ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, PC_B) - } - Return (PC_B) + ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, Local0) + Return (Local0) } /* Get PCIe Length */ Method (GPCL, 0, Serialized) { - If (LEqual (PC_L, 0)) { - ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, PC_L) - } - Return (PC_L) + ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0) + Return (Local0) } /* Get DMI BAR */ Method (GDMB, 0, Serialized) { - If (LEqual (DM_B, 0)) { - ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, DM_B) - } - Return (DM_B) + ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, Local0) + Return (Local0) } /* PCI Device Resource Consumption */ @@ -294,70 +273,71 @@ Name (_HID, EISAID ("PNP0C02")) Name (_UID, 1) - Name (BUF0, ResourceTemplate () - { - /* MCH BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.48h - */ - Memory32Fixed (ReadWrite, 0, 0x08000, MCHB) - - /* DMI BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.68h - */ - Memory32Fixed (ReadWrite, 0, 0x01000, DMIB) - - /* EP BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.40h - */ - Memory32Fixed (ReadWrite, 0, 0x01000, EGPB) - - /* PCI Express BAR _BAS and _LEN will be updated in - * _CRS below according to B0:D0:F0:Reg.60h - */ - Memory32Fixed (ReadWrite, 0, 0, PCIX) - - /* MISC ICH TTT base address reserved for the - * TxT module use. - */ - Memory32Fixed (ReadWrite, 0xFED20000, 0x20000) - - /* VTD engine memory range. - * Check if the hard code meets the real configuration. - */ - Memory32Fixed (ReadOnly, 0xFED90000, 0x00004000) - - /* MISC ICH. Check if the hard code meets the - * real configuration. - */ - Memory32Fixed (ReadWrite, 0xFED45000, 0x4B000, TPMM) - - /* FLASH range */ - Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000, FIOH) /* 16MB */ - - /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ - Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH) - - /* HPET address decode range */ - Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) - }) - Method (_CRS, 0, Serialized) { - CreateDwordField (BUF0, ^MCHB._BAS, MBR0) + Name (BUF0, ResourceTemplate () + { + /* MCH BAR _BAS will be updated in _CRS below according to + * B0:D0:F0:Reg.48h + */ + Memory32Fixed (ReadWrite, 0, 0x08000, MCHB) + + /* DMI BAR _BAS will be updated in _CRS below according to + * B0:D0:F0:Reg.68h + */ + Memory32Fixed (ReadWrite, 0, 0x01000, DMIB) + + /* EP BAR _BAS will be updated in _CRS below according to + * B0:D0:F0:Reg.40h + */ + Memory32Fixed (ReadWrite, 0, 0x01000, EGPB) + + /* PCI Express BAR _BAS and _LEN will be updated in + * _CRS below according to B0:D0:F0:Reg.60h + */ + Memory32Fixed (ReadWrite, 0, 0, PCIX) + + /* MISC ICH TTT base address reserved for the + * TxT module use. + */ + Memory32Fixed (ReadWrite, 0xFED20000, 0x20000) + + /* VTD engine memory range. */ + Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) + + /* MISC ICH. Check if the hard code meets the + * real configuration. + */ + Memory32Fixed (ReadWrite, 0xFED45000, 0x4B000, TPMM) + + /* FLASH range */ + Memory32Fixed (ReadOnly, 0, CONFIG_ROM_SIZE, FIOH) + + /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ + Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) + + /* HPET address decode range */ + Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) + }) + + CreateDwordField (BUF0, MCHB._BAS, MBR0) Store (\_SB.PCI0.GMHB (), MBR0) - CreateDwordField (BUF0, ^DMIB._BAS, DBR0) + CreateDwordField (BUF0, DMIB._BAS, DBR0) Store (\_SB.PCI0.GDMB (), DBR0) - CreateDwordField (BUF0, ^EGPB._BAS, EBR0) + CreateDwordField (BUF0, EGPB._BAS, EBR0) Store (\_SB.PCI0.GEPB (), EBR0) - CreateDwordField (BUF0, ^PCIX._BAS, XBR0) + CreateDwordField (BUF0, PCIX._BAS, XBR0) Store (\_SB.PCI0.GPCB (), XBR0) - CreateDwordField (BUF0, ^PCIX._LEN, XSZ0) + CreateDwordField (BUF0, PCIX._LEN, XSZ0) Store (\_SB.PCI0.GPCL (), XSZ0) + CreateDwordField (BUF0, FIOH._BAS, FBR0) + Subtract(0x100000000, CONFIG_ROM_SIZE, FBR0) + Return (BUF0) } } diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h index c73d766..814dd94 100644 --- a/src/soc/intel/skylake/include/soc/iomap.h +++ b/src/soc/intel/skylake/include/soc/iomap.h @@ -63,6 +63,9 @@ #define THERMAL_BASE_ADDRESS 0xfe600000 +#define VTD_BASE_ADDRESS 0xFED90000 +#define VTD_BASE_SIZE 0x00004000 + /* CPU Trace reserved memory size */ #define GDXC_MOT_MEMORY_SIZE (96*MiB) #define GDXC_IOT_MEMORY_SIZE (32*MiB) diff --git a/src/soc/intel/tigerlake/acpi/northbridge.asl b/src/soc/intel/tigerlake/acpi/northbridge.asl index d6c2d34..149839d 100644 --- a/src/soc/intel/tigerlake/acpi/northbridge.asl +++ b/src/soc/intel/tigerlake/acpi/northbridge.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. + * Copyright (C) 2019-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -52,11 +52,9 @@ , 11, DIBR, 20, /* DMIBAR [31:12] */ - Offset (0xa0), /* Top of Used Memory */ - TOM, 64, - - Offset (0xa8), /* Top of Upper Used Memory */ - TUUD, 64, + Offset (0xa0), + TOM, 64, /* Top of Used Memory */ + TUUD, 64, /* Top of Upper Used Memory */ Offset (0xbc), /* Top of Low Used Memory */ TLUD, 32, @@ -224,58 +222,39 @@ Return (MCRS) } -/* - * TODO: Clean up below functions and follow ASL2.0 code syntax - */ -Name (EP_B, 0) /* to store EP BAR */ -Name (MH_B, 0) /* to store MCH BAR */ -Name (PC_B, 0) /* to store PCIe BAR */ -Name (PC_L, 0) /* to store PCIe BAR Length */ -Name (DM_B, 0) /* to store DMI BAR */ - /* Get MCH BAR */ Method (GMHB, 0, Serialized) { - If (LEqual (MH_B, 0)) { - ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, MH_B) - } - Return (MH_B) + ShiftLeft (\_SB.PCI0.MCHC.MHBR, 15, Local0) + Return (Local0) } /* Get EP BAR */ Method (GEPB, 0, Serialized) { - If (LEqual (EP_B, 0)) { - ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, EP_B) - } - Return (EP_B) + ShiftLeft (\_SB.PCI0.MCHC.EPBR, 12, Local0) + Return (Local0) } /* Get PCIe BAR */ Method (GPCB, 0, Serialized) { - If (LEqual (PC_B, 0)) { - ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, PC_B) - } - Return (PC_B) + ShiftLeft (\_SB.PCI0.MCHC.PXBR, 26, Local0) + Return (Local0) } /* Get PCIe Length */ Method (GPCL, 0, Serialized) { - If (LEqual (PC_L, 0)) { - ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, PC_L) - } - Return (PC_L) + ShiftRight (0x10000000, \_SB.PCI0.MCHC.PXSZ, Local0) + Return (Local0) } /* Get DMI BAR */ Method (GDMB, 0, Serialized) { - If (LEqual (DM_B, 0)) { - ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, DM_B) - } - Return (DM_B) + ShiftLeft (\_SB.PCI0.MCHC.DIBR, 12, Local0) + Return (Local0) } /* PCI Device Resource Consumption */ @@ -284,59 +263,61 @@ Name (_HID, EISAID ("PNP0C02")) Name (_UID, 1) - Name (BUF0, ResourceTemplate () - { - /* MCH BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.48h - */ - Memory32Fixed (ReadWrite, 0, 0x08000, MCHB) - - /* DMI BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.68h - */ - Memory32Fixed (ReadWrite, 0, 0x01000, DMIB) - - /* EP BAR _BAS will be updated in _CRS below according to - * B0:D0:F0:Reg.40h - */ - Memory32Fixed (ReadWrite, 0, 0x01000, EGPB) - - /* PCI Express BAR _BAS and _LEN will be updated in - * _CRS below according to B0:D0:F0:Reg.60h - */ - Memory32Fixed (ReadWrite, 0, 0, PCIX) - - /* VTD engine memory range. - */ - Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) - - /* Memory mapped SPI Flash range */ - Memory32Fixed (ReadOnly, 0xFFF00000, 0x1000000) - - /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ - Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) - - /* HPET address decode range */ - Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) - }) - Method (_CRS, 0, Serialized) { - CreateDwordField (BUF0, ^MCHB._BAS, MBR0) + Name (BUF0, ResourceTemplate () + { + /* MCH BAR _BAS will be updated in _CRS below according to + * B0:D0:F0:Reg.48h + */ + Memory32Fixed (ReadWrite, 0, 0x08000, MCHB) + + /* DMI BAR _BAS will be updated in _CRS below according to + * B0:D0:F0:Reg.68h + */ + Memory32Fixed (ReadWrite, 0, 0x01000, DMIB) + + /* EP BAR _BAS will be updated in _CRS below according to + * B0:D0:F0:Reg.40h + */ + Memory32Fixed (ReadWrite, 0, 0x01000, EGPB) + + /* PCI Express BAR _BAS and _LEN will be updated in + * _CRS below according to B0:D0:F0:Reg.60h + */ + Memory32Fixed (ReadWrite, 0, 0, PCIX) + + /* VTD engine memory range. */ + Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) + + /* FLASH range */ + Memory32Fixed (ReadOnly, 0, CONFIG_ROM_SIZE, FIOH) + + /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ + Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) + + /* HPET address decode range */ + Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) + }) + + CreateDwordField (BUF0, MCHB._BAS, MBR0) Store (\_SB.PCI0.GMHB (), MBR0) - CreateDwordField (BUF0, ^DMIB._BAS, DBR0) + CreateDwordField (BUF0, DMIB._BAS, DBR0) Store (\_SB.PCI0.GDMB (), DBR0) - CreateDwordField (BUF0, ^EGPB._BAS, EBR0) + CreateDwordField (BUF0, EGPB._BAS, EBR0) Store (\_SB.PCI0.GEPB (), EBR0) - CreateDwordField (BUF0, ^PCIX._BAS, XBR0) + CreateDwordField (BUF0, PCIX._BAS, XBR0) Store (\_SB.PCI0.GPCB (), XBR0) - CreateDwordField (BUF0, ^PCIX._LEN, XSZ0) + CreateDwordField (BUF0, PCIX._LEN, XSZ0) Store (\_SB.PCI0.GPCL (), XSZ0) + CreateDwordField (BUF0, FIOH._BAS, FBR0) + Subtract(0x100000000, CONFIG_ROM_SIZE, FBR0) + Return (BUF0) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/38154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id74269ec5a96b087562ccdf2141233db5585ae59 Gerrit-Change-Number: 38154 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

5 18

Change in coreboot[master]: mainboard/pcengines/apu2/mainboard.c: fill SMBIOS type 16 and 17
by Piotr Kleinschmidt (Code Review) 13 Jan '20

13 Jan '20

Piotr Kleinschmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35889 ) Change subject: mainboard/pcengines/apu2/mainboard.c: fill SMBIOS type 16 and 17 ...................................................................... mainboard/pcengines/apu2/mainboard.c: fill SMBIOS type 16 and 17 Change-Id: I24cd5abceabd11a079a8331e4b95cb69af8e94bf Signed-off-by: Piotr Kleinschmidt <piotr.kleins(a)gmail.com> --- M src/device/dram/Makefile.inc M src/lib/Makefile.inc M src/mainboard/pcengines/apu2/mainboard.c 3 files changed, 124 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/35889/1 diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc index f397a53..d9df410 100644 --- a/src/device/dram/Makefile.inc +++ b/src/device/dram/Makefile.inc @@ -1 +1,2 @@ romstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c +ramstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c \ No newline at end of file diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e5678ff..dc09851 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -328,6 +328,7 @@ endif # CONFIG_RAMSTAGE_LIBHWBASE romstage-y += spd_bin.c +ramstage-y += spd_bin.c ifeq ($(CONFIG_GENERIC_SPD_BIN),y) LIB_SPD_BIN = $(obj)/spd.bin diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 682120b..1d91a39 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -27,6 +27,9 @@ #include <superio/nuvoton/nct5104d/nct5104d.h> #include <smbios.h> #include <string.h> +#include <cbmem.h> +#include <spd_bin.h> +#include <cbfs.h> #include "gpio_ftns.h" #define SPD_SIZE 128 @@ -154,6 +157,81 @@ gpio->enabled = CONFIG(APU2_PINMUX_GPIO1); } +static void set_dimm_info(uint8_t *spd, struct dimm_info *dimm) +{ + const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; + const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; + const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; + const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + + int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; + int ranks = spd_ranks[(spd[DDR3_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[DDR3_ORGANIZATION] & 7]; + int busw = spd_busw[spd[DDR3_BUS_DEV_WIDTH] & 7]; + + switch (spd[12]) { + case 0x0a: + dimm->ddr_frequency = 1600; + break; + case 0x0c: + dimm->ddr_frequency = 1333; + break; + default: + dimm->ddr_frequency = 0; + break; + } + + dimm->ddr_type = MEMORY_TYPE_DDR3; + + /* Parse the SPD data to determine the DIMM information */ + + dimm->dimm_size = capmb / 8 * busw / devw * ranks; /* MiB */ + dimm->mod_type = spd[3] & 0xf; + dimm->module_part_number[0] = '\0'; + dimm->mod_id = *(uint16_t *)&spd[117]; + + switch (busw) { + default: + case 8: + dimm->bus_width = MEMORY_BUS_WIDTH_8; + break; + case 16: + dimm->bus_width = MEMORY_BUS_WIDTH_16; + break; + case 32: + dimm->bus_width = MEMORY_BUS_WIDTH_32; + break; + case 64: + dimm->bus_width = MEMORY_BUS_WIDTH_64; + break; + } + + if(spd[3]==0x08){ + dimm->bus_width |= BIOS_MEMORY_ECC_SINGLE_BIT_CORRECTING; + } +} + +static void mainboard_get_dimm_info(u8 *spd_buffer) +{ + struct dimm_info *dimm; + struct memory_info *mem_info; + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + if (mem_info == NULL) + return; + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first channel memory */ + dimm = &mem_info->dimm[0]; + set_dimm_info(spd_buffer, dimm); + mem_info->dimm_cnt = 1; +} + /********************************************** * enable the dedicated function in mainboard. **********************************************/ @@ -164,6 +242,11 @@ config_gpio_mux(); + u8 spd_index = get_spd_offset(); + u8 spd_buffer[CONFIG_DIMM_SPD_SIZE]; + + read_ddr3_spd_from_cbfs(spd_buffer, spd_index); + // // Enable the RTC output // @@ -176,6 +259,8 @@ /* Initialize the PIRQ data structures for consumption */ pirq_setup(); + + mainboard_get_dimm_info(spd_buffer); } static void mainboard_final(void *chip_info) @@ -241,6 +326,43 @@ return sku; } +int fill_mainboard_smbios_type16(unsigned long *current, int *handle) +{ + u8 spd_index = get_spd_offset(); + u8 spd_buffer[CONFIG_DIMM_SPD_SIZE]; + + if (read_ddr3_spd_from_cbfs(spd_buffer, spd_index) < 0) + return 0; + + struct smbios_type16 *t = (struct smbios_type16 *)*current; + int len = sizeof(struct smbios_type16) - 2; + memset(t, 0, sizeof(struct smbios_type16)); + + t->handle = *handle; + t->length = len; + t->type = SMBIOS_PHYS_MEMORY_ARRAY; + t->use = MEMORY_ARRAY_USE_SYSTEM; + t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; + t->maximum_capacity = 4 * 1024 * 1024; // 4GB (in kB) due to board design + t->extended_maximum_capacity = 0; + t->memory_error_information_handle = 0xFFFE; + t->number_of_memory_devices = 1; // only 1 device soldered down to 1 channel + + switch(spd_buffer[3]){ + case 0x08: + t->memory_error_correction = MEMORY_ARRAY_ECC_MULTI_BIT; + break; + case 0x03: + t->memory_error_correction = MEMORY_ARRAY_ECC_NONE; + break; + default: + t->memory_error_correction = MEMORY_ARRAY_ECC_UNKNOWN; + break; + } + len += smbios_string_table_len(t->eos); + return len; +} + struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, .final = mainboard_final, -- To view, visit https://review.coreboot.org/c/coreboot/+/35889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24cd5abceabd11a079a8331e4b95cb69af8e94bf Gerrit-Change-Number: 35889 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2020