coreboot-gerrit January 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: src/arch/x86/smbios.c: add SMBIOS type 16 structure
by Piotr Kleinschmidt (Code Review) 13 Jan '20

13 Jan '20

Piotr Kleinschmidt has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35888 ) Change subject: src/arch/x86/smbios.c: add SMBIOS type 16 structure ...................................................................... src/arch/x86/smbios.c: add SMBIOS type 16 structure Change-Id: I590ebf89ecb3f97a9ce028ca34696e5809d66d49 Signed-off-by: Piotr Kleinschmidt <piotr.kleins(a)gmail.com> --- M src/arch/x86/smbios.c M src/include/smbios.h 2 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35888/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 4eb8726..4e8a794 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -527,6 +527,11 @@ return ""; } +int __weak fill_mainboard_smbios_type16(unsigned long *current, int *handle) +{ + return 0; +} + static int get_socket_type(void) { if (CONFIG(CPU_INTEL_SLOT_1)) @@ -938,6 +943,16 @@ return len; } +static int smbios_write_type16(unsigned long *current, int *handle) +{ + int len = fill_mainboard_smbios_type16(current, handle); + if(len){ + *current += len; + (*handle)++; + } + return len; +} + static int smbios_write_type17(unsigned long *current, int *handle) { int len = sizeof(struct smbios_type17); @@ -1176,6 +1191,8 @@ if (CONFIG(ELOG)) update_max(len, max_struct_size, elog_smbios_write_type15(&current,handle++)); + update_max(len, max_struct_size, smbios_write_type16(&current, + &handle)); update_max(len, max_struct_size, smbios_write_type17(&current, &handle)); update_max(len, max_struct_size, smbios_write_type32(&current, diff --git a/src/include/smbios.h b/src/include/smbios.h index 0bba0a7..e808177 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -52,6 +52,7 @@ const char *smbios_system_version(void); void smbios_system_set_uuid(u8 *uuid); const char *smbios_system_sku(void); +int fill_mainboard_smbios_type16(unsigned long *current, int *handle); const char *smbios_mainboard_manufacturer(void); const char *smbios_mainboard_product_name(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/35888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I590ebf89ecb3f97a9ce028ca34696e5809d66d49 Gerrit-Change-Number: 35888 Gerrit-PatchSet: 1 Gerrit-Owner: Piotr Kleinschmidt <piotr.kleinschmidt(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Call mainboard ACPI sleep methods
by Angel Pons (Code Review) 13 Jan '20

13 Jan '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38318 ) Change subject: soc/intel/skylake: Call mainboard ACPI sleep methods ...................................................................... Patch Set 6: Code-Review+1 Older Intel platforms leave the _PTS and _WAK methods to be defined in mainboard-specific code. That means most of them are left at defaults, so this sounds like a good idea. -- To view, visit https://review.coreboot.org/c/coreboot/+/38318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I969d92c7445b01964d92d28b21f6667614ea82e7 Gerrit-Change-Number: 38318 Gerrit-PatchSet: 6 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Comment-Date: Mon, 13 Jan 2020 09:04:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{common,skl,cnl,icl,apl,tgl}: Make me_hfsts1 structure SoC ...
by Sridhar Siricilla (Code Review) 13 Jan '20

13 Jan '20

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35546 ) Change subject: soc/intel/{common,skl,cnl,icl,apl,tgl}: Make me_hfsts1 structure SoC specific ...................................................................... Patch Set 24: (11 comments) https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… File src/soc/intel/common/block/cse/cse.c: https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 609: memset(&reply, 0, reply_size); > Not required. Removed the code. Done https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 650: padding > Done in the patch @ https://review.coreboot. […] Done https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 662: or temporary disable mode > Please refer patch: https://review.coreboot.org/c/coreboot/+/37283/13 for latest. […] Done https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 664: hfs1.fields.working_state > Helper function wouldn't be unnecessay function call & additional operations to return the bitfield. Helper function wouldn't be unnecessay function calls & additional operations to return the bitfield? https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 679: return 1; > keeping global reset out of this command handler will help supporting all flows of CSE FW Update. Done https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 687: DISABLES > DISABLED Implemented in patch - https://review.coreboot.org/c/coreboot/+/37283/17 https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 698: padding > reserved Implemented in https://review.coreboot.org/c/coreboot/+/37283/17 https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 711: > This command can be sent only if CWS is normal. […] Yes, I add 'TODO' statement, and will update HMRFPO_STATUS once Chrome SKU is available. https://review.coreboot.org/c/coreboot/+/35546/15/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35546/15/src/soc/intel/common/bloc… PS15, Line 47: #if CONFIG(SOC_INTEL_APOLLOLAKE) > correct. moved me_hfs1 to SoC specific folders. https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc… PS14, Line 152: * > Change is done in the patch - https://review.coreboot. […] Done https://review.coreboot.org/c/coreboot/+/35546/13/src/soc/intel/common/bloc… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35546/13/src/soc/intel/common/bloc… PS13, Line 49: u32 bist_test_result: 1; > The bit fields have been documented in the respective SOC's ME BIOS Writer Guide. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Gerrit-Change-Number: 35546 Gerrit-PatchSet: 24 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <riz.pro(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 13 Jan 2020 06:46:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Call mainboard ACPI sleep methods
by Benjamin Doron (Code Review) 13 Jan '20

13 Jan '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38318 ) Change subject: soc/intel/skylake: Call mainboard ACPI sleep methods ...................................................................... Patch Set 6: > Patch Set 6: > > > Patch Set 6: > > > > > Patch Set 6: > > > > > > Did already have a mainboard level MPTS/MWAK change on top for skylake mainboard? Otherwise the code will not do anything. > > > > Mainboards would implement MPTS/MWAK methods if they needed to, I imagine. The mainboard that I've mostly completed a port for is going to be using it, so I thought I'd try getting this edit into the SoC-level ACPI code. > > Then that will be more than just skylake, what about all the other SOC? If put two commits together to review will be better. Some of the SoCs already do this by including the common SoC code. However, you are right; I'll wait on this until I have a port that will call it. -- To view, visit https://review.coreboot.org/c/coreboot/+/38318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I969d92c7445b01964d92d28b21f6667614ea82e7 Gerrit-Change-Number: 38318 Gerrit-PatchSet: 6 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Comment-Date: Mon, 13 Jan 2020 05:00:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{common,skl,cnl,icl,apl,tgl}: Make me_hfsts1 structure SoC ...
by Sridhar Siricilla (Code Review) 13 Jan '20

13 Jan '20

Sridhar Siricilla has uploaded a new patch set (#24) to the change originally created by Rizwan Qureshi. ( https://review.coreboot.org/c/coreboot/+/35546 ) Change subject: soc/intel/{common,skl,cnl,icl,apl,tgl}: Make me_hfsts1 structure SoC specific ...................................................................... soc/intel/{common,skl,cnl,icl,apl,tgl}: Make me_hfsts1 structure SoC specific Move me_hfsts1 structure from common code to SoC specific. TEST=Build and Boot hatch, soraka, tglrvp, bobba boards. TBD=iclrvp Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/apollolake/cse.c A src/soc/intel/apollolake/include/soc/me.h M src/soc/intel/cannonlake/include/soc/me.h M src/soc/intel/cannonlake/me.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/icelake/Makefile.inc A src/soc/intel/icelake/include/soc/me.h A src/soc/intel/icelake/me.c M src/soc/intel/skylake/include/soc/me.h M src/soc/intel/skylake/me.c M src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/include/soc/me.h A src/soc/intel/tigerlake/me.c 14 files changed, 567 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35546/24 -- To view, visit https://review.coreboot.org/c/coreboot/+/35546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Gerrit-Change-Number: 35546 Gerrit-PatchSet: 24 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <riz.pro(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 13 Jan '20

13 Jan '20

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Sridhar Siricilla, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, V Sowmya, Nico Huber, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35402 to look at the new patch set (#54). Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... soc/intel/common/block/cse: Add boot partition related APIs The CSE region is logically divided into 3 boot partitions when redundancy is enabled. These boot partitions are represented by BP1, BP2 and BP3. In chrome platforms, CSE can boot from either BP1 or BP2. The CSE image layout appears as below.. ------------- ------------------ -------------------------- |CSE REGION | => | RO | RW | => | BP1 | BP2 + BP3 + DATA | ------------- ------------------ -------------------------- In order to support CSE FW update to RW region, below APIs help coreboot to get info about the boot partitions, and allows coreboot to set CSE to boot from required boot partition (either BP1(RO) or BP2). GET_BOOT_PARTITION_INFO - provides info on available partitions in the CSE region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets the next boot partition to boot for CSE. With the HECI API, firmware can notify CSE to boot from BP1 or BP2 on next boot. BUG=b:145809764 Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/Makefile.inc A src/soc/intel/common/block/cse/cse_bp.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 489 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35402/54 -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 54 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/basecode: Implement CSE update flow
by Sridhar Siricilla (Code Review) 13 Jan '20

13 Jan '20

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Sridhar Siricilla, Rizwan Qureshi, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, V Sowmya, Andrey Petrov, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35403 to look at the new patch set (#48). Change subject: soc/intel/common/basecode: Implement CSE update flow ...................................................................... soc/intel/common/basecode: Implement CSE update flow This is the core patch that implement CSE FW update flow. To enable the FW update flow the following are required: * Descriptor change to accommodate a larger CSME region The CSME size is 4.1MB. * FMAP changes to accommodate ME update binary in RW CBFSes & larger CSE binary. Due to the increased CSME binary size and to accommodate the extra CSME RW binaries (which are ~2.5 MB) in RW CBFSes, the board FMAP has to be modified. * The new CSE binary with new partitions and respective RW area binaries. The following changes have been done in this patch: * Implement Update flow Get the partition info containing version of ME RW using GET_BOOT_PARTITION_INFO HECI command Get the me_rw.version from the currently selected RW slot. If the version from the above 2 locations don't match start the update - Set the CSE's next boot partition to RO using SET_BOOT_PARTITION HECI command. - Send global reset command to reset only the CSME - Wait for CSME to enter SOFT_TEMP_DISABLE operation mode (indicated by HFSTS1 register bit 19:16) - Enable HMRFPO (Host ME Region Flash Protection Override) using the HMRFPO_ENABLE HECI command - Erase and Copy the CBFS ME RW to ME RW partition - Set the CSE's next boot partition to RW using SET_BOOT_PARTITION HECI command - Trigger global reset The system should boot with the Updated ME Verified basic update flows on Cometlake RVP and hatch. BUG=b:111330995 Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- A Documentation/soc/intel/cse_fw_update/Layout_after.svg A Documentation/soc/intel/cse_fw_update/Layout_before.svg A Documentation/soc/intel/cse_fw_update/cse_fw_update.md M Documentation/soc/intel/index.md A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/cse_update.c A src/soc/intel/common/basecode/include/intelbasecode/cse_update.h 8 files changed, 857 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35403/48 -- To view, visit https://review.coreboot.org/c/coreboot/+/35403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f6bba3324069d65edabaccd234006b0840e700 Gerrit-Change-Number: 35403 Gerrit-PatchSet: 48 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/{common,skl,cnl,icl,apl,tgl}: Make me_hfsts1 structure SoC ...
by Sridhar Siricilla (Code Review) 13 Jan '20

13 Jan '20

Sridhar Siricilla has uploaded a new patch set (#23) to the change originally created by Rizwan Qureshi. ( https://review.coreboot.org/c/coreboot/+/35546 ) Change subject: soc/intel/{common,skl,cnl,icl,apl,tgl}: Make me_hfsts1 structure SoC specific ...................................................................... soc/intel/{common,skl,cnl,icl,apl,tgl}: Make me_hfsts1 structure SoC specific Move me_hfsts1 structure from common code to SoC specific. TEST=Build and Boot hatch, soraka, tglrvp, bobba boards. TBD=iclrvp Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/apollolake/cse.c A src/soc/intel/apollolake/include/soc/me.h M src/soc/intel/cannonlake/include/soc/me.h M src/soc/intel/cannonlake/me.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/icelake/Makefile.inc A src/soc/intel/icelake/include/soc/me.h A src/soc/intel/icelake/me.c M src/soc/intel/skylake/include/soc/me.h M src/soc/intel/skylake/me.c M src/soc/intel/tigerlake/Makefile.inc A src/soc/intel/tigerlake/include/soc/me.h A src/soc/intel/tigerlake/me.c 14 files changed, 567 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35546/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/35546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Gerrit-Change-Number: 35546 Gerrit-PatchSet: 23 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <riz.pro(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 13 Jan '20

13 Jan '20

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Sridhar Siricilla, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, V Sowmya, Nico Huber, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35402 to look at the new patch set (#53). Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... soc/intel/common/block/cse: Add boot partition related APIs The CSE region is logically divided into 3 boot partitions when redundancy is enabled. These boot partitions are represented by BP1, BP2 and BP3. In chrome platforms, CSE can boot from either BP1 or BP2. The CSE image layout appears as below.. ------------- ------------------ -------------------------- |CSE REGION | => | RO | RW | => | BP1 | BP2 + BP3 + DATA | ------------- ------------------ -------------------------- In order to support CSE FW update to RW region, below APIs help coreboot to get info about the boot partitions, and allows coreboot to set CSE to boot from required boot partition (either BP1(RO) or BP2). GET_BOOT_PARTITION_INFO - provides info on available partitions in the CSE region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets the next boot partition to boot for CSE. With the HECI API, firmware can notify CSE to boot from BP1 or BP2 on next boot. BUG=b:145809764 Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/Makefile.inc A src/soc/intel/common/block/cse/cse_bp.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 489 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35402/53 -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 53 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Call mainboard ACPI sleep methods
by Subrata Banik (Code Review) 13 Jan '20

13 Jan '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38318 ) Change subject: soc/intel/skylake: Call mainboard ACPI sleep methods ...................................................................... Patch Set 6: > Patch Set 6: > > > Patch Set 6: > > > > > Patch Set 6: > > > > > > Did already have a mainboard level MPTS/MWAK change on top for skylake mainboard? Otherwise the code will not do anything. > > > > Mainboards would implement MPTS/MWAK methods if they needed to, I imagine. The mainboard that I've mostly completed a port for is going to be using it, so I thought I'd try getting this edit into the SoC-level ACPI code. > > Then that will be more than just skylake, what about all the other SOC? If put two commits together to review will be better. i agree with Lance, having MPTS and MWAK implemented and calling make more sense -- To view, visit https://review.coreboot.org/c/coreboot/+/38318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I969d92c7445b01964d92d28b21f6667614ea82e7 Gerrit-Change-Number: 38318 Gerrit-PatchSet: 6 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Comment-Date: Mon, 13 Jan 2020 04:36:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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