Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38254 )
Change subject: asus/p3b-f,intel/i440bx: Move enable/disable_spd() call ......................................................................
asus/p3b-f,intel/i440bx: Move enable/disable_spd() call
Change-Id: I4a324dcebcd53439206205e64c5bbb7c6eac4fb2 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/asus/p3b-f/romstage.c M src/northbridge/intel/i440bx/raminit.c M src/northbridge/intel/i440bx/raminit.h 3 files changed, 13 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/38254/1
diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index e9630bf..8e254ba 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -49,7 +49,7 @@ * 24-30 of the PIIX4E (bit 31 is reserved). Thus, GPIOs 27 and 28 * control which SMBus/I2C offsets can be accessed. */ -static void enable_spd(void) +void enable_spd(void) { outb(0x6f, PM_IO_BASE + 0x37); } @@ -58,7 +58,7 @@ * Disable SPD access after RAM init to allow access to SMBus/I2C offsets * 0x48/0x49/0x2d, which is required e.g. by lm-sensors. */ -static void disable_spd(void) +void disable_spd(void) { outb(0x67, PM_IO_BASE + 0x37); } @@ -71,10 +71,8 @@ enable_smbus(); enable_pm();
- enable_spd();
sdram_initialize();
- disable_spd(); cbmem_initialize_empty(); } diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 0f9f2f6..28b22ec 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -1035,10 +1035,18 @@ DUMPNORTH(); }
+/* Implemented under mainboard. */ +void __weak enable_spd(void) { } +void __weak disable_spd(void) { } + void sdram_initialize(void) { + enable_spd(); + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); + + disable_spd(); } diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index 448f8d6..23299d1 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -20,6 +20,9 @@ /* The 440BX supports up to four (single- or double-sided) DIMMs. */ #define DIMM_SOCKETS 4
+void enable_spd(void); +void disable_spd(void); + /* Function prototypes. */ int spd_read_byte(unsigned int device, unsigned int address); void sdram_set_registers(void);
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38254 )
Change subject: asus/p3b-f,intel/i440bx: Move enable/disable_spd() call ......................................................................
Patch Set 1: Code-Review+1
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38254 )
Change subject: asus/p3b-f,intel/i440bx: Move enable/disable_spd() call ......................................................................
Patch Set 1: Code-Review+2
Not sure if these mainboard-specific things should be moved into the chipset code. However, given that barely anybody uses this code, I don't really care.
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38254 )
Change subject: asus/p3b-f,intel/i440bx: Move enable/disable_spd() call ......................................................................
asus/p3b-f,intel/i440bx: Move enable/disable_spd() call
Change-Id: I4a324dcebcd53439206205e64c5bbb7c6eac4fb2 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38254 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asus/p3b-f/romstage.c M src/northbridge/intel/i440bx/raminit.c M src/northbridge/intel/i440bx/raminit.h 3 files changed, 13 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index e9630bf..8e254ba 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -49,7 +49,7 @@ * 24-30 of the PIIX4E (bit 31 is reserved). Thus, GPIOs 27 and 28 * control which SMBus/I2C offsets can be accessed. */ -static void enable_spd(void) +void enable_spd(void) { outb(0x6f, PM_IO_BASE + 0x37); } @@ -58,7 +58,7 @@ * Disable SPD access after RAM init to allow access to SMBus/I2C offsets * 0x48/0x49/0x2d, which is required e.g. by lm-sensors. */ -static void disable_spd(void) +void disable_spd(void) { outb(0x67, PM_IO_BASE + 0x37); } @@ -71,10 +71,8 @@ enable_smbus(); enable_pm();
- enable_spd();
sdram_initialize();
- disable_spd(); cbmem_initialize_empty(); } diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 0f9f2f6..28b22ec 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -1035,10 +1035,18 @@ DUMPNORTH(); }
+/* Implemented under mainboard. */ +void __weak enable_spd(void) { } +void __weak disable_spd(void) { } + void sdram_initialize(void) { + enable_spd(); + dump_spd_registers(); sdram_set_registers(); sdram_set_spd_registers(); sdram_enable(); + + disable_spd(); } diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index 448f8d6..23299d1 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -20,6 +20,9 @@ /* The 440BX supports up to four (single- or double-sided) DIMMs. */ #define DIMM_SOCKETS 4
+void enable_spd(void); +void disable_spd(void); + /* Function prototypes. */ int spd_read_byte(unsigned int device, unsigned int address); void sdram_set_registers(void);
-
Angel Pons (Code Review) -
Kyösti Mälkki (Code Review)
-
Paul Menzel (Code Review)