Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38235 )
Change subject: intel/e7505,i82801dx: Remove wrapper spd_read_byte() ......................................................................
intel/e7505,i82801dx: Remove wrapper spd_read_byte()
Change-Id: I4a2d3043f77c9aa9c93b4718c5742fbd8d69b79f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/aopen/dxplplusu/romstage.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/e7505/raminit.h 3 files changed, 30 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/38235/1
diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index c647f96..0df6410 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -17,16 +17,10 @@ #include <cbmem.h> #include <console/console.h> #include <device/pci_type.h> -#include <device/smbus_host.h> #include <arch/romstage.h>
#include <northbridge/intel/e7505/raminit.h>
-int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - void mainboard_romstage_entry(void) { static const struct mem_controller memctrl[] = { @@ -40,7 +34,6 @@
/* If this is a warm boot, some initialization can be skipped */ if (!e7505_mch_is_ready()) { - enable_smbus();
/* The real MCH initialisation. */ e7505_mch_init(memctrl); diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 051b206..d8abc22 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -29,6 +29,7 @@ #include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> +#include <device/smbus_host.h> #include <lib.h> #include <commonlib/helpers.h> #include <console/console.h> @@ -338,20 +339,20 @@ pgsz.side2 = 0;
// Side 1 - value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); + value = smbus_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); if (value < 0) goto hw_err; pgsz.side1 = value & 0xf; // # columns in bank 1
/* Get the module data width and convert it to a power of two */ value = - spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB); + smbus_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB); if (value < 0) goto hw_err; module_data_width = (value & 0xff) << 8;
value = - spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB); + smbus_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB); if (value < 0) goto hw_err; module_data_width |= (value & 0xff); @@ -359,7 +360,7 @@ pgsz.side1 += log2(module_data_width);
/* side two */ - value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); + value = smbus_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); if (value < 0) goto hw_err; if (value > 2) @@ -368,7 +369,7 @@
pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently value = - spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); + smbus_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); if (value < 0) goto hw_err; if ((value & 0xf0) != 0) { @@ -400,7 +401,7 @@ width.side2 = 0;
value = - spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH); + smbus_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH); die_on_spd_error(value);
width.side1 = value & 0x7f; // Mask off bank 2 flag @@ -410,7 +411,7 @@ } else { // If bank 2 exists, it's the same width as bank 1 value = - spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); + smbus_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); die_on_spd_error(value);
if (value == 2) @@ -442,7 +443,7 @@
if (sz.side1 > 0) {
- value = spd_read_byte(dimm_socket_address, SPD_NUM_ROWS); + value = smbus_read_byte(dimm_socket_address, SPD_NUM_ROWS); die_on_spd_error(value);
sz.side1 += value & 0xf; @@ -457,7 +458,7 @@ }
value = - spd_read_byte(dimm_socket_address, + smbus_read_byte(dimm_socket_address, SPD_NUM_BANKS_PER_SDRAM); die_on_spd_error(value);
@@ -486,8 +487,8 @@ uint16_t dimm1_address) { uint8_t bEqual = 0; - int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number); - int dimm1_value = spd_read_byte(dimm1_address, spd_byte_number); + int dimm0_value = smbus_read_byte(dimm0_address, spd_byte_number); + int dimm1_value = smbus_read_byte(dimm1_address, spd_byte_number);
if ((dimm0_value >= 0) && (dimm1_value >= 0) && (dimm0_value == dimm1_value)) @@ -541,25 +542,25 @@ if (channel0_dimm == 0) continue; // No such socket on this mainboard
- if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != + if (smbus_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR) continue;
#ifdef VALIDATE_DIMM_COMPATIBILITY - if (spd_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) != + if (smbus_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) != SPD_VOLTAGE_SSTL2) continue; // Unsupported voltage
// E7501 does not support unregistered DIMMs spd_value = - spd_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES); + smbus_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES); if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) continue;
// Must support burst = 4 for dual-channel operation on E7501 // NOTE: for single-channel, burst = 8 is required spd_value = - spd_read_byte(channel0_dimm, + smbus_read_byte(channel0_dimm, SPD_SUPPORTED_BURST_LENGTHS); if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0)) continue; @@ -601,7 +602,7 @@
// NOTE: unpopulated DIMMs cause read to fail spd_value = - spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES); + smbus_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES); if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n"); @@ -609,7 +610,7 @@ } #ifdef VALIDATE_DIMM_COMPATIBILITY spd_value = - spd_read_byte(channel1_dimm, + smbus_read_byte(channel1_dimm, SPD_SUPPORTED_BURST_LENGTHS); if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0)) continue; @@ -943,7 +944,7 @@ ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
value = - spd_read_byte(dimm_socket_address, + smbus_read_byte(dimm_socket_address, SPD_MIN_ROW_PRECHARGE_TIME); if (value < 0) goto hw_err; @@ -951,7 +952,7 @@ slowest_row_precharge = value;
value = - spd_read_byte(dimm_socket_address, + smbus_read_byte(dimm_socket_address, SPD_MIN_RAS_TO_CAS_DELAY); if (value < 0) goto hw_err; @@ -959,7 +960,7 @@ slowest_ras_cas_delay = value;
value = - spd_read_byte(dimm_socket_address, + smbus_read_byte(dimm_socket_address, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); if (value < 0) goto hw_err; @@ -1076,7 +1077,7 @@ ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
value = - spd_read_byte(dimm_socket_address, + smbus_read_byte(dimm_socket_address, SPD_ACCEPTABLE_CAS_LATENCIES); if (value < 0) goto hw_err; @@ -1087,7 +1088,7 @@ // Can we support the highest CAS# latency?
value = - spd_read_byte(dimm_socket_address, + smbus_read_byte(dimm_socket_address, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); if (value < 0) goto hw_err; @@ -1103,7 +1104,7 @@ current_cas_latency >>= 1; if (current_cas_latency != 0) { value = - spd_read_byte(dimm_socket_address, + smbus_read_byte(dimm_socket_address, SPD_SDRAM_CYCLE_TIME_2ND); if (value < 0) goto hw_err; @@ -1115,7 +1116,7 @@ current_cas_latency >>= 1; if (current_cas_latency != 0) { value = - spd_read_byte(dimm_socket_address, + smbus_read_byte(dimm_socket_address, SPD_SDRAM_CYCLE_TIME_3RD); if (value < 0) goto hw_err; @@ -1248,14 +1249,14 @@ // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported.
value = - spd_read_byte(dimm_socket_address, + smbus_read_byte(dimm_socket_address, SPD_DIMM_CONFIG_TYPE); die_on_spd_error(value); if (value != ERROR_SCHEME_ECC) { controller_mode &= ~(3 << 20); }
- value = spd_read_byte(dimm_socket_address, SPD_REFRESH); + value = smbus_read_byte(dimm_socket_address, SPD_REFRESH); die_on_spd_error(value); value &= 0x7f; // Mask off self-refresh bit if (value > MAX_SPD_REFRESH_RATE) { @@ -1282,7 +1283,7 @@ // Switch to 2 clocks for address/command if required by any one of the DIMMs // NOTE: At 133 MHz, 1 clock == 7.52 ns value = - spd_read_byte(dimm_socket_address, + smbus_read_byte(dimm_socket_address, SPD_CMD_SIGNAL_INPUT_HOLD_TIME); die_on_spd_error(value); if (value >= 0xa0) { /* At 133MHz this constant should be 0x75 */ @@ -1766,6 +1767,8 @@ { timestamp_add_now(TS_BEFORE_INITRAM);
+ enable_smbus(); + sdram_set_registers(memctrl); sdram_set_spd_registers(memctrl); sdram_enable(memctrl); diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index f3fc264..c65675f 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -34,8 +34,4 @@ void e7505_mch_done(const struct mem_controller *memctrl); int e7505_mch_is_ready(void);
- -/* Mainboard exports this. */ -int spd_read_byte(unsigned int device, unsigned int address); - #endif /* RAMINIT_H */
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38235
to look at the new patch set (#4).
Change subject: intel/e7505,i82801dx: Remove wrapper spd_read_byte() ......................................................................
intel/e7505,i82801dx: Remove wrapper spd_read_byte()
Change-Id: I4a2d3043f77c9aa9c93b4718c5742fbd8d69b79f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/aopen/dxplplusu/romstage.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/e7505/raminit.h 3 files changed, 28 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/38235/4
Idwer Vollering has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38235 )
Change subject: intel/e7505,i82801dx: Remove wrapper spd_read_byte() ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38235/4/src/northbridge/intel/e7505... File src/northbridge/intel/e7505/raminit.c:
https://review.coreboot.org/c/coreboot/+/38235/4/src/northbridge/intel/e7505... PS4, Line 1286: smbus_read_byte(dimm_socket_address, Are you aware that this ifdef section is compiled out?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38235 )
Change subject: intel/e7505,i82801dx: Remove wrapper spd_read_byte() ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/38235/4/src/northbridge/intel/e7505... File src/northbridge/intel/e7505/raminit.c:
https://review.coreboot.org/c/coreboot/+/38235/4/src/northbridge/intel/e7505... PS4, Line 1251: value = This could be reflowed, I guess.
https://review.coreboot.org/c/coreboot/+/38235/4/src/northbridge/intel/e7505... PS4, Line 1286: smbus_read_byte(dimm_socket_address,
Are you aware that this ifdef section is compiled out?
Even then, not replacing the function call would be worse (the code would rot)
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38235 )
Change subject: intel/e7505,i82801dx: Remove wrapper spd_read_byte() ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38235/4/src/northbridge/intel/e7505... File src/northbridge/intel/e7505/raminit.c:
https://review.coreboot.org/c/coreboot/+/38235/4/src/northbridge/intel/e7505... PS4, Line 1286: smbus_read_byte(dimm_socket_address,
Even then, not replacing the function call would be worse (the code would rot)
I have some follow-up on the topic, I'll touch this then.
There is enough CAR to hold the entire SPDs instead, no need to read them individually.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38235 )
Change subject: intel/e7505,i82801dx: Remove wrapper spd_read_byte() ......................................................................
Patch Set 4: Code-Review+2
Hello Patrick Rudolph, Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38235
to look at the new patch set (#5).
Change subject: intel/e7505,i82801dx: Remove wrapper spd_read_byte() ......................................................................
intel/e7505,i82801dx: Remove wrapper spd_read_byte()
Change-Id: I4a2d3043f77c9aa9c93b4718c5742fbd8d69b79f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/aopen/dxplplusu/romstage.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/e7505/raminit.h 3 files changed, 28 insertions(+), 55 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/38235/5
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38235 )
Change subject: intel/e7505,i82801dx: Remove wrapper spd_read_byte() ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38235/4/src/northbridge/intel/e7505... File src/northbridge/intel/e7505/raminit.c:
https://review.coreboot.org/c/coreboot/+/38235/4/src/northbridge/intel/e7505... PS4, Line 1251: value =
This could be reflowed, I guess.
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38235 )
Change subject: intel/e7505,i82801dx: Remove wrapper spd_read_byte() ......................................................................
Patch Set 6: Code-Review+2
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38235 )
Change subject: intel/e7505,i82801dx: Remove wrapper spd_read_byte() ......................................................................
intel/e7505,i82801dx: Remove wrapper spd_read_byte()
Change-Id: I4a2d3043f77c9aa9c93b4718c5742fbd8d69b79f Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38235 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/aopen/dxplplusu/romstage.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/e7505/raminit.h 3 files changed, 28 insertions(+), 55 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 7f66fc5..6c74c1f 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -21,11 +21,6 @@ #include <southbridge/intel/i82801dx/i82801dx.h> #include <northbridge/intel/e7505/raminit.h>
-int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - void mainboard_romstage_entry(void) { static const struct mem_controller memctrl[] = { diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 051b206..972a2f3 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -39,6 +39,7 @@ #include <spd.h> #include <sdram_mode.h> #include <timestamp.h> +#include <southbridge/intel/i82801dx/i82801dx.h>
#include "raminit.h" #include "e7505.h" @@ -338,20 +339,18 @@ pgsz.side2 = 0;
// Side 1 - value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); + value = smbus_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); if (value < 0) goto hw_err; pgsz.side1 = value & 0xf; // # columns in bank 1
/* Get the module data width and convert it to a power of two */ - value = - spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB); + value = smbus_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB); if (value < 0) goto hw_err; module_data_width = (value & 0xff) << 8;
- value = - spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB); + value = smbus_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB); if (value < 0) goto hw_err; module_data_width |= (value & 0xff); @@ -359,7 +358,7 @@ pgsz.side1 += log2(module_data_width);
/* side two */ - value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); + value = smbus_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); if (value < 0) goto hw_err; if (value > 2) @@ -367,8 +366,7 @@ if (value == 2) {
pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently - value = - spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); + value = smbus_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); if (value < 0) goto hw_err; if ((value & 0xf0) != 0) { @@ -399,8 +397,7 @@ width.side1 = 0; width.side2 = 0;
- value = - spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH); + value = smbus_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH); die_on_spd_error(value);
width.side1 = value & 0x7f; // Mask off bank 2 flag @@ -409,8 +406,7 @@ width.side2 = width.side1 << 1; // Bank 2 exists and is double-width } else { // If bank 2 exists, it's the same width as bank 1 - value = - spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); + value = smbus_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); die_on_spd_error(value);
if (value == 2) @@ -442,7 +438,7 @@
if (sz.side1 > 0) {
- value = spd_read_byte(dimm_socket_address, SPD_NUM_ROWS); + value = smbus_read_byte(dimm_socket_address, SPD_NUM_ROWS); die_on_spd_error(value);
sz.side1 += value & 0xf; @@ -456,8 +452,7 @@ sz.side2 += value; // Symmetric }
- value = - spd_read_byte(dimm_socket_address, + value = smbus_read_byte(dimm_socket_address, SPD_NUM_BANKS_PER_SDRAM); die_on_spd_error(value);
@@ -486,8 +481,8 @@ uint16_t dimm1_address) { uint8_t bEqual = 0; - int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number); - int dimm1_value = spd_read_byte(dimm1_address, spd_byte_number); + int dimm0_value = smbus_read_byte(dimm0_address, spd_byte_number); + int dimm1_value = smbus_read_byte(dimm1_address, spd_byte_number);
if ((dimm0_value >= 0) && (dimm1_value >= 0) && (dimm0_value == dimm1_value)) @@ -541,25 +536,23 @@ if (channel0_dimm == 0) continue; // No such socket on this mainboard
- if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != + if (smbus_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR) continue;
#ifdef VALIDATE_DIMM_COMPATIBILITY - if (spd_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) != + if (smbus_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) != SPD_VOLTAGE_SSTL2) continue; // Unsupported voltage
// E7501 does not support unregistered DIMMs - spd_value = - spd_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES); + spd_value = smbus_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES); if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) continue;
// Must support burst = 4 for dual-channel operation on E7501 // NOTE: for single-channel, burst = 8 is required - spd_value = - spd_read_byte(channel0_dimm, + spd_value = smbus_read_byte(channel0_dimm, SPD_SUPPORTED_BURST_LENGTHS); if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0)) continue; @@ -600,16 +593,14 @@ ASSERT(channel1_dimm != 0); // No such socket on this mainboard??
// NOTE: unpopulated DIMMs cause read to fail - spd_value = - spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES); + spd_value = smbus_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES); if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n"); continue; } #ifdef VALIDATE_DIMM_COMPATIBILITY - spd_value = - spd_read_byte(channel1_dimm, + spd_value = smbus_read_byte(channel1_dimm, SPD_SUPPORTED_BURST_LENGTHS); if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0)) continue; @@ -942,24 +933,21 @@ dimm_socket_address = ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
- value = - spd_read_byte(dimm_socket_address, + value = smbus_read_byte(dimm_socket_address, SPD_MIN_ROW_PRECHARGE_TIME); if (value < 0) goto hw_err; if (value > slowest_row_precharge) slowest_row_precharge = value;
- value = - spd_read_byte(dimm_socket_address, + value = smbus_read_byte(dimm_socket_address, SPD_MIN_RAS_TO_CAS_DELAY); if (value < 0) goto hw_err; if (value > slowest_ras_cas_delay) slowest_ras_cas_delay = value;
- value = - spd_read_byte(dimm_socket_address, + value = smbus_read_byte(dimm_socket_address, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); if (value < 0) goto hw_err; @@ -1075,8 +1063,7 @@ dimm_socket_address = ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL];
- value = - spd_read_byte(dimm_socket_address, + value = smbus_read_byte(dimm_socket_address, SPD_ACCEPTABLE_CAS_LATENCIES); if (value < 0) goto hw_err; @@ -1086,8 +1073,7 @@
// Can we support the highest CAS# latency?
- value = - spd_read_byte(dimm_socket_address, + value = smbus_read_byte(dimm_socket_address, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); if (value < 0) goto hw_err; @@ -1102,8 +1088,7 @@
current_cas_latency >>= 1; if (current_cas_latency != 0) { - value = - spd_read_byte(dimm_socket_address, + value = smbus_read_byte(dimm_socket_address, SPD_SDRAM_CYCLE_TIME_2ND); if (value < 0) goto hw_err; @@ -1114,8 +1099,7 @@ // Can we support the next-highest CAS# latency (max - 1.0)? current_cas_latency >>= 1; if (current_cas_latency != 0) { - value = - spd_read_byte(dimm_socket_address, + value = smbus_read_byte(dimm_socket_address, SPD_SDRAM_CYCLE_TIME_3RD); if (value < 0) goto hw_err; @@ -1247,15 +1231,14 @@ // Disable ECC mode if any one of the DIMMs does not support ECC // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported.
- value = - spd_read_byte(dimm_socket_address, + value = smbus_read_byte(dimm_socket_address, SPD_DIMM_CONFIG_TYPE); die_on_spd_error(value); if (value != ERROR_SCHEME_ECC) { controller_mode &= ~(3 << 20); }
- value = spd_read_byte(dimm_socket_address, SPD_REFRESH); + value = smbus_read_byte(dimm_socket_address, SPD_REFRESH); die_on_spd_error(value); value &= 0x7f; // Mask off self-refresh bit if (value > MAX_SPD_REFRESH_RATE) { @@ -1281,8 +1264,7 @@
// Switch to 2 clocks for address/command if required by any one of the DIMMs // NOTE: At 133 MHz, 1 clock == 7.52 ns - value = - spd_read_byte(dimm_socket_address, + value = smbus_read_byte(dimm_socket_address, SPD_CMD_SIGNAL_INPUT_HOLD_TIME); die_on_spd_error(value); if (value >= 0xa0) { /* At 133MHz this constant should be 0x75 */ diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index f3fc264..c65675f 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -34,8 +34,4 @@ void e7505_mch_done(const struct mem_controller *memctrl); int e7505_mch_is_ready(void);
- -/* Mainboard exports this. */ -int spd_read_byte(unsigned int device, unsigned int address); - #endif /* RAMINIT_H */
-
Angel Pons (Code Review) -
Idwer Vollering (Code Review)
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Kyösti Mälkki (Code Review)