Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38186 )
Change subject: console/post: Move cmos_post_code() under pc80/rtc ......................................................................
console/post: Move cmos_post_code() under pc80/rtc
We should keep console/ somewhat arch-agnostic.
Change-Id: I4465888023ba5ae0706b5e98e541c40f975d11e3 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/console/post.c M src/drivers/pc80/rtc/Makefile.inc A src/drivers/pc80/rtc/post.c M src/include/console/console.h 4 files changed, 147 insertions(+), 133 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/38186/1
diff --git a/src/console/post.c b/src/console/post.c index 9d535cb..b9a7557 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -13,11 +13,7 @@ */
#include <stdint.h> -#include <elog.h> #include <console/console.h> -#include <device/device.h> -#include <pc80/mc146818rtc.h> -#include <smp/spinlock.h> #if CONFIG(POST_IO) #include <arch/io.h> #endif @@ -27,135 +23,7 @@ /* Some mainboards have very nice features beyond just a simple display. * They can override this function. */ -void __weak mainboard_post(uint8_t value) -{ -} - -#if CONFIG(CMOS_POST) - -DECLARE_SPIN_LOCK(cmos_post_lock) - -void cmos_post_log(void) -{ - u8 code = 0; -#if CONFIG(CMOS_POST_EXTRA) - u32 extra = 0; -#endif - - spin_lock(&cmos_post_lock); - - /* Get post code from other bank */ - switch (cmos_read(CMOS_POST_BANK_OFFSET)) { - case CMOS_POST_BANK_0_MAGIC: - code = cmos_read(CMOS_POST_BANK_1_OFFSET); -#if CONFIG(CMOS_POST_EXTRA) - extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); -#endif - break; - case CMOS_POST_BANK_1_MAGIC: - code = cmos_read(CMOS_POST_BANK_0_OFFSET); -#if CONFIG(CMOS_POST_EXTRA) - extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); -#endif - break; - } - - spin_unlock(&cmos_post_lock); - - /* Check last post code in previous boot against normal list */ - switch (code) { - case POST_OS_BOOT: - case POST_OS_RESUME: - case POST_ENTER_ELF_BOOT: - case 0: - break; - default: - printk(BIOS_WARNING, "POST: Unexpected post code " - "in previous boot: 0x%02x\n", code); -#if CONFIG(ELOG) && (ENV_RAMSTAGE || CONFIG(ELOG_PRERAM)) - elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); -#if CONFIG(CMOS_POST_EXTRA) - if (extra) - elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra); -#endif -#endif - } -} - -void cmos_post_init(void) -{ - u8 magic = CMOS_POST_BANK_0_MAGIC; - - /* Switch to the other bank */ - switch (cmos_read(CMOS_POST_BANK_OFFSET)) { - case CMOS_POST_BANK_1_MAGIC: - break; - case CMOS_POST_BANK_0_MAGIC: - magic = CMOS_POST_BANK_1_MAGIC; - break; - default: - /* Initialize to zero */ - cmos_write(0, CMOS_POST_BANK_0_OFFSET); - cmos_write(0, CMOS_POST_BANK_1_OFFSET); -#if CONFIG(CMOS_POST_EXTRA) - cmos_write32(0, CMOS_POST_BANK_0_EXTRA); - cmos_write32(0, CMOS_POST_BANK_1_EXTRA); -#endif - } - - cmos_write(magic, CMOS_POST_BANK_OFFSET); -} - -#if CONFIG(CMOS_POST_EXTRA) -void post_log_extra(u32 value) -{ - spin_lock(&cmos_post_lock); - - switch (cmos_read(CMOS_POST_BANK_OFFSET)) { - case CMOS_POST_BANK_0_MAGIC: - cmos_write32(value, CMOS_POST_BANK_0_EXTRA); - break; - case CMOS_POST_BANK_1_MAGIC: - cmos_write32(value, CMOS_POST_BANK_1_EXTRA); - break; - } - - spin_unlock(&cmos_post_lock); -} - -void post_log_path(const struct device *dev) -{ - if (dev) { - /* Encode path into lower 3 bytes */ - u32 path = dev_path_encode(dev); - /* Upper byte contains the log type */ - path |= CMOS_POST_EXTRA_DEV_PATH << 24; - post_log_extra(path); - } -} - -void post_log_clear(void) -{ - post_log_extra(0); -} -#endif /* CONFIG_CMOS_POST_EXTRA */ - -static void cmos_post_code(u8 value) -{ - spin_lock(&cmos_post_lock); - - switch (cmos_read(CMOS_POST_BANK_OFFSET)) { - case CMOS_POST_BANK_0_MAGIC: - cmos_write(value, CMOS_POST_BANK_0_OFFSET); - break; - case CMOS_POST_BANK_1_MAGIC: - cmos_write(value, CMOS_POST_BANK_1_OFFSET); - break; - } - - spin_unlock(&cmos_post_lock); -} -#endif /* CONFIG_CMOS_POST */ +void __weak mainboard_post(uint8_t value) { }
void post_code(uint8_t value) { diff --git a/src/drivers/pc80/rtc/Makefile.inc b/src/drivers/pc80/rtc/Makefile.inc index 998b7e7..eb0ff6f 100644 --- a/src/drivers/pc80/rtc/Makefile.inc +++ b/src/drivers/pc80/rtc/Makefile.inc @@ -7,6 +7,8 @@ ramstage-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c smm-$(CONFIG_DRIVERS_MC146818) += mc146818rtc.c
+all-$(CONFIG_CMOS_POST) += post.c + ifeq ($(CONFIG_USE_OPTION_TABLE),y) cbfs-files-$(CONFIG_HAVE_CMOS_DEFAULT) += cmos.default cmos.default-file = $(CONFIG_CMOS_DEFAULT_FILE):nvramtool diff --git a/src/drivers/pc80/rtc/post.c b/src/drivers/pc80/rtc/post.c new file mode 100644 index 0000000..e559edf --- /dev/null +++ b/src/drivers/pc80/rtc/post.c @@ -0,0 +1,143 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <elog.h> +#include <console/console.h> +#include <device/device.h> +#include <pc80/mc146818rtc.h> +#include <smp/spinlock.h> + +DECLARE_SPIN_LOCK(cmos_post_lock) + +void cmos_post_log(void) +{ + u8 code = 0; +#if CONFIG(CMOS_POST_EXTRA) + u32 extra = 0; +#endif + + spin_lock(&cmos_post_lock); + + /* Get post code from other bank */ + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_0_MAGIC: + code = cmos_read(CMOS_POST_BANK_1_OFFSET); +#if CONFIG(CMOS_POST_EXTRA) + extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); +#endif + break; + case CMOS_POST_BANK_1_MAGIC: + code = cmos_read(CMOS_POST_BANK_0_OFFSET); +#if CONFIG(CMOS_POST_EXTRA) + extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); +#endif + break; + } + + spin_unlock(&cmos_post_lock); + + /* Check last post code in previous boot against normal list */ + switch (code) { + case POST_OS_BOOT: + case POST_OS_RESUME: + case POST_ENTER_ELF_BOOT: + case 0: + break; + default: + printk(BIOS_WARNING, "POST: Unexpected post code " + "in previous boot: 0x%02x\n", code); +#if CONFIG(ELOG) && (ENV_RAMSTAGE || CONFIG(ELOG_PRERAM)) + elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); +#if CONFIG(CMOS_POST_EXTRA) + if (extra) + elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra); +#endif +#endif + } +} + +void cmos_post_init(void) +{ + u8 magic = CMOS_POST_BANK_0_MAGIC; + + /* Switch to the other bank */ + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_1_MAGIC: + break; + case CMOS_POST_BANK_0_MAGIC: + magic = CMOS_POST_BANK_1_MAGIC; + break; + default: + /* Initialize to zero */ + cmos_write(0, CMOS_POST_BANK_0_OFFSET); + cmos_write(0, CMOS_POST_BANK_1_OFFSET); +#if CONFIG(CMOS_POST_EXTRA) + cmos_write32(0, CMOS_POST_BANK_0_EXTRA); + cmos_write32(0, CMOS_POST_BANK_1_EXTRA); +#endif + } + + cmos_write(magic, CMOS_POST_BANK_OFFSET); +} + +#if CONFIG(CMOS_POST_EXTRA) +void post_log_extra(u32 value) +{ + spin_lock(&cmos_post_lock); + + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_0_MAGIC: + cmos_write32(value, CMOS_POST_BANK_0_EXTRA); + break; + case CMOS_POST_BANK_1_MAGIC: + cmos_write32(value, CMOS_POST_BANK_1_EXTRA); + break; + } + + spin_unlock(&cmos_post_lock); +} + +void post_log_path(const struct device *dev) +{ + if (dev) { + /* Encode path into lower 3 bytes */ + u32 path = dev_path_encode(dev); + /* Upper byte contains the log type */ + path |= CMOS_POST_EXTRA_DEV_PATH << 24; + post_log_extra(path); + } +} + +void post_log_clear(void) +{ + post_log_extra(0); +} +#endif /* CONFIG_CMOS_POST_EXTRA */ + +void cmos_post_code(u8 value) +{ + spin_lock(&cmos_post_lock); + + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_0_MAGIC: + cmos_write(value, CMOS_POST_BANK_0_OFFSET); + break; + case CMOS_POST_BANK_1_MAGIC: + cmos_write(value, CMOS_POST_BANK_1_OFFSET); + break; + } + + spin_unlock(&cmos_post_lock); +} diff --git a/src/include/console/console.h b/src/include/console/console.h index 583420c..d3c1d54 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -29,6 +29,7 @@ #include <console/vtxprintf.h>
void post_code(u8 value); +void cmos_post_code(u8 value); #if CONFIG(CMOS_POST_EXTRA) void post_log_extra(u32 value); struct device;
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38186
to look at the new patch set (#2).
Change subject: console/post: Move cmos_post_code() under pc80/rtc ......................................................................
console/post: Move cmos_post_code() under pc80/rtc
We should keep console/ somewhat arch-agnostic.
Change-Id: I4465888023ba5ae0706b5e98e541c40f975d11e3 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/console/post.c M src/drivers/pc80/rtc/Makefile.inc A src/drivers/pc80/rtc/post.c M src/include/console/console.h 4 files changed, 147 insertions(+), 133 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/38186/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38186 )
Change subject: console/post: Move cmos_post_code() under pc80/rtc ......................................................................
Patch Set 4: Code-Review+2
Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38186 )
Change subject: console/post: Move cmos_post_code() under pc80/rtc ......................................................................
console/post: Move cmos_post_code() under pc80/rtc
We should keep console/ somewhat arch-agnostic.
Change-Id: I4465888023ba5ae0706b5e98e541c40f975d11e3 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/38186 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/console/post.c M src/drivers/pc80/rtc/Makefile.inc A src/drivers/pc80/rtc/post.c M src/include/console/console.h 4 files changed, 147 insertions(+), 133 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/console/post.c b/src/console/post.c index 9d535cb..b9a7557 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -13,11 +13,7 @@ */
#include <stdint.h> -#include <elog.h> #include <console/console.h> -#include <device/device.h> -#include <pc80/mc146818rtc.h> -#include <smp/spinlock.h> #if CONFIG(POST_IO) #include <arch/io.h> #endif @@ -27,135 +23,7 @@ /* Some mainboards have very nice features beyond just a simple display. * They can override this function. */ -void __weak mainboard_post(uint8_t value) -{ -} - -#if CONFIG(CMOS_POST) - -DECLARE_SPIN_LOCK(cmos_post_lock) - -void cmos_post_log(void) -{ - u8 code = 0; -#if CONFIG(CMOS_POST_EXTRA) - u32 extra = 0; -#endif - - spin_lock(&cmos_post_lock); - - /* Get post code from other bank */ - switch (cmos_read(CMOS_POST_BANK_OFFSET)) { - case CMOS_POST_BANK_0_MAGIC: - code = cmos_read(CMOS_POST_BANK_1_OFFSET); -#if CONFIG(CMOS_POST_EXTRA) - extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); -#endif - break; - case CMOS_POST_BANK_1_MAGIC: - code = cmos_read(CMOS_POST_BANK_0_OFFSET); -#if CONFIG(CMOS_POST_EXTRA) - extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); -#endif - break; - } - - spin_unlock(&cmos_post_lock); - - /* Check last post code in previous boot against normal list */ - switch (code) { - case POST_OS_BOOT: - case POST_OS_RESUME: - case POST_ENTER_ELF_BOOT: - case 0: - break; - default: - printk(BIOS_WARNING, "POST: Unexpected post code " - "in previous boot: 0x%02x\n", code); -#if CONFIG(ELOG) && (ENV_RAMSTAGE || CONFIG(ELOG_PRERAM)) - elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); -#if CONFIG(CMOS_POST_EXTRA) - if (extra) - elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra); -#endif -#endif - } -} - -void cmos_post_init(void) -{ - u8 magic = CMOS_POST_BANK_0_MAGIC; - - /* Switch to the other bank */ - switch (cmos_read(CMOS_POST_BANK_OFFSET)) { - case CMOS_POST_BANK_1_MAGIC: - break; - case CMOS_POST_BANK_0_MAGIC: - magic = CMOS_POST_BANK_1_MAGIC; - break; - default: - /* Initialize to zero */ - cmos_write(0, CMOS_POST_BANK_0_OFFSET); - cmos_write(0, CMOS_POST_BANK_1_OFFSET); -#if CONFIG(CMOS_POST_EXTRA) - cmos_write32(0, CMOS_POST_BANK_0_EXTRA); - cmos_write32(0, CMOS_POST_BANK_1_EXTRA); -#endif - } - - cmos_write(magic, CMOS_POST_BANK_OFFSET); -} - -#if CONFIG(CMOS_POST_EXTRA) -void post_log_extra(u32 value) -{ - spin_lock(&cmos_post_lock); - - switch (cmos_read(CMOS_POST_BANK_OFFSET)) { - case CMOS_POST_BANK_0_MAGIC: - cmos_write32(value, CMOS_POST_BANK_0_EXTRA); - break; - case CMOS_POST_BANK_1_MAGIC: - cmos_write32(value, CMOS_POST_BANK_1_EXTRA); - break; - } - - spin_unlock(&cmos_post_lock); -} - -void post_log_path(const struct device *dev) -{ - if (dev) { - /* Encode path into lower 3 bytes */ - u32 path = dev_path_encode(dev); - /* Upper byte contains the log type */ - path |= CMOS_POST_EXTRA_DEV_PATH << 24; - post_log_extra(path); - } -} - -void post_log_clear(void) -{ - post_log_extra(0); -} -#endif /* CONFIG_CMOS_POST_EXTRA */ - -static void cmos_post_code(u8 value) -{ - spin_lock(&cmos_post_lock); - - switch (cmos_read(CMOS_POST_BANK_OFFSET)) { - case CMOS_POST_BANK_0_MAGIC: - cmos_write(value, CMOS_POST_BANK_0_OFFSET); - break; - case CMOS_POST_BANK_1_MAGIC: - cmos_write(value, CMOS_POST_BANK_1_OFFSET); - break; - } - - spin_unlock(&cmos_post_lock); -} -#endif /* CONFIG_CMOS_POST */ +void __weak mainboard_post(uint8_t value) { }
void post_code(uint8_t value) { diff --git a/src/drivers/pc80/rtc/Makefile.inc b/src/drivers/pc80/rtc/Makefile.inc index 95b25d6..4938d78 100644 --- a/src/drivers/pc80/rtc/Makefile.inc +++ b/src/drivers/pc80/rtc/Makefile.inc @@ -11,6 +11,8 @@ all-$(CONFIG_USE_OPTION_TABLE) += option.c smm-$(CONFIG_USE_OPTION_TABLE) += option.c
+all-$(CONFIG_CMOS_POST) += post.c + ifeq ($(CONFIG_USE_OPTION_TABLE),y) cbfs-files-$(CONFIG_HAVE_CMOS_DEFAULT) += cmos.default cmos.default-file = $(CONFIG_CMOS_DEFAULT_FILE):nvramtool diff --git a/src/drivers/pc80/rtc/post.c b/src/drivers/pc80/rtc/post.c new file mode 100644 index 0000000..e559edf --- /dev/null +++ b/src/drivers/pc80/rtc/post.c @@ -0,0 +1,143 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <elog.h> +#include <console/console.h> +#include <device/device.h> +#include <pc80/mc146818rtc.h> +#include <smp/spinlock.h> + +DECLARE_SPIN_LOCK(cmos_post_lock) + +void cmos_post_log(void) +{ + u8 code = 0; +#if CONFIG(CMOS_POST_EXTRA) + u32 extra = 0; +#endif + + spin_lock(&cmos_post_lock); + + /* Get post code from other bank */ + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_0_MAGIC: + code = cmos_read(CMOS_POST_BANK_1_OFFSET); +#if CONFIG(CMOS_POST_EXTRA) + extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); +#endif + break; + case CMOS_POST_BANK_1_MAGIC: + code = cmos_read(CMOS_POST_BANK_0_OFFSET); +#if CONFIG(CMOS_POST_EXTRA) + extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); +#endif + break; + } + + spin_unlock(&cmos_post_lock); + + /* Check last post code in previous boot against normal list */ + switch (code) { + case POST_OS_BOOT: + case POST_OS_RESUME: + case POST_ENTER_ELF_BOOT: + case 0: + break; + default: + printk(BIOS_WARNING, "POST: Unexpected post code " + "in previous boot: 0x%02x\n", code); +#if CONFIG(ELOG) && (ENV_RAMSTAGE || CONFIG(ELOG_PRERAM)) + elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); +#if CONFIG(CMOS_POST_EXTRA) + if (extra) + elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra); +#endif +#endif + } +} + +void cmos_post_init(void) +{ + u8 magic = CMOS_POST_BANK_0_MAGIC; + + /* Switch to the other bank */ + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_1_MAGIC: + break; + case CMOS_POST_BANK_0_MAGIC: + magic = CMOS_POST_BANK_1_MAGIC; + break; + default: + /* Initialize to zero */ + cmos_write(0, CMOS_POST_BANK_0_OFFSET); + cmos_write(0, CMOS_POST_BANK_1_OFFSET); +#if CONFIG(CMOS_POST_EXTRA) + cmos_write32(0, CMOS_POST_BANK_0_EXTRA); + cmos_write32(0, CMOS_POST_BANK_1_EXTRA); +#endif + } + + cmos_write(magic, CMOS_POST_BANK_OFFSET); +} + +#if CONFIG(CMOS_POST_EXTRA) +void post_log_extra(u32 value) +{ + spin_lock(&cmos_post_lock); + + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_0_MAGIC: + cmos_write32(value, CMOS_POST_BANK_0_EXTRA); + break; + case CMOS_POST_BANK_1_MAGIC: + cmos_write32(value, CMOS_POST_BANK_1_EXTRA); + break; + } + + spin_unlock(&cmos_post_lock); +} + +void post_log_path(const struct device *dev) +{ + if (dev) { + /* Encode path into lower 3 bytes */ + u32 path = dev_path_encode(dev); + /* Upper byte contains the log type */ + path |= CMOS_POST_EXTRA_DEV_PATH << 24; + post_log_extra(path); + } +} + +void post_log_clear(void) +{ + post_log_extra(0); +} +#endif /* CONFIG_CMOS_POST_EXTRA */ + +void cmos_post_code(u8 value) +{ + spin_lock(&cmos_post_lock); + + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_0_MAGIC: + cmos_write(value, CMOS_POST_BANK_0_OFFSET); + break; + case CMOS_POST_BANK_1_MAGIC: + cmos_write(value, CMOS_POST_BANK_1_OFFSET); + break; + } + + spin_unlock(&cmos_post_lock); +} diff --git a/src/include/console/console.h b/src/include/console/console.h index 583420c..d3c1d54 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -29,6 +29,7 @@ #include <console/vtxprintf.h>
void post_code(u8 value); +void cmos_post_code(u8 value); #if CONFIG(CMOS_POST_EXTRA) void post_log_extra(u32 value); struct device;
-
Angel Pons (Code Review) -
Kyösti Mälkki (Code Review)
-
Nico Huber (Code Review)