Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38124 )
Change subject: drivers/intel/fsp2_0/logo.c: Correct check for logo_size
......................................................................
drivers/intel/fsp2_0/logo.c: Correct check for logo_size
The check to validate if the logo file was loaded correctly was
incorrect.
Now check the actual logo size.
BUG=N/A
TEST=build
Change-Id: Ib3a808dd831986e8347512892ee88983d376d34c
Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com>
---
M src/drivers/intel/fsp2_0/logo.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38124/1
diff --git a/src/drivers/intel/fsp2_0/logo.c b/src/drivers/intel/fsp2_0/logo.c
index ba2b5dc..1a9152f 100644
--- a/src/drivers/intel/fsp2_0/logo.c
+++ b/src/drivers/intel/fsp2_0/logo.c
@@ -26,7 +26,7 @@
if (logo_buffer) {
*logo_size = cbfs_boot_load_file("logo.bmp", (void *)logo_buffer,
1 * MiB, CBFS_TYPE_RAW);
- if (logo_size)
+ if (*logo_size)
*logo_ptr = (UINT32)logo_buffer;
}
}
--
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Gerrit-Branch: master
Gerrit-Change-Id: Ib3a808dd831986e8347512892ee88983d376d34c
Gerrit-Change-Number: 38124
Gerrit-PatchSet: 1
Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com>
Gerrit-MessageType: newchange
Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38123 )
Change subject: drivers/intel/fsp1_1/logo.c: Correct check for logo_size
......................................................................
drivers/intel/fsp1_1/logo.c: Correct check for logo_size
The check to validate if the logo file was loaded correctly was
incorrect.
Now check the actual logo size.
BUG=N/A
TEST=build
Change-Id: I4df2076b2f0cc371848a912c622268dfec24e2ef
Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com>
---
M src/drivers/intel/fsp1_1/logo.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/38123/1
diff --git a/src/drivers/intel/fsp1_1/logo.c b/src/drivers/intel/fsp1_1/logo.c
index 23aad01..b00406d 100644
--- a/src/drivers/intel/fsp1_1/logo.c
+++ b/src/drivers/intel/fsp1_1/logo.c
@@ -26,7 +26,7 @@
if (logo_buffer) {
*logo_size = cbfs_boot_load_file("logo.bmp", (void *)logo_buffer,
1 * MiB, CBFS_TYPE_RAW);
- if (logo_size)
+ if (*logo_size)
*logo_ptr = (UINT32)logo_buffer;
}
}
--
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Gerrit-Change-Id: I4df2076b2f0cc371848a912c622268dfec24e2ef
Gerrit-Change-Number: 38123
Gerrit-PatchSet: 1
Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com>
Gerrit-MessageType: newchange
huayang duan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37924 )
Change subject: mainboard/google/kukui: Restore vcore to default voltage after DRAM calibration
......................................................................
mainboard/google/kukui: Restore vcore to default voltage after DRAM calibration
DRAM calibration will set vcore to different voltage for different frequency,
after DRAM calibration should restore vcore to default volatge
BRANCH=none
BUG=none
TEST=bootup pass
Change-Id: Ia87b4ac78a32dbd4c4ab52e84d307cb46525afa1
Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com>
---
M src/mainboard/google/kukui/romstage.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/37924/1
diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c
index 2b7dd6a..a34b35e 100644
--- a/src/mainboard/google/kukui/romstage.c
+++ b/src/mainboard/google/kukui/romstage.c
@@ -74,5 +74,8 @@
pmic_init_scp_voltage();
rtc_boot();
mt_mem_init(&dparam_ops);
+
+ /* after DRAM calibration, restore vcore voltage to default setting */
+ pmic_set_vcore_vol(800000);
mtk_mmu_after_dram();
}
--
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Gerrit-Change-Id: Ia87b4ac78a32dbd4c4ab52e84d307cb46525afa1
Gerrit-Change-Number: 37924
Gerrit-PatchSet: 1
Gerrit-Owner: huayang duan <huayangduan(a)gmail.com>
Gerrit-MessageType: newchange
Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37399 )
Change subject: mb/lenovo/t530/devicetree: Use subsystemid inheritance
......................................................................
mb/lenovo/t530/devicetree: Use subsystemid inheritance
Missing PCI IDs are checked against those collected at
https://github.com/linuxhw/LsPCI/tree/master/Notebook/Lenovo/ThinkPad.
Change-Id: I61457b7a791dc3341d582f67e651acc6230c525c
Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com>
---
M src/mainboard/lenovo/t530/variants/t530/devicetree.cb
1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/37399/1
diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb
index 190539a..47e40c3 100644
--- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb
+++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb
@@ -37,6 +37,8 @@
register "pci_mmio_size" = "2048"
device domain 0 on
+ subsystemid 0x17aa 0x21f6 inherit
+
device pci 00.0 on end # host bridge
device pci 01.0 on end # PCIe Bridge for discrete graphics
device pci 02.0 on end # vga controller
@@ -77,7 +79,9 @@
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
- device pci 19.0 on end # Intel Gigabit Ethernet
+ device pci 19.0 on # Intel Gigabit Ethernet
+ subsystemid 0x17aa 0x21f3
+ end
device pci 1a.0 on end # USB2 EHCI #2
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe Port #1
--
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Gerrit-Change-Id: I61457b7a791dc3341d582f67e651acc6230c525c
Gerrit-Change-Number: 37399
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Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>
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Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37603 )
Change subject: mb/lenovo/x1/devicetree: Rebalance against x220 one
......................................................................
mb/lenovo/x1/devicetree: Rebalance against x220 one
Change-Id: Ib009c33d8393d4a76036941ac77965dc12e4ec3e
Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com>
---
M src/mainboard/lenovo/x220/variants/x1/overridetree.cb
1 file changed, 0 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/37603/1
diff --git a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb
index a08a12f..68a70f0 100644
--- a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb
+++ b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb
@@ -15,31 +15,15 @@
device domain 0 on
subsystemid 0x17aa 0x21e8 inherit
- device pci 00.0 on end # host bridge
- device pci 02.0 on end # vga controller
-
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# Enable SATA ports 0 (HDD bay) & 2 (msata) & 3 (esatap)
register "sata_port_map" = "0x1d"
# X1 does not have ExpressCard slot
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
- device pci 1a.0 on end # USB2 EHCI #2
- device pci 1b.0 on end # High Definition Audio
device pci 1c.0 off end # PCIe Port #1
- device pci 1c.1 on end # PCIe Port #2 (wlan)
device pci 1c.2 off end # PCIe Port #3
device pci 1c.3 off end # PCIe Port #4
- device pci 1c.4 on
- chip drivers/ricoh/rce822 # Ricoh cardreader
- device pci 00.0 on end
- end
- end # PCIe Port #5 (SD)
- device pci 1c.5 off end # PCIe Port #6
- device pci 1c.6 on end # PCIe Port #7
- device pci 1c.7 off end # PCIe Port #8
- device pci 1d.0 on end # USB2 EHCI #1
- device pci 1e.0 off end # PCI bridge
device pci 1f.0 on #LPC bridge
chip ec/lenovo/h8
register "config2" = "0xe0"
@@ -50,14 +34,8 @@
register "event5_enable" = "0x3c"
register "evente_enable" = "0x3d"
-
- # BDC detection is broken on this board:
- register "has_bdc_detection" = "0"
end
end # LPC bridge
- device pci 1f.2 on end # SATA Controller 1
- device pci 1f.3 on end # SMBus
- device pci 1f.6 on end # Thermal
end
end
end
--
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Gerrit-Change-Id: Ib009c33d8393d4a76036941ac77965dc12e4ec3e
Gerrit-Change-Number: 37603
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Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>
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Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37942 )
Change subject: mb/lenovo/x1_1st_gen/devicetree: Use subsystemid inheritance
......................................................................
mb/lenovo/x1_1st_gen/devicetree: Use subsystemid inheritance
PCI ID was changed according to the reports from Linux Hardware Project:
https://github.com/linuxhw/LsPCI/tree/master/Notebook/Lenovo/ThinkPad
Change-Id: I67b81a4c9378c13d557e5d9c5d3797cebeeff5a1
Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com>
---
M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
1 file changed, 14 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/37942/1
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
index 288870f..ded920c 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
+++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb
@@ -34,13 +34,11 @@
register "pci_mmio_size" = "1024"
device domain 0 on
- device pci 00.0 on
- subsystemid 0x17aa 0x21fa
- end # host bridge
+ subsystemid 0x17aa 0x21f9 inherit
+
+ device pci 00.0 on end # host bridge
device pci 01.0 off end # PCIe Bridge for discrete graphics
- device pci 02.0 on
- subsystemid 0x17aa 0x21fa
- end # vga controller
+ device pci 02.0 on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# GPI routing
@@ -74,50 +72,33 @@
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
- device pci 14.0 on
- subsystemid 0x17aa 0x21f9
- end # USB 3.0 Controller
- device pci 16.0 on
- subsystemid 0x17aa 0x21f9
- end # Management Engine Interface 1
+ device pci 14.0 on end # USB 3.0 Controller
+ device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 19.0 off end # Intel Gigabit Ethernet
- device pci 1a.0 on
- subsystemid 0x17aa 0x21f9
- end # USB2 EHCI #2
- device pci 1b.0 on
- subsystemid 0x17aa 0x21f9
- end # High Definition Audio
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on
- subsystemid 0x17aa 0x21f9
chip drivers/ricoh/rce822
register "sdwppol" = "0"
register "disable_mask" = "0x87"
- device pci 00.0 on
- subsystemid 0x17aa 0x21f3
- end
+ device pci 00.0 on end
end
end # PCIe Port #1
- device pci 1c.1 on
- subsystemid 0x17aa 0x21f9
- end # PCIe Port #2
+ device pci 1c.1 on end # PCIe Port #2
device pci 1c.2 off end # PCIe Port #3
device pci 1c.3 off end # PCIe Port #4
device pci 1c.4 off end # PCIe Port #5
device pci 1c.5 off end # PCIe Port #6
device pci 1c.6 off end # PCIe Port #7
device pci 1c.7 off end # PCIe Port #8
- device pci 1d.0 on
- subsystemid 0x17aa 0x21f9
- end # USB2 EHCI #1
+ device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on #LPC bridge
- subsystemid 0x17aa 0x21f9
chip ec/lenovo/pmh7
- device pnp ff.1 on # dummy
- end
+ device pnp ff.1 on end # dummy
register "backlight_enable" = "0x01"
register "dock_event_enable" = "0x01"
end
@@ -162,11 +143,8 @@
register "wwan_gpio_lvl" = "0"
end
end # LPC bridge
- device pci 1f.2 on
- subsystemid 0x17aa 0x21f9
- end # SATA Controller 1
+ device pci 1f.2 on end # SATA Controller 1
device pci 1f.3 on
- subsystemid 0x17aa 0x21f9
# eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c
device i2c 54 on end
@@ -180,9 +158,7 @@
end
end # SMBus
device pci 1f.5 off end # SATA Controller 2
- device pci 1f.6 on
- subsystemid 0x17aa 0x21f9
- end # Thermal
+ device pci 1f.6 on end # Thermal
end
end
end
--
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Gerrit-Change-Id: I67b81a4c9378c13d557e5d9c5d3797cebeeff5a1
Gerrit-Change-Number: 37942
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Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>
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Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38063 )
Change subject: mb/google/nyan/devicetree.cb: Correct some comments
......................................................................
mb/google/nyan/devicetree.cb: Correct some comments
Use a consistent spelling for SoC (System-on-a-Chip), and fix a few
minor typos.
Change-Id: I29eacc9e93b2eb686ce945de0173844ef5eae1b9
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/mainboard/google/nyan/devicetree.cb
M src/mainboard/google/nyan_big/devicetree.cb
M src/mainboard/google/nyan_blaze/devicetree.cb
3 files changed, 15 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/38063/1
diff --git a/src/mainboard/google/nyan/devicetree.cb b/src/mainboard/google/nyan/devicetree.cb
index 5db8192..ae4f5bc 100644
--- a/src/mainboard/google/nyan/devicetree.cb
+++ b/src/mainboard/google/nyan/devicetree.cb
@@ -15,12 +15,12 @@
chip soc/nvidia/tegra124
device cpu_cluster 0 on end
-# N.B. We ae not using the device tree in an effective way.
-# We need to change this in future such that the on-soc
+# N.B. We are not using the device tree in an effective way.
+# We need to change this in future such that the on-SoC
# devices are 'chips', which will allow us to go at them
-# in parallel. This is even easier on the ARM SOCs since there
+# in parallel. This is even easier on the ARM SoCs since there
# are no single-access resources such as the infamous
-# cf8/cfc registers found on PCs.
+# 0xcf8/0xcfc registers found on PCs.
register "display_controller" = "TEGRA_ARM_DISPLAYA"
register "xres" = "1366"
register "yres" = "768"
@@ -39,7 +39,7 @@
register "panel_vdd_gpio" = "0"
register "pwm" = "1"
- # various panel delay time
+ # Various panel delay times
register "vdd_delay_ms" = "200"
register "pwm_to_bl_delay_ms" = "10"
register "vdd_to_hpd_delay_ms" = "200"
diff --git a/src/mainboard/google/nyan_big/devicetree.cb b/src/mainboard/google/nyan_big/devicetree.cb
index 5db8192..ae4f5bc 100644
--- a/src/mainboard/google/nyan_big/devicetree.cb
+++ b/src/mainboard/google/nyan_big/devicetree.cb
@@ -15,12 +15,12 @@
chip soc/nvidia/tegra124
device cpu_cluster 0 on end
-# N.B. We ae not using the device tree in an effective way.
-# We need to change this in future such that the on-soc
+# N.B. We are not using the device tree in an effective way.
+# We need to change this in future such that the on-SoC
# devices are 'chips', which will allow us to go at them
-# in parallel. This is even easier on the ARM SOCs since there
+# in parallel. This is even easier on the ARM SoCs since there
# are no single-access resources such as the infamous
-# cf8/cfc registers found on PCs.
+# 0xcf8/0xcfc registers found on PCs.
register "display_controller" = "TEGRA_ARM_DISPLAYA"
register "xres" = "1366"
register "yres" = "768"
@@ -39,7 +39,7 @@
register "panel_vdd_gpio" = "0"
register "pwm" = "1"
- # various panel delay time
+ # Various panel delay times
register "vdd_delay_ms" = "200"
register "pwm_to_bl_delay_ms" = "10"
register "vdd_to_hpd_delay_ms" = "200"
diff --git a/src/mainboard/google/nyan_blaze/devicetree.cb b/src/mainboard/google/nyan_blaze/devicetree.cb
index 5db8192..ae4f5bc 100644
--- a/src/mainboard/google/nyan_blaze/devicetree.cb
+++ b/src/mainboard/google/nyan_blaze/devicetree.cb
@@ -15,12 +15,12 @@
chip soc/nvidia/tegra124
device cpu_cluster 0 on end
-# N.B. We ae not using the device tree in an effective way.
-# We need to change this in future such that the on-soc
+# N.B. We are not using the device tree in an effective way.
+# We need to change this in future such that the on-SoC
# devices are 'chips', which will allow us to go at them
-# in parallel. This is even easier on the ARM SOCs since there
+# in parallel. This is even easier on the ARM SoCs since there
# are no single-access resources such as the infamous
-# cf8/cfc registers found on PCs.
+# 0xcf8/0xcfc registers found on PCs.
register "display_controller" = "TEGRA_ARM_DISPLAYA"
register "xres" = "1366"
register "yres" = "768"
@@ -39,7 +39,7 @@
register "panel_vdd_gpio" = "0"
register "pwm" = "1"
- # various panel delay time
+ # Various panel delay times
register "vdd_delay_ms" = "200"
register "pwm_to_bl_delay_ms" = "10"
register "vdd_to_hpd_delay_ms" = "200"
--
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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35546 )
Change subject: soc/intel/{common,skl,cnl,icl,apl,tgl}: Make me_hfsts1 structure SoC specific
......................................................................
Patch Set 20:
(2 comments)
This change is ready for review.
https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc…
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc…
PS14, Line 606: heci_reset();
> Why is heci_reset() done here?
heci_reset() is called to reset heci interface to synchronize host and ME for communication.
https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc…
File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/35546/14/src/soc/intel/common/bloc…
PS14, Line 47: SOC_INTEL_APOLLOLAKE
> In fact, I think I see at least one more deviation for TGL. […]
Moved me_hfsts1 defination into SoC specific code.
--
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