coreboot-gerrit January 2020

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 10 Jan '20

10 Jan '20

Hello Patrick Rudolph, Subrata Banik, Balaji Manigandan, Aamir Bohra, Sridhar Siricilla, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, V Sowmya, Nico Huber, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35402 to look at the new patch set (#50). Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... soc/intel/common/block/cse: Add boot partition related APIs The CSE region is logically divided into 3 boot partitions when redundancy is enabled. These boot partitions are represented by BP1, BP2 and BP3. In chrome platforms, CSE can boot from either BP1 or BP2. The CSE image layout appears as below.. ------------- ------------------ -------------------------- |CSE REGION | => | RO | RW | => | BP1 | BP2 + BP3 + DATA | ------------- ------------------ -------------------------- In order to support CSE FW update to RW region, below APIs help coreboot to get info about the boot partitions, and allows coreboot to set CSE to boot from required boot partition (either BP1(RO) or BP2). GET_BOOT_PARTITION_INFO - provides info on available partitions in the CSE region. The API provides info on boot partitions like start/end offsets of a partition within CSE region, and their version and partition status. SET_BOOT_PARTITION_INFO - Sets the next boot partition to boot for CSE. With the HECI API, firmware can notify CSE to boot from BP1 or BP2 on next boot. BUG=b:145809764 Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/Makefile.inc A src/soc/intel/common/block/cse/cse_bp.c M src/soc/intel/common/block/include/intelblocks/cse.h 3 files changed, 489 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35402/50 -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 50 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: timestamps: Fix syncing to CBMEM
by Kyösti Mälkki (Code Review) 10 Jan '20

10 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38301 ) Change subject: timestamps: Fix syncing to CBMEM ...................................................................... timestamps: Fix syncing to CBMEM For timestamps added before CBMEM coming online and call to timestamp_sync_cache_to_cbmem(), ts_table->base_time was subtracted twice. Change-Id: Ia786c12c68c8921c0d09bc58a29fefdc72bf0c6d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/lib/timestamp.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/38301/1 diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index d2206f6..3855f6d 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -128,7 +128,7 @@ tse = &ts_table->entries[ts_table->num_entries++]; tse->entry_id = id; - tse->entry_stamp = ts_time - ts_table->base_time; + tse->entry_stamp = ts_time; if (ts_table->num_entries == ts_table->max_entries) printk(BIOS_ERR, "ERROR: Timestamp table full\n"); @@ -148,6 +148,7 @@ return; } + ts_time -= ts_table->base_time; timestamp_add_table_entry(ts_table, id, ts_time); if (CONFIG(TIMESTAMPS_ON_CONSOLE)) -- To view, visit https://review.coreboot.org/c/coreboot/+/38301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia786c12c68c8921c0d09bc58a29fefdc72bf0c6d Gerrit-Change-Number: 38301 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: timestamps: Fix TIMESTAMPS_ON_CONSOLE behaviour
by Kyösti Mälkki (Code Review) 10 Jan '20

10 Jan '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38300 ) Change subject: timestamps: Fix TIMESTAMPS_ON_CONSOLE behaviour ...................................................................... timestamps: Fix TIMESTAMPS_ON_CONSOLE behaviour As logging is guarded by Kconfig, increase the level from BIOS_SPEW to BIOS_INFO. The original callsite inside timestamp_add_table_entry() was also called when syncing from timestamps from .bss to CBMEM. We should not reprint the values then. Change-Id: I72ca4b6a04d8734c141a04e651fc8c23932b1f23 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/lib/timestamp.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/38300/1 diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 7c7210c..d2206f6 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -130,9 +130,6 @@ tse->entry_id = id; tse->entry_stamp = ts_time - ts_table->base_time; - if (CONFIG(TIMESTAMPS_ON_CONSOLE)) - printk(BIOS_SPEW, "Timestamp - %s: %llu\n", timestamp_name(id), ts_time); - if (ts_table->num_entries == ts_table->max_entries) printk(BIOS_ERR, "ERROR: Timestamp table full\n"); } @@ -152,6 +149,9 @@ } timestamp_add_table_entry(ts_table, id, ts_time); + + if (CONFIG(TIMESTAMPS_ON_CONSOLE)) + printk(BIOS_INFO, "Timestamp - %s: %llu\n", timestamp_name(id), ts_time); } void timestamp_add_now(enum timestamp_id id) -- To view, visit https://review.coreboot.org/c/coreboot/+/38300 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72ca4b6a04d8734c141a04e651fc8c23932b1f23 Gerrit-Change-Number: 38300 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: google/endeavour: add variant based on karma
by Jeff Chase (Code Review) 10 Jan '20

10 Jan '20

Jeff Chase has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36791 ) Change subject: google/endeavour: add variant based on karma ...................................................................... google/endeavour: add variant based on karma BUG=b:144307303 TEST=build Change-Id: I09a10e99877d18361b31b36bed703b02508ccd05 --- M src/mainboard/google/fizz/Kconfig M src/mainboard/google/fizz/Kconfig.name A src/mainboard/google/fizz/variants/endeavour/Makefile.inc A src/mainboard/google/fizz/variants/endeavour/gpio.c A src/mainboard/google/fizz/variants/endeavour/include/variant/acpi/dptf.asl A src/mainboard/google/fizz/variants/endeavour/include/variant/ec.h A src/mainboard/google/fizz/variants/endeavour/include/variant/gpio.h A src/mainboard/google/fizz/variants/endeavour/nhlt.c A src/mainboard/google/fizz/variants/endeavour/overridetree.cb 9 files changed, 389 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/36791/1 diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index 44ac064..689f5ec 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -52,11 +52,13 @@ string default "Fizz" if BOARD_GOOGLE_FIZZ default "Karma" if BOARD_GOOGLE_KARMA + default "Endeavour" if BOARD_GOOGLE_ENDEAVOUR config MAINBOARD_FAMILY string default "Google_Fizz" if BOARD_GOOGLE_FIZZ default "Google_Kalista" if BOARD_GOOGLE_KARMA + default "Google_Endeavour" if BOARD_GOOGLE_ENDEAVOUR config MAX_CPUS int @@ -78,6 +80,7 @@ string default "fizz" if BOARD_GOOGLE_FIZZ default "karma" if BOARD_GOOGLE_KARMA + default "endeavour" if BOARD_GOOGLE_ENDEAVOUR config INCLUDE_NHLT_BLOBS bool "Include blobs for audio." diff --git a/src/mainboard/google/fizz/Kconfig.name b/src/mainboard/google/fizz/Kconfig.name index 608a58d..45cdbd9 100644 --- a/src/mainboard/google/fizz/Kconfig.name +++ b/src/mainboard/google/fizz/Kconfig.name @@ -7,3 +7,7 @@ config BOARD_GOOGLE_KARMA bool "-> Karma" select BOARD_GOOGLE_BASEBOARD_FIZZ + +config BOARD_GOOGLE_ENDEAVOUR + bool "-> Endeavour" + select BOARD_GOOGLE_BASEBOARD_FIZZ diff --git a/src/mainboard/google/fizz/variants/endeavour/Makefile.inc b/src/mainboard/google/fizz/variants/endeavour/Makefile.inc new file mode 100644 index 0000000..0ad298b --- /dev/null +++ b/src/mainboard/google/fizz/variants/endeavour/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += nhlt.c diff --git a/src/mainboard/google/fizz/variants/endeavour/gpio.c b/src/mainboard/google/fizz/variants/endeavour/gpio.c new file mode 100644 index 0000000..c11055c --- /dev/null +++ b/src/mainboard/google/fizz/variants/endeavour/gpio.c @@ -0,0 +1,280 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ +static const struct pad_config gpio_table[] = { +/* RCIN# */ PAD_CFG_NC(GPP_A0), /* TP308 */ +/* ESPI_IO0 */ +/* ESPI_IO1 */ +/* ESPI_IO2 */ +/* ESPI_IO3 */ +/* ESPI_CS# */ +/* SERIRQ */ PAD_CFG_NC(GPP_A6), /* TP331 */ +/* PIRQA# */ PAD_CFG_GPI_INT(GPP_A7, 20K_PU, DEEP, + EDGE), /* SD_CDZ */ +/* CLKRUN# */ PAD_CFG_NC(GPP_A8), /* TP329 */ +/* ESPI_CLK */ +/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), /* TP188 */ +/* PME# */ PAD_CFG_NC(GPP_A11), /* TP149 */ +/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), +/* SUSWARN# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A13, NONE, + DEEP), /* eSPI mode */ +/* ESPI_RESET# */ +/* SUSACK# */ PAD_CFG_NC(GPP_A15), /* TP150 */ +/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), +/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), +/* ISH_GP0 */ PAD_CFG_GPO(GPP_A18, 0, DEEP), /* 7322_OE */ +/* ISH_GP1 */ PAD_CFG_GPI_GPIO_DRIVER(GPP_A19, NONE, DEEP), /* HDPO */ +/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), +/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), +/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), +/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), + +/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), /* TP156 */ +/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), +/* VRALERT# */ PAD_CFG_NC(GPP_B2), /* TP152 */ +/* CPU_GP2 */ PAD_CFG_NC(GPP_B3), +/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, + NF1), /* CLK_PCIE_LAN_REQ# */ +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, + NF1), /* PCIE_CLKREQ_SSD# */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, + NF1), /* PCIE_CLKREQ_NGFF1# */ +/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), /* TP333 */ +/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), /* TP139 */ +/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, + NF1), /* PCIE_CLKREQ_WLAN# */ +/* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* MPHY_EXT_PWR */ +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PM_SLP_S0# */ +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PCI_PLTRST# */ +/* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* SPKR */ +/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CS_L */ +/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CLK */ +/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MISO */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MOSI */ +/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), /* TP111 */ +/* GSPI1_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B20, 20K_PU, + DEEP), /* VR_DISABLE_L */ +/* GSPI1_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_B21, 20K_PU, + DEEP), /* HWA_TRST_N */ +/* GSPI1_MOSI */ PAD_CFG_NC(GPP_B22), /* GSPI1_MOSI */ +/* SML1ALERT# */ PAD_CFG_NC(GPP_B23), /* TP141 */ + +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* PCH_MBCLK0_R */ +/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* PCH_MBDAT0_R */ +/* SMBALERT# */ PAD_CFG_NC(GPP_C2), +/* SML0CLK */ PAD_CFG_NC(GPP_C3), +/* SML0DATA */ PAD_CFG_NC(GPP_C4), +/* SML0ALERT# */ PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), +/* SM1CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C6, 20K_PU, + DEEP), /* EC_IN_RW */ +/* SM1DATA */ PAD_CFG_NC(GPP_C7), /* TP310 */ +/* UART0_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C8, 20K_PU, + DEEP), /* GPIO1 */ +/* UART0_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C9, 20K_PU, + DEEP), /* GPIO2 */ +/* UART0_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C10, 20K_PU, + DEEP), /* GPIO3 */ +/* UART0_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C11, 20K_PU, + DEEP), /* GPIO4 */ +/* UART1_RXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C12, NONE, + DEEP), /* SKU_ID0 */ +/* UART1_TXD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C13, NONE, + DEEP), /* SKU_ID1 */ +/* UART1_RTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C14, NONE, + DEEP), /* SKU_ID2 */ +/* UART1_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C15, NONE, + DEEP), /* SKU_ID3 */ +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), +/* I2C1_SDA */ PAD_CFG_NC(GPP_C18), +/* I2C1_SCL */ PAD_CFG_NC(GPP_C19), +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ +/* UART2_RTS# */ PAD_CFG_NC(GPP_C22), /* TP309 */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, + DEEP), /* SCREW_SPI_WP_STATUS */ + +/* SPI1_CS# */ PAD_CFG_NC(GPP_D0), /* TP259 */ +/* SPI1_CLK */ PAD_CFG_NC(GPP_D1), /* TP260 */ +/* SPI1_MISO */ PAD_CFG_NC(GPP_D2), /* TP261 */ +/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3), /* TP262 */ +/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* TP153 */ +/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5), +/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6), +/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), +/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), +/* ISH_SPI_CS# */ PAD_CFG_GPI_INT(GPP_D9, NONE, + PLTRST, EDGE), /* HP_IRQ_GPIO */ +/* ISH_SPI_CLK */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D10, NONE, + DEEP), /* OEM_ID1 */ +/* ISH_SPI_MISO */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D11, NONE, + DEEP), /* OEM_ID2 */ +/* ISH_SPI_MOSI */ PAD_CFG_GPI_GPIO_DRIVER(GPP_D12, NONE, + DEEP), /* OEM_ID3 */ +/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), +/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), +/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), +/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), +/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), +/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), +/* DMIC_CLK0 */ PAD_CFG_NC(GPP_D19), /* TP121 */ +/* DMIC_DATA0 */ PAD_CFG_NC(GPP_D20), /* TP122 */ +/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21), /* TP257 */ +/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22), /* TP258 */ +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* I2S_MCLK */ + +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, + PLTRST), /* H1_PCH_INT_ODL */ +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, + NF1), /* MB_PCIE_SATA#_DET */ +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP, + NF1), /* DB_PCIE_SATA#_DET */ +/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), +/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */ +/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ +/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */ +/* CPU_GP1 */ PAD_CFG_NC(GPP_E7), +/* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP314 */ +/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB-C */ +/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, + NF1), /* Rear Dual-Stack USB Ports */ +/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, + NF1), /* Front USB Ports */ +/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, + NF1), /* Rear Single USB Port */ +/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, + NF1), /* INT_HDMI_HPD */ +/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, + NF1), /* DDI2_HPD */ +/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15), /* TP325 */ +/* DDPE_HPD3 */ PAD_CFG_NC(GPP_E16), /* TP326 */ +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, + NF1), /* HDMI_DDCCLK_SW */ +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, + NF1), /* HDMI_DDCCLK_DATA */ +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* CRT CLK */ +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* CRT DATA */ +/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), + +/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), /* TP191 */ +/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), /* TP192 */ +/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), /* TP190 */ +/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), /* TP189 */ +/* I2C2_SDA */ PAD_CFG_NF(GPP_F4, NONE, DEEP, + NF1), /* PCH_I2C2_H1_3V3_SDA */ +/* I2C2_SCL */ PAD_CFG_NF(GPP_F5, NONE, DEEP, + NF1), /* PCH_I2C2_H1_3V3_SCL */ +/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), +/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2C4_SDA */ PAD_CFG_NC(GPP_F8), +/* I2C4_SCL */ PAD_CFG_NC(GPP_F9), +/* I2C5_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, + NF1), /* PCH_I2C2_AUDIO_1V8_SDA */ +/* I2C5_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, + NF1), /* PCH_I2C2_AUDIO_1V8_SCL */ +/* EMMC_CMD */ PAD_CFG_NC(GPP_F12), +/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13), +/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14), +/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15), +/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16), +/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17), +/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18), +/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19), +/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20), +/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21), +/* EMMC_CLK */ PAD_CFG_NC(GPP_F22), +/* RSVD */ PAD_CFG_NC(GPP_F23), + +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* SD_CDZ */ +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NC(GPP_G7), /* TP292 */ + +/* BATLOW# */ PAD_CFG_NC(GPD0), /* TP148 */ +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* PCH_ACPRESENT */ +/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE# */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), /* PCH_PWRBTN# */ +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S3# */ +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_S4# */ +/* SLP_A# */ PAD_CFG_NC(GPD6), /* TP147 */ +/* RSVD */ PAD_CFG_NC(GPD7), +/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUS_CLK */ +/* SLP_WLAN# */ PAD_CFG_NC(GPD9), /* TP146 */ +/* SLP_S5# */ PAD_CFG_NC(GPD10), /* TP143 */ +/* LANPHYC */ PAD_CFG_NC(GPD11), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { +/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CS_L */ +/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_CLK */ +/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MISO */ +/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, + NF1), /* PCH_SPI_H1_3V3_MOSI */ +/* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, + PLTRST), /* H1_PCH_INT_ODL */ +/* Ensure UART pins are in native mode for H1. */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ +/* UART2_CTS# */ PAD_CFG_GPI_GPIO_DRIVER(GPP_C23, NONE, + DEEP), /* SCREW_SPI_WP_STATUS */ +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, + NF1), /* MB_PCIE_SATA#_DET */ +/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ +}; + +const struct pad_config * __weak variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config * __weak + variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio * __weak variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/fizz/variants/endeavour/include/variant/acpi/dptf.asl b/src/mainboard/google/fizz/variants/endeavour/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..1e82bc9 --- /dev/null +++ b/src/mainboard/google/fizz/variants/endeavour/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/fizz/variants/endeavour/include/variant/ec.h b/src/mainboard/google/fizz/variants/endeavour/include/variant/ec.h new file mode 100644 index 0000000..1396a2f --- /dev/null +++ b/src/mainboard/google/fizz/variants/endeavour/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_EC_H__ +#define __MAINBOARD_EC_H__ + +#include <baseboard/ec.h> + +#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/google/fizz/variants/endeavour/include/variant/gpio.h b/src/mainboard/google/fizz/variants/endeavour/include/variant/gpio.h new file mode 100644 index 0000000..3f82b9f --- /dev/null +++ b/src/mainboard/google/fizz/variants/endeavour/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <baseboard/gpio.h> + +#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/fizz/variants/endeavour/nhlt.c b/src/mainboard/google/fizz/variants/endeavour/nhlt.c new file mode 100644 index 0000000..07a66e8 --- /dev/null +++ b/src/mainboard/google/fizz/variants/endeavour/nhlt.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <baseboard/variants.h> +#include <console/console.h> +#include <nhlt.h> +#include <soc/nhlt.h> + +void __weak variant_nhlt_init(struct nhlt *nhlt) +{ + + /* RT5663 Headset codec */ + if (nhlt_soc_add_rt5663(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add headset codec.\n"); + +} + +void __weak variant_nhlt_oem_overrides(const char **oem_id, + const char **oem_table_id, + uint32_t *oem_revision) +{ + *oem_id = "GOOGLE"; + *oem_table_id = "ENDEAVOUR"; + *oem_revision = 0; +} diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb new file mode 100644 index 0000000..500e6cf --- /dev/null +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/skylake + device domain 0 on + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/36791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09a10e99877d18361b31b36bed703b02508ccd05 Gerrit-Change-Number: 36791 Gerrit-PatchSet: 1 Gerrit-Owner: Jeff Chase <jnchase(a)google.com> Gerrit-MessageType: newchange

4 18

Change in coreboot[master]: src/device: Update pci_class to Specification Rev 1.11
by HAOUAS Elyes (Code Review) 10 Jan '20

10 Jan '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37656 ) Change subject: src/device: Update pci_class to Specification Rev 1.11 ...................................................................... src/device: Update pci_class to Specification Rev 1.11 Change-Id: If51605719fd96e399aec2ae86caedda44f2648d4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/pci_class.c 1 file changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/37656/1 diff --git a/src/device/pci_class.c b/src/device/pci_class.c index 0aa2f28..dd308cd 100644 --- a/src/device/pci_class.c +++ b/src/device/pci_class.c @@ -43,6 +43,7 @@ { 0x06, "SATA controller" }, { 0x07, "Serial Attached SCSI controller" }, { 0x08, "Non-Volatile memory controller" }, + { 0x09, "Universal Flash Storage controller" }, { 0x80, "Mass storage controller" } }; @@ -54,6 +55,8 @@ { 0x04, "ISDN controller" }, { 0x05, "WorldFip controller" }, { 0x06, "PICMG controller" }, + { 0x07, "InfiniBand Controller" }, + { 0x08, "Host fabric controller" }, { 0x80, "Network controller" } }; @@ -90,6 +93,7 @@ { 0x08, "RACEway bridge" }, { 0x09, "Semi-transparent PCI-to-PCI bridge" }, { 0x0a, "InfiniBand to PCI host bridge" }, + { 0x0b, "Advanced Switching to PCI host bridge" }, { 0x80, "Bridge" } }; @@ -111,6 +115,7 @@ { 0x04, "PCI Hot-plug controller" }, { 0x05, "SD Host controller" }, { 0x06, "IOMMU" }, + { 0x07, "Root Complex Event Collector" }, { 0x80, "System peripheral" } }; @@ -135,7 +140,8 @@ { 0x10, "Alpha" }, { 0x20, "Power PC" }, { 0x30, "MIPS" }, - { 0x40, "Co-processor" } + { 0x40, "Co-processor" }, + { 0x80, "Other processors" } }; static const PCI_SUBCLASS serial_bus[] = { @@ -148,7 +154,9 @@ { 0x06, "InfiniBand" }, { 0x07, "IPMI SMIC interface" }, { 0x08, "SERCOS interface" }, - { 0x09, "CANBUS" } + { 0x09, "CANBUS" }, + { 0x0a, "MIPI I3C SM Host Controller Interface" }, + { 0x80, "Other Serial Bus Controllers" } }; static const PCI_SUBCLASS wireless[] = { @@ -159,6 +167,8 @@ { 0x12, "Broadband" }, { 0x20, "802.1a controller" }, { 0x21, "802.1b controller" }, + { 0x40, "Cellular controller/modem" }, + { 0x41, "Cellular controller/modem plus Ethernet (802.11)" }, { 0x80, "Wireless controller" } }; -- To view, visit https://review.coreboot.org/c/coreboot/+/37656 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If51605719fd96e399aec2ae86caedda44f2648d4 Gerrit-Change-Number: 37656 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: mb/msi/ms7707/devicetree.cb: Align contents
by Angel Pons (Code Review) 10 Jan '20

10 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38080 ) Change subject: mb/msi/ms7707/devicetree.cb: Align contents ...................................................................... mb/msi/ms7707/devicetree.cb: Align contents Change-Id: I2e8100d01d1feb29df83c400f712e58ae9a5e402 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/msi/ms7707/devicetree.cb 1 file changed, 30 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/38080/1 diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index fc23f35..9753c32 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -16,6 +16,11 @@ end device domain 0x0 on subsystemid 0x1462 0x7707 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 off end # Internal graphics + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "docking_supported" = "0" @@ -27,24 +32,25 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" register "gpe0_en" = "0x28000040" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # HD Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge chip superio/fintek/f71808a register "multi_function_register_0" = "0x00" # 0x28 register "multi_function_register_1" = "0xc0" # 0x29 @@ -52,7 +58,7 @@ register "multi_function_register_3" = "0x4f" # 0x2b register "multi_function_register_4" = "0x90" # 0x2c register "hwm_peci_tsi_ctrl" = "0x02" # 0x0a - PECI enabled, 1.23 V - register "hwm_tcc_temp" = "0x64" # 0x0c - TCC temperature = 100 °C + register "hwm_tcc_temp" = "0x64" # 0x0c - TCC temperature = 100 °C register "hwm_fan1_seg1_speed" = "0xff" # 0xaa - Fan 1 segment 1 register "hwm_fan1_seg2_speed" = "0xe2" # 0xab - Fan 1 segment 2 register "hwm_fan1_seg3_speed" = "0xaf" # 0xac - Fan 1 segment 3 @@ -67,7 +73,7 @@ register "hwm_fan2_temp_src" = "0x1e" # 0xbf - Fan 2 source = temperature 2 register "hwm_domain1_en" = "0x01" - register "hwm_fan1_boundary_hysteresis" = "0x43" + register "hwm_fan1_boundary_hysteresis" = "0x43" register "hwm_vt1_boundary_1_temperature" = "0x52" # 82°C register "hwm_vt1_boundary_2_temperature" = "0x46" # 70°C register "hwm_vt1_boundary_3_temperature" = "0x41" # 65°C @@ -104,13 +110,10 @@ end end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal end - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 off end # Internal graphics end end -- To view, visit https://review.coreboot.org/c/coreboot/+/38080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e8100d01d1feb29df83c400f712e58ae9a5e402 Gerrit-Change-Number: 38080 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/intel/wtm2/devicetree.cb: Align comments
by Angel Pons (Code Review) 10 Jan '20

10 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38079 ) Change subject: mb/intel/wtm2/devicetree.cb: Align comments ...................................................................... mb/intel/wtm2/devicetree.cb: Align comments Change-Id: I701aea4656e59a369c2e663438a4b2f9644f0ed6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/wtm2/devicetree.cb 1 file changed, 31 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/38079/1 diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 54b2bff..8d36f04 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -31,36 +31,36 @@ device lapic 0 on end end device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller - device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - device pci 1d.0 off end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + device pci 03.0 on end # mini-hd audio + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1d.0 off end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal end end -- To view, visit https://review.coreboot.org/c/coreboot/+/38079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I701aea4656e59a369c2e663438a4b2f9644f0ed6 Gerrit-Change-Number: 38079 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/emeraldlake2/devicetree.cb: Align contents
by Angel Pons (Code Review) 10 Jan '20

10 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38078 ) Change subject: mb/intel/emeraldlake2/devicetree.cb: Align contents ...................................................................... mb/intel/emeraldlake2/devicetree.cb: Align contents Change-Id: I4ad24a011bd0711dc9a1133dc6188a213cc3926b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/emeraldlake2/devicetree.cb 1 file changed, 26 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/38078/1 diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 0a024b7..6da5614 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -29,15 +29,15 @@ end device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set) - register "gpi1_routing" = "1" + register "gpi1_routing" = "1" register "gpi14_routing" = "2" register "alt_gp_smi_en" = "0x0002" register "gpe0_en" = "0x4000" @@ -52,28 +52,28 @@ register "c2_latency" = "1" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 (WLAN) - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 (Debug) - device pci 1c.3 on end # PCIe Port #4 (LAN) - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 (WLAN) + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 (Debug) + device pci 1c.3 on end # PCIe Port #4 (LAN) + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 on end # Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/38078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ad24a011bd0711dc9a1133dc6188a213cc3926b Gerrit-Change-Number: 38078 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/dg43gt: Make devicetree prettier
by Angel Pons (Code Review) 10 Jan '20

10 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38077 ) Change subject: mb/intel/dg43gt: Make devicetree prettier ...................................................................... mb/intel/dg43gt: Make devicetree prettier Use lowercase for hex constants and align comments and register values. Change-Id: Ib14906113e366a2a6f268fe8b8be32b1794fb344 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/dg43gt/devicetree.cb 1 file changed, 43 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/38077/1 diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb index 38ae29b..c71deab 100644 --- a/src/mainboard/intel/dg43gt/devicetree.cb +++ b/src/mainboard/intel/dg43gt/devicetree.cb @@ -20,15 +20,15 @@ chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end + chip cpu/intel/model_1067x # CPU + device lapic 0xacac off end end end device domain 0 on # PCI domain subsystemid 0x8086 0x0028 inherit - device pci 0.0 on end # Host Bridge - device pci 2.0 on end # Integrated graphics controller - device pci 2.1 on end # Integrated graphics controller 2 + device pci 0.0 on end # Host Bridge + device pci 2.0 on end # Integrated graphics controller + device pci 2.1 on end # Integrated graphics controller 2 device pci 3.0 off end # ME device pci 3.1 off end # ME chip southbridge/intel/i82801jx # Southbridge @@ -40,54 +40,54 @@ register "sata_traffic_monitor" = "0" # Enable PCIe ports 0,2,3 as slots. - register "pcie_slot_implemented" = "0xb" + register "pcie_slot_implemented" = "0xb" register "gen1_dec" = "0x00fc0601" register "gen2_dec" = "0x00fc0291" - device pci 19.0 on end # GBE - device pci 1a.0 on end # USB - device pci 1a.1 on end # USB - device pci 1a.2 on end # USB - device pci 1a.7 on end # USB - device pci 1b.0 on end # Audio - device pci 1c.0 on end # PCIe 1 - device pci 1c.1 off end # PCIe 2 - device pci 1c.2 on end # PCIe 3 - device pci 1c.3 on end # PCIe 4 - device pci 1c.4 off end # PCIe 5 - device pci 1c.5 off end # PCIe 6 - device pci 1d.0 on end # USB - device pci 1d.1 on end # USB - device pci 1d.2 on end # USB - device pci 1d.7 on end # USB - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA bridge + device pci 19.0 on end # GBE + device pci 1a.0 on end # USB + device pci 1a.1 on end # USB + device pci 1a.2 on end # USB + device pci 1a.7 on end # USB + device pci 1b.0 on end # Audio + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 off end # PCIe 2 + device pci 1c.2 on end # PCIe 3 + device pci 1c.3 on end # PCIe 4 + device pci 1c.4 off end # PCIe 5 + device pci 1c.5 off end # PCIe 6 + device pci 1d.0 on end # USB + device pci 1d.1 on end # USB + device pci 1d.2 on end # USB + device pci 1d.7 on end # USB + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # LPC bridge chip superio/winbond/w83627dhg # Super I/O device pnp 2e.0 on # Floppy # GLOBAL - io 0x60 = 0x3f0 + io 0x60 = 0x3f0 irq 0x70 = 6 drq 0x74 = 2 end device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 + io 0x60 = 0x378 irq 0x70 = 5 drq 0x74 = 4 end device pnp 2e.2 on # COM 1 - io 0x60 = 0x3f8 + io 0x60 = 0x3f8 irq 0x70 = 4 end device pnp 2e.3 off end # COM 2 device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 + io 0x60 = 0x60 irq 0x70 = 1 - io 0x62 = 0x64 + io 0x62 = 0x64 irq 0xf0 = 0x85 end device pnp 2e.6 off end # SPI - device pnp 2e.7 on end # GPIO 6 + device pnp 2e.7 on end # GPIO 6 device pnp 2e.8 off end # WDTO# PLED device pnp 2e.9 off end # GPIO 2 device pnp 2e.109 on # GPIO 3 @@ -99,31 +99,29 @@ irq 0xe1 = 0x01 end device pnp 2e.a on # ACPI - irq 0xe4 = 0x30 # power dram during S3 + irq 0xe4 = 0x30 # power dram during S3 end device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 + io 0x60 = 0x290 end device pnp 2e.c off end # PECI, SST end end - device pci 1f.1 on end # PATA/IDE - device pci 1f.2 on end # SATA - device pci 1f.3 on # SMbus - chip drivers/i2c/ck505 # SLG8XP549T - register "mask" = "{ 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff }" - register "regs" = "{ 0x11, 0xd9, 0xff, - 0xfd, 0xff, 0x00, 0x00, - 0x06, 0x10, 0x05, 0x01, - 0x80, 0x0d }" + device pci 1f.1 on end # PATA/IDE + device pci 1f.2 on end # SATA + device pci 1f.3 on # SMBus + chip drivers/i2c/ck505 # SLG8XP549T + register "mask" = "{ 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff }" + register "regs" = "{ 0x11, 0xd9, 0xff, 0xfd, + 0xff, 0x00, 0x00, 0x06, + 0x10, 0x05, 0x01, 0x80, 0x0d }" device i2c 69 on end end end device pci 1f.4 off end - device pci 1f.5 on end # IDE + device pci 1f.5 on end # IDE device pci 1f.6 off end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/38077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib14906113e366a2a6f268fe8b8be32b1794fb344 Gerrit-Change-Number: 38077 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/dcp847ske: Make devicetree prettier
by Angel Pons (Code Review) 10 Jan '20

10 Jan '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38076 ) Change subject: mb/intel/dcp847ske: Make devicetree prettier ...................................................................... mb/intel/dcp847ske: Make devicetree prettier Align contents and fix some redundant comments. Change-Id: I45fb02ac90fe3d280379b08c9931f1064c71633f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/dcp847ske/devicetree.cb 1 file changed, 28 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/38076/1 diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index 6ed7c03..b62c5df 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -28,36 +28,37 @@ end end device domain 0x0 on - device pci 00.0 on end # Host bridge Host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller + device pci 00.0 on end # Host bridge + device pci 01.0 off end # PCIe Bridge for discrete graphics + device pci 02.0 on end # Internal graphics VGA controller + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "c2_latency" = "0x0065" register "sata_port_map" = "0x1" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" - register "gen1_dec" = "0x00fc0a01" # SuperIO @0xa00-0xaff + register "gen1_dec" = "0x00fc0a01" # SuperIO @0xa00-0xaff - device pci 14.0 off end # USB xHCI - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 off end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller - device pci 1c.0 on end # PCIe Port #1 (unused) - device pci 1c.1 on end # PCIe Port #2 (full-length mPCIe/mSATA) - device pci 1c.2 on end # PCIe Port #3 (half-length mPCIe) - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device pci 14.0 off end # USB xHCI + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 off end # USB2 EHCI #2 + device pci 1b.0 on end # HD Audio controller + device pci 1c.0 on end # PCIe Port #1 (unused) + device pci 1c.1 on end # PCIe Port #2 (full-length mPCIe/mSATA) + device pci 1c.2 on end # PCIe Port #3 (half-length mPCIe) + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge chip superio/nuvoton/nct6776 device pnp 4e.0 off end # Floppy device pnp 4e.1 off end # Parallel port @@ -98,10 +99,10 @@ device pnp 4e.17 off end # GPIOA end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/38076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45fb02ac90fe3d280379b08c9931f1064c71633f Gerrit-Change-Number: 38076 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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