coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

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1442 discussions

Change in coreboot[master]: mb/google/octopus: Set sar file name for meep sku
by Chen Wisley (Code Review) 05 Sep '19

05 Sep '19

Hello Wisley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35211 to review the following change. Change subject: mb/google/octopus: Set sar file name for meep sku ...................................................................... mb/google/octopus: Set sar file name for meep sku Set meep sar file name by sku number BUG=b:138261454, b:118782854 BRANCH=octopus TEST=emerge-octopus coreboot, and check wifi_sar-meep.hex Change-Id: I25aa3080392ce277e537c973088dde569246630e Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/octopus/variants/meep/include/variant/sku.h M src/mainboard/google/octopus/variants/meep/variant.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/35211/1 diff --git a/src/mainboard/google/octopus/variants/meep/include/variant/sku.h b/src/mainboard/google/octopus/variants/meep/include/variant/sku.h index 5656d37..41cd490 100644 --- a/src/mainboard/google/octopus/variants/meep/include/variant/sku.h +++ b/src/mainboard/google/octopus/variants/meep/include/variant/sku.h @@ -17,6 +17,9 @@ #define __MAINBOARD_SKU_H__ enum { + SKU_1_MEEP = 1, + SKU_2_MEEP = 2, + SKU_3_MEEP = 3, SKU_33_DORP = 33, /* HDMI */ SKU_34_DORP = 34, /* HDMI+Kblight */ SKU_35_DORP = 35, /* HDMI+TS */ diff --git a/src/mainboard/google/octopus/variants/meep/variant.c b/src/mainboard/google/octopus/variants/meep/variant.c index fc34888..5b924d2 100644 --- a/src/mainboard/google/octopus/variants/meep/variant.c +++ b/src/mainboard/google/octopus/variants/meep/variant.c @@ -25,6 +25,11 @@ uint32_t sku_id = get_board_sku(); switch (sku_id) { + case SKU_1_MEEP: + case SKU_2_MEEP: + case SKU_3_MEEP: + filename = "wifi_sar-meep.hex"; + break; case SKU_49_VORTININJA: case SKU_50_VORTININJA: case SKU_51_VORTININJA: -- To view, visit https://review.coreboot.org/c/coreboot/+/35211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25aa3080392ce277e537c973088dde569246630e Gerrit-Change-Number: 35211 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: inteltool: Add Sky Lake Xeon E DMI3 Host bridge Id
by Maxim Polyakov (Code Review) 05 Sep '19

05 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35125 ) Change subject: inteltool: Add Sky Lake Xeon E DMI3 Host bridge Id ...................................................................... inteltool: Add Sky Lake Xeon E DMI3 Host bridge Id Change-Id: I4b429536fc2db16d770120487e4c383da437593a Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/memory.c M util/inteltool/pcie.c 4 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35125/1 diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 6aff416..7eec062 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -128,6 +128,8 @@ "6th generation (Skylake-S family) Core Processor (Desktop)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2, "6th generation (Skylake-S family) Core Processor (Desktop)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E, + "6th generation (Skylake family) Core Processor Xeon E (Server)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U, "7th generation (Kaby Lake family) Core Processor (Mobile)" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 4e4bfc0..ec6ca4f 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -286,6 +286,7 @@ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M 0x1910 /* Skylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918 /* Skylake (Workstation) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D 0x191f /* Skylake (Desktop) */ +#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E 0x2020 /* Sky Lake E (Server) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U 0x5904 /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y 0x590C /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q 0x5914 /* Kabylake (Mobile) */ diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 222ac8a..e80f1ba 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -221,6 +221,7 @@ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 33644ab..b7c72cb 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -267,6 +267,7 @@ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: @@ -393,6 +394,7 @@ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: @@ -503,6 +505,7 @@ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: -- To view, visit https://review.coreboot.org/c/coreboot/+/35125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b429536fc2db16d770120487e4c383da437593a Gerrit-Change-Number: 35125 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/drallion: modify PCIE setting
by EricR Lai (Code Review) 05 Sep '19

05 Sep '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35243 ) Change subject: mb/google/drallion: modify PCIE setting ...................................................................... mb/google/drallion: modify PCIE setting Based on HW schematic to modify PCIE setting. BUG=b:138082886 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ia744a6f3cba76c507c1c43b0a981cb6d89c1a40f --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 18 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/35243/1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 8870126..561217a 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -189,22 +189,27 @@ }, }" + # PCIe port 9 for Card Reader + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[4]" = "8" + register "PcieClkSrcClkReq[4]" = "4" + # PCIe port 10 for M.2 2230 WLAN register "PcieRpEnable[9]" = "1" - register "PcieClkSrcUsage[2]" = "9" - register "PcieClkSrcClkReq[2]" = "2" - - # PCIe port 11 for card reader - register "PcieRpEnable[10]" = "1" - register "PcieRpLtrEnable[10]" = "1" - register "PcieClkSrcUsage[1]" = "10" + register "PcieClkSrcUsage[1]" = "9" register "PcieClkSrcClkReq[1]" = "1" + # PCIe port 12 for M.2 3042 WWAN + register "PcieRpEnable[11]" = "1" + register "PcieClkSrcUsage[0]" = "11" + register "PcieClkSrcClkReq[0]" = "0" + # PCIe port 13 for M.2 2280 SSD register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" - register "PcieClkSrcUsage[4]" = "12" - register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcUsage[2]" = "12" + register "PcieClkSrcClkReq[2]" = "2" # GPIO PM programming register "gpio_override_pm" = "1" @@ -359,7 +364,7 @@ end end # I2C #4 device pci 19.1 off end # I2C #5 - device pci 19.2 off end # UART #2 + device pci 19.2 on end # UART #2 device pci 1a.0 off end # eMMC device pci 1c.0 off end # PCI Express Port 1 (USB) device pci 1c.1 off end # PCI Express Port 2 (USB) @@ -373,12 +378,12 @@ smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" end # PCI Express Port 9 device pci 1d.1 on end # PCI Express Port 10 - device pci 1d.2 on end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 on end # PCI Express Port 12 device pci 1d.4 on smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" end # PCI Express Port 13 (x4) - device pci 1e.0 on end # UART #0 + device pci 1e.0 off end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 -- To view, visit https://review.coreboot.org/c/coreboot/+/35243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia744a6f3cba76c507c1c43b0a981cb6d89c1a40f Gerrit-Change-Number: 35243 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: inteltool: add Lewisburg C62x GPIOs support
by Maxim Polyakov (Code Review) 05 Sep '19

05 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34942 ) Change subject: inteltool: add Lewisburg C62x GPIOs support ...................................................................... inteltool: add Lewisburg C62x GPIOs support These changes are in accordance with the documentation: [*] page 361, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, Document Number: 336067-007US, May 2019 https://www3.intel.com/content/dam/www/public/us/en/documents/ datasheets/c620-series-chipset-datasheet.pdf Tesed on SUPERMICRO MBD-X11DPL-I-O and Intel S2600WF Wolf Pass Change-Id: I43f8f3701de6ab7f89a78c2f5b939b5edd6d5b9d Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/pcr.c 3 files changed, 493 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/34942/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index 741aed4..c433e81 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1047,6 +1047,13 @@ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C621: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C622: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C624: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C625: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C626: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C627: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C628: case PCI_DEVICE_ID_INTEL_H310: case PCI_DEVICE_ID_INTEL_H370: case PCI_DEVICE_ID_INTEL_Z390: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 0387418..908162c 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -959,6 +959,474 @@ &sunrise_community_gpd, &sunrise_lp_community_fg, }; +static const char *const lewisburg_group_a_names[] = { + "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", + "GPP_A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_A3", "LAD2", "n/a", "ESPI_IO2", + "GPP_A4", "LAD3", "n/a", "ESPI_IO3", + "GPP_A5", "LFRAME#", "n/a", "ESPI_CS0#", + "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", + "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "n/a", "n/a", + "GPP_A12", "BM_BUSY#", "n/a", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "n/a", "n/a", "ESPI_RESET#", + "GPP_A15", "SUS_ACK#", "n/a", "n/a", + "GPP_A16", "CLKOUT_LPC2", "n/a", "n/a", + "GPP_A17", "n/a", "n/a", "n/a", + "GPP_A18", "n/a", "n/a", "n/a", + "GPP_A19", "n/a", "n/a", "n/a", + "GPP_A20", "n/a", "n/a", "n/a", + "GPP_A21", "n/a", "n/a", "n/a", + "GPP_A22", "n/a", "n/a", "n/a", + "GPP_A23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(lewisburg_group_a_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_a_names, +}; + +static const char *const lewisburg_group_b_names[] = { + "GPP_B0", "CORE_VID0", "n/a", "n/a", + "GPP_B1", "CORE_VID1", "n/a", "n/a", + "GPP_B2", "n/a", "n/a", "n/a", + "GPP_B3", "CPU_GP2", "n/a", "n/a", + "GPP_B4", "CPU_GP3", "n/a", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", + "GPP_B11", "n/a", "n/a", "n/a", + "GPP_B12", "GLB_RST_WARN_N#", "n/a", "n/a", + "GPP_B13", "PLTRST#", "n/a", "n/a", + "GPP_B14", "SPKR", "n/a", "n/a", + "GPP_B15", "n/a", "n/a", "n/a", + "GPP_B16", "n/a", "n/a", "n/a", + "GPP_B17", "n/a", "n/a", "n/a", + "GPP_B18", "n/a", "n/a", "n/a", + "GPP_B19", "n/a", "n/a", "n/a", + "GPP_B20", "n/a", "n/a", "n/a", + "GPP_B21", "n/a", "n/a", "n/a", + "GPP_B22", "n/a", "n/a", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", "MEIE_SML1ALRT#", +}; + +static const struct gpio_group lewisburg_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(lewisburg_group_b_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_b_names, +}; + +static const char *const lewisburg_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", "n/a", + "GPP_C1", "SMBDATA", "n/a", "n/a", + "GPP_C2", "SMBALERT#", "n/a", "n/a", + "GPP_C3", "SML0CLK", "SML0CLK_IE#", "n/a", + "GPP_C4", "SML0DATA", "SML0DATA_IE", "n/a", + "GPP_C5", "SML0ALERT#", "SML0ALERT_IE#", "n/a", + "GPP_C6", "SML1CLK", "SML1CLK_IE", "n/a", + "GPP_C7", "SML1DATA", "SML1DATA_IE", "n/a", + "GPP_C8", "n/a", "n/a", "n/a", + "GPP_C9", "n/a", "n/a", "n/a", + "GPP_C10", "n/a", "n/a", "n/a", + "GPP_C11", "n/a", "n/a", "n/a", + "GPP_C12", "n/a", "n/a", "n/a", + "GPP_C13", "n/a", "n/a", "n/a", + "GPP_C14", "n/a", "n/a", "n/a", + "GPP_C15", "n/a", "n/a", "n/a", + "GPP_C16", "n/a", "n/a", "n/a", + "GPP_C17", "n/a", "n/a", "n/a", + "GPP_C18", "n/a", "n/a", "n/a", + "GPP_C19", "n/a", "n/a", "n/a", + "GPP_C20", "n/a", "n/a", "n/a", + "GPP_C21", "n/a", "n/a", "n/a", + "GPP_C22", "n/a", "n/a", "n/a", + "GPP_C23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(lewisburg_group_c_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_c_names, +}; + +static const char *const lewisburg_group_d_names[] = { + "GPP_D0", "n/a", "n/a", "SERIAL_BLINK", + "GPP_D1", "n/a", "n/a", "SERIAL_BLINK", + "GPP_D2", "n/a", "n/a", "SERIAL_BLINK", + "GPP_D3", "n/a", "n/a", "SERIAL_BLINK", + "GPP_D4", "n/a", "n/a", "SERIAL_BLINK", + "GPP_D5", "n/a", "n/a", "n/a", + "GPP_D6", "n/a", "n/a", "n/a", + "GPP_D7", "n/a", "n/a", "n/a", + "GPP_D8", "n/a", "n/a", "n/a", + "GPP_D9", "n/a", "n/a", "SSATA_DEVSLP3", + "GPP_D10", "n/a", "n/a", "SSATA_DEVSLP4", + "GPP_D11", "n/a", "n/a", "SSATA_DEVSLP5", + "GPP_D12", "n/a", "n/a", "SSATA_SDATAOUT1", + "GPP_D13", "n/a", "SML0BCLK", "SML0BCLK_IE", + "GPP_D14", "n/a", "SML0BDATA", "SML0BDATA_IE", + "GPP_D15", "n/a", "n/a", "SSATA_SDATAOUT0", + "GPP_D16", "n/a", "SML0BALERT#", "SML0BALERT_IE#", + "GPP_D17", "n/a", "n/a", "n/a", + "GPP_D18", "n/a", "n/a", "n/a", + "GPP_D19", "n/a", "n/a", "n/a", + "GPP_D20", "n/a", "n/a", "n/a", + "GPP_D21", "n/a", "n/a", "IE_UART_RX", + "GPP_D22", "n/a", "n/a", "IE_UART_TX", + "GPP_D23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(lewisburg_group_d_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_d_names, +}; + +/* The functions in this group are the same as in the pad group E for + the Sunrise chipset */ +static const struct gpio_group lewisburg_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_e_names, +}; + +static const char *const lewisburg_group_f_names[] = { + "GPP_F0", "SATAXPCIE3", "n/a", "SATAGP3", + "GPP_F1", "SATAXPCIE4", "n/a", "SATAGP4", + "GPP_F2", "SATAXPCIE5", "n/a", "SATAGP5", + "GPP_F3", "SATAXPCIE6", "n/a", "SATAGP6", + "GPP_F4", "SATAXPCIE7", "n/a", "SATAGP7", + "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a", + "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a", + "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a", + "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a", + "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a", + "GPP_F10", "SATA_SCLOCK", "n/a", "n/a", + "GPP_F11", "SATA_SLOAD", "n/a", "n/a", + "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a", + "GPP_F13", "SATA_SDATAOUT2", "n/a", "n/a", + "GPP_F14", "n/a", "n/a", "SSATA_LED#", + "GPP_F15", "USB_OC4#", "n/a", "n/a", + "GPP_F16", "USB_OC5#", "n/a", "n/a", + "GPP_F17", "USB_OC6#", "n/a", "n/a", + "GPP_F18", "USB_OC7#", "n/a", "n/a", + "GPP_F19", "LAN_SMBCLK", "n/a", "n/a", + "GPP_F20", "LAN_SMBDATA", "n/a", "n/a", + "GPP_F21", "LAN_SMBALRT#", "n/a", "n/a", + "GPP_F22", "n/a", "n/a", "SSATA_SCLOCK", + "GPP_F23", "n/a", "n/a", "SSATA_SLOAD", +}; + +static const struct gpio_group lewisburg_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(lewisburg_group_f_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_f_names, +}; + +static const char *const lewisburg_group_g_names[] = { + "GPP_G0", "FAN_TACH_0", "FAN_TACH_0_IE", "n/a", + "GPP_G1", "FAN_TACH_1", "FAN_TACH_1_IE", "n/a", + "GPP_G2", "FAN_TACH_2", "FAN_TACH_2_IE", "n/a", + "GPP_G3", "FAN_TACH_3", "FAN_TACH_3_IE", "n/a", + "GPP_G4", "FAN_TACH_4", "FAN_TACH_4_IE", "n/a", + "GPP_G5", "FAN_TACH_5", "FAN_TACH_5_IE", "n/a", + "GPP_G6", "FAN_TACH_6", "FAN_TACH_6_IE", "n/a", + "GPP_G7", "FAN_TACH_7", "FAN_TACH_7_IE", "n/a", + "GPP_G8", "FAN_PWM_0", "FAN_PWM_0_IE", "n/a", + "GPP_G9", "FAN_PWM_1", "FAN_PWM_1_IE", "n/a", + "GPP_G10", "FAN_PWM_2", "FAN_PWM_2_IE", "n/a", + "GPP_G11", "FAN_PWM_3", "FAN_PWM_3_IE", "n/a", + "GPP_G12", "n/a", "n/a", "n/a", + "GPP_G13", "n/a", "n/a", "n/a", + "GPP_G14", "n/a", "n/a", "n/a", + "GPP_G15", "n/a", "n/a", "n/a", + "GPP_G16", "n/a", "n/a", "n/a", + "GPP_G17", "ADR_COMPLETE", "n/a", "n/a", + "GPP_G18", "NMI#", "n/a", "n/a", + "GPP_G19", "SMI#", "n/a", "n/a", + "GPP_G20", "n/a", "SSATA_DEVSLP0", "n/a", + "GPP_G21", "n/a", "SSATA_DEVSLP1", "n/a", + "GPP_G22", "n/a", "SSATA_DEVSLP2", "n/a", + "GPP_G23", "n/a", "SSATAXPCIE0", "SSATAGP0", +}; + +static const struct gpio_group lewisburg_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(lewisburg_group_g_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_g_names, +}; + +static const char *const lewisburg_group_h_names[] = { + "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a", + "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a", + "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a", + "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a", + "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a", + "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a", + "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a", + "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a", + "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a", + "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a", + "GPP_H10", "SML2CLK", "SML2CLK_IE", "n/a", + "GPP_H11", "SML2DATA", "SML2DATA_IE", "n/a", + "GPP_H12", "SML2ALERT#", "SML2ALERT#_IE#", "n/a", + "GPP_H13", "SML3CLK", "SML3CLK_IE", "n/a", + "GPP_H14", "SML3DATA", "SML3DATA_IE", "n/a", + "GPP_H15", "SML3ALERT#", "SML3ALERT#_IE#", "n/a", + "GPP_H16", "SML4CLK", "SML4CLK_IE", "n/a", + "GPP_H17", "SML4DATA", "SML4DATA_IE", "n/a", + "GPP_H18", "SML4ALERT#", "SML4ALERT#_IE#", "n/a", + "GPP_H19", "n/a", "SSATAXPCIE1", "SSATAGP1", + "GPP_H20", "n/a", "SSATAXPCIE2", "SSATAGP2", + "GPP_H21", "n/a", "SSATAXPCIE3", "SSATAGP3", + "GPP_H22", "n/a", "SSATAXPCIE4", "SSATAGP4", + "GPP_H23", "n/a", "SSATAXPCIE5", "SSATAGP5", +}; + +static const struct gpio_group lewisburg_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(lewisburg_group_h_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_h_names, +}; + +static const char *const lewisburg_group_i_names[] = { + "GPP_I0", "n/a", "LAN_TDO", "n/a", + "GPP_I1", "n/a", "LAN_TCK", "n/a", + "GPP_I2", "n/a", "LAN_TMS", "n/a", + "GPP_I3", "n/a", "LAN_TDI", "n/a", + "GPP_I4", "n/a", "RESET_IN#", "n/a", + "GPP_I5", "n/a", "RESET_OUT#", "n/a", + "GPP_I6", "n/a", "RESET_DONE", "n/a", + "GPP_I7", "n/a", "LAN_TRST_IN", "n/a", + "GPP_I8", "n/a", "PCI_DIS", "n/a", + "GPP_I9", "n/a", "LAN_DIS", "n/a", + "GPP_I10", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_i = { + .display = "------- GPIO Group GPP_I -------", + .pad_count = ARRAY_SIZE(lewisburg_group_i_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_i_names, +}; + +static const char *const lewisburg_group_j_names[] = { + "GPP_J0", "LAN_LED_P0_0", "n/a", "n/a", + "GPP_J1", "LAN_LED_P0_1", "n/a", "n/a", + "GPP_J2", "LAN_LED_P1_0", "n/a", "n/a", + "GPP_J3", "LAN_LED_P1_1", "n/a", "n/a", + "GPP_J4", "LAN_LED_P2_0", "n/a", "n/a", + "GPP_J5", "LAN_LED_P2_1", "n/a", "n/a", + "GPP_J6", "LAN_LED_P3_0", "n/a", "n/a", + "GPP_J7", "LAN_LED_P3_1", "n/a", "n/a", + "GPP_J8", "LAN_I2C_SCL_MDC_P0", "n/a", "n/a", + "GPP_J9", "LAN_I2C_SDA_MDIO_P0", "n/a", "n/a", + "GPP_J10", "LAN_I2C_SCL_MDC_P1", "n/a", "n/a", + "GPP_J11", "LAN_I2C_SDA_MDIO_P1", "n/a", "n/a", + "GPP_J12", "LAN_I2C_SCL_MDC_P2", "n/a", "n/a", + "GPP_J13", "LAN_I2C_SDA_MDIO_P2", "n/a", "n/a", + "GPP_J14", "LAN_I2C_SCL_MDC_P3", "n/a", "n/a", + "GPP_J15", "LAN_I2C_SDA_MDIO_P3", "n/a", "n/a", + "GPP_J16", "LAN_SDP_P0_0", "n/a", "n/a", + "GPP_J17", "LAN_SDP_P0_1", "n/a", "n/a", + "GPP_J18", "LAN_SDP_P1_0", "n/a", "n/a", + "GPP_J19", "LAN_SDP_P1_1", "n/a", "n/a", + "GPP_J20", "LAN_SDP_P2_0", "n/a", "n/a", + "GPP_J21", "LAN_SDP_P2_1", "n/a", "n/a", + "GPP_J22", "LAN_SDP_P3_0", "n/a", "n/a", + "GPP_J23", "LAN_SDP_P3_1", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_j = { + .display = "------- GPIO Group GPP_J -------", + .pad_count = ARRAY_SIZE(lewisburg_group_j_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_j_names, +}; + +static const char *const lewisburg_group_k_names[] = { + "GPP_K0", "LAN_NCSI_CLK_IN", "n/a", "n/a", + "GPP_K1", "LAN_NCSI_TXD0", "n/a", "n/a", + "GPP_K2", "LAN_NCSI_TXD1", "n/a", "n/a", + "GPP_K3", "LAN_NCSI_TX_EN", "n/a", "n/a", + "GPP_K4", "LAN_NCSI_CRS_DV", "n/a", "n/a", + "GPP_K5", "LAN_NCSI_RXD0", "n/a", "n/a", + "GPP_K6", "LAN_NCSI_RXD1", "n/a", "n/a", + "GPP_K7", "RESERVED", "n/a", "n/a", + "GPP_K8", "LAN_NCSI_ARB_IN", "n/a", "n/a", + "GPP_K9", "LAN_NCSI_ARB_OUT", "n/a", "n/a", + "GPP_K10", "PE_RST#", "n/a", "n/a", + "GPP_K11", "n/a", "n/a", "n/a", + "GPP_K12", "n/a", "n/a", "n/a", + "GPP_K13", "n/a", "n/a", "n/a", + "GPP_K14", "n/a", "n/a", "n/a", + "GPP_K15", "n/a", "n/a", "n/a", + "GPP_K16", "n/a", "n/a", "n/a", + "GPP_K17", "n/a", "n/a", "n/a", + "GPP_K18", "n/a", "n/a", "n/a", + "GPP_K19", "n/a", "n/a", "n/a", + "GPP_K20", "n/a", "n/a", "n/a", + "GPP_K21", "n/a", "n/a", "n/a", + "GPP_K22", "n/a", "n/a", "n/a", + "GPP_K23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_k = { + .display = "------- GPIO Group GPP_K -------", + .pad_count = ARRAY_SIZE(lewisburg_group_k_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_k_names, +}; + +static const char *const lewisburg_group_l_names[] = { + "GPP_L2", "TESTCH0_D0", "n/a", "n/a", + "GPP_L3", "TESTCH0_D1", "n/a", "n/a", + "GPP_L4", "TESTCH0_D2", "n/a", "n/a", + "GPP_L5", "TESTCH0_D3", "n/a", "n/a", + "GPP_L6", "TESTCH0_D4", "n/a", "n/a", + "GPP_L7", "TESTCH0_D5", "n/a", "n/a", + "GPP_L8", "TESTCH0_D6", "n/a", "n/a", + "GPP_L9", "TESTCH0_D7", "n/a", "n/a", + "GPP_L10", "TESTCH0_CLK", "n/a", "n/a", + "GPP_L11", "TESTCH1_D0", "n/a", "n/a", + "GPP_L12", "TESTCH1_D1", "n/a", "n/a", + "GPP_L13", "TESTCH1_D2", "n/a", "n/a", + "GPP_L14", "TESTCH1_D3", "n/a", "n/a", + "GPP_L15", "TESTCH1_D4", "n/a", "n/a", + "GPP_L16", "TESTCH1_D5", "n/a", "n/a", + "GPP_L17", "TESTCH1_D6", "n/a", "n/a", + "GPP_L18", "TESTCH1_D7", "n/a", "n/a", + "GPP_L19", "TESTCH1_CLK", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_l = { + .display = "------- GPIO Group GPP_L -------", + .pad_count = ARRAY_SIZE(lewisburg_group_l_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_l_names, +}; + +static const char *const lewisburg_group_gpd_names[] = { + "GPD0", "POWER_DEBUG_N", "n/a", "n/a", + "GPD1", "ACPRESENT", "n/a", "n/a", + "GPD2", "GBE_WAKE#", "n/a", "n/a", + "GPD3", "PWRBTN#", "n/a", "n/a", + "GPD4", "SLP_S3#", "n/a", "n/a", + "GPD5", "SLP_S4#", "n/a", "n/a", + "GPD6", "SLP_A#", "n/a", "n/a", + "GPD7", "RESERVED", "n/a", "n/a", + "GPD8", "SUSCLK", "n/a", "n/a", + "GPD9", "RESERVED", "n/a", "n/a", + "GPD10", "SLP_S5#", "n/a", "n/a", + "GPD11", "GBEPHY", "n/a", "n/a", +}; + +static const struct gpio_group lewisburg_group_gpd = { + .display = "-------- GPIO Group GPD --------", + .pad_count = ARRAY_SIZE(lewisburg_group_gpd_names) / 4, + .func_count = 4, + .pad_names = lewisburg_group_gpd_names, +}; + +static const struct gpio_group *const lewisburg_community0_abf_groups[] = { + &lewisburg_group_a, + &lewisburg_group_b, + &lewisburg_group_f, +}; + +static const struct gpio_community lewisburg_community0_abf = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xaf, + .group_count = ARRAY_SIZE(lewisburg_community0_abf_groups), + .groups = lewisburg_community0_abf_groups, +}; + +static const struct gpio_group *const lewisburg_community1_cde_groups[] = { + &lewisburg_group_c, + &lewisburg_group_d, + &lewisburg_group_e, +}; + +static const struct gpio_community lewisburg_community1_cde = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xae, + .group_count = ARRAY_SIZE(lewisburg_community1_cde_groups), + .groups = lewisburg_community1_cde_groups, +}; + +static const struct gpio_group *const lewisburg_community2_gpd_groups[] = { + &lewisburg_group_gpd, +}; + +static const struct gpio_community lewisburg_community2_gpd = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0xad, + .group_count = ARRAY_SIZE(lewisburg_community2_gpd_groups), + .groups = lewisburg_community2_gpd_groups, +}; + +static const struct gpio_group *const lewisburg_community3_i_groups[] = { + &lewisburg_group_i, +}; + +static const struct gpio_community lewisburg_community3_i = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0xac, + .group_count = ARRAY_SIZE(lewisburg_community3_i_groups), + .groups = lewisburg_community3_i_groups, +}; + +static const struct gpio_group *const lewisburg_community4_jk_groups[] = { + &lewisburg_group_j, + &lewisburg_group_k, +}; + +static const struct gpio_community lewisburg_community4_jk = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0xab, + .group_count = ARRAY_SIZE(lewisburg_community4_jk_groups), + .groups = lewisburg_community4_jk_groups, +}; + +static const struct gpio_group *const lewisburg_community5_ghl_groups[] = { + &lewisburg_group_g, + &lewisburg_group_h, + &lewisburg_group_l, +}; + +static const struct gpio_community lewisburg_community5_ghl = { + .name = "------- GPIO Community 5 -------", + .pcr_port_id = 0x11, + .group_count = ARRAY_SIZE(lewisburg_community5_ghl_groups), + .groups = lewisburg_community5_ghl_groups, +}; + +static const struct gpio_community *const lewisburg_communities[] = { + &lewisburg_community0_abf, + &lewisburg_community1_cde, + &lewisburg_community2_gpd, + &lewisburg_community3_i, + &lewisburg_community4_jk, + &lewisburg_community5_ghl, +}; + static const char *const denverton_group_north_all_names[] = { "NORTH_ALL_GBE0_SDP0", "NORTH_ALL_GBE1_SDP0", @@ -1801,6 +2269,17 @@ communities = sunrise_lp_communities; pcr_init(sb); break; + case PCI_DEVICE_ID_INTEL_LEWISBURG_C621: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C622: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C624: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C625: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C626: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C627: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C628: + community_count = ARRAY_SIZE(lewisburg_communities); + communities = lewisburg_communities; + pcr_init(sb); + break; case PCI_DEVICE_ID_INTEL_DNV_LPC: community_count = ARRAY_SIZE(denverton_communities); communities = denverton_communities; diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index c969620..d6d86e8 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -103,6 +103,13 @@ case PCI_DEVICE_ID_INTEL_HM175: case PCI_DEVICE_ID_INTEL_QM175: case PCI_DEVICE_ID_INTEL_CM238: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C621: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C622: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C624: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C625: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C626: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C627: + case PCI_DEVICE_ID_INTEL_LEWISBURG_C628: case PCI_DEVICE_ID_INTEL_DNV_LPC: p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1); break; -- To view, visit https://review.coreboot.org/c/coreboot/+/34942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43f8f3701de6ab7f89a78c2f5b939b5edd6d5b9d Gerrit-Change-Number: 34942 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

5 21

Change in coreboot[master]: mb/google/octopus: Load custom SAR values by SKU ID for Bloog
by Tony Huang (Code Review) 05 Sep '19

05 Sep '19

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35097 ) Change subject: mb/google/octopus: Load custom SAR values by SKU ID for Bloog ...................................................................... mb/google/octopus: Load custom SAR values by SKU ID for Bloog Use sku-id to load the SAR values. SKU ID map 33 to 36 for Bloog 49 to 52 for Blooguard BUG=b:138180187 BRANCH=octopus TEST=build and verify SAR load by sku-id Change-Id: Id0bc2609fd1c4eaeb380f8f1532ab30d34e2aeb3 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/bloog/variant.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/35097/1 diff --git a/src/mainboard/google/octopus/variants/bloog/variant.c b/src/mainboard/google/octopus/variants/bloog/variant.c index 58b3bc4..6484080 100644 --- a/src/mainboard/google/octopus/variants/bloog/variant.c +++ b/src/mainboard/google/octopus/variants/bloog/variant.c @@ -29,6 +29,9 @@ if (sku_id == SKU_UNKNOWN) return NULL; + if (sku_id == 33 || sku_id == 34 || sku_id == 35 || sku_id == 36) + filename = "wifi_sar-bloog.hex"; + if (sku_id == 49 || sku_id == 50 || sku_id == 51 || sku_id == 52) filename = "wifi_sar-blooguard.hex"; -- To view, visit https://review.coreboot.org/c/coreboot/+/35097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0bc2609fd1c4eaeb380f8f1532ab30d34e2aeb3 Gerrit-Change-Number: 35097 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/siemens/mc_apl5: Disable IGD if no EDID data available
by Mario Scheithauer (Code Review) 05 Sep '19

05 Sep '19

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35242 ) Change subject: mb/siemens/mc_apl5: Disable IGD if no EDID data available ...................................................................... mb/siemens/mc_apl5: Disable IGD if no EDID data available To avoid possible panel failures due to incorrect timing settings for PTN3460, the internal graphic device should be disabled. Change-Id: Ie0b9ed99fb78461bb48d6f2ff328643cd8c2cd15 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/35242/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c index f6fed97..2cc7dd4 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c @@ -16,9 +16,32 @@ #include <console/console.h> #include <hwilib.h> #include <device/i2c_simple.h> +#include <device/pci_ops.h> +#include <soc/pci_devs.h> #include <types.h> #include <variant/ptn3460.h> +static void igd_disable(void) +{ + struct device *root_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + uint8_t deven; + uint16_t ggc; + + /* GMCH Graphics Control Register */ + ggc = pci_read_config16(root_dev, 0x50); + /* Set size of Graphics Translation Table Memory (GGMS) [7:6] + * to 0 and select 0 MB for Graphics Memory (GMS) [15:8]. */ + ggc &= ~(0xffc0); + /* Disable IGD VGA (IVD). */ + ggc |= 0x2; + pci_write_config16(root_dev, 0x50, ggc); + /* Device Enable Register */ + deven = pci_read_config8(root_dev, 0x54); + /* Disable IGD device (D2F0EN). */ + deven &= ~(0x10); + pci_write_config8(root_dev, 0x54, deven); +} + /** * This function sets up the DP2LVDS-converter to be used with the appropriate * lcd panel. @@ -42,6 +65,8 @@ /* Get all needed information from hwinfo block. */ if (hwilib_get_field(Edid, edid_data, sizeof(edid_data)) != sizeof(edid_data)) { + /* Disable IGD to avoid panel failures. */ + igd_disable(); printk(BIOS_ERR, "LCD: No EDID data available in %s\n", hwi_block); return 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/35242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0b9ed99fb78461bb48d6f2ff328643cd8c2cd15 Gerrit-Change-Number: 35242 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: soc/intel/cannonlake: memory spd data debug
by EricR Lai (Code Review) 05 Sep '19

05 Sep '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35235 ) Change subject: soc/intel/cannonlake: memory spd data debug ...................................................................... soc/intel/cannonlake: memory spd data debug Add printing SPD data for debug usage. BUG=b:139397313 BRANCH=N/A TEST=Tested the on Hatch and checked cbmem log. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I1e257a8ea6ff9c906267841819d2a4b62a9e0b9e --- M src/soc/intel/cannonlake/cnl_memcfg_init.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/35235/1 diff --git a/src/soc/intel/cannonlake/cnl_memcfg_init.c b/src/soc/intel/cannonlake/cnl_memcfg_init.c index d3e5e83..5d3db76 100644 --- a/src/soc/intel/cannonlake/cnl_memcfg_init.c +++ b/src/soc/intel/cannonlake/cnl_memcfg_init.c @@ -81,6 +81,7 @@ default: die("nonexistent memory slot"); } + print_spd_info((unsigned char *)spd_data_ptr); } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/35235 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1e257a8ea6ff9c906267841819d2a4b62a9e0b9e Gerrit-Change-Number: 35235 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

5 17

Change in coreboot[master]: drivers/intel/fsp2_0: Fix minor whitespace
by Richard Spiegel (Code Review) 05 Sep '19

05 Sep '19

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35265 ) Change subject: drivers/intel/fsp2_0: Fix minor whitespace ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03a62c6a35053b67bfc609a365068cf284bcc1a0 Gerrit-Change-Number: 35265 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Sep 2019 14:45:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/amd/picasso: Create a hybrid romstage to begin in DRAM
by Richard Spiegel (Code Review) 05 Sep '19

05 Sep '19

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33759 ) Change subject: soc/amd/picasso: Create a hybrid romstage to begin in DRAM ...................................................................... Patch Set 13: (3 comments) Is the name hibrid_romstage going to be final? I remember some discussions about using some different name. If so, shouldn't you change file name and the commit message?> https://review.coreboot.org/c/coreboot/+/33759/13/src/soc/amd/picasso/early… File src/soc/amd/picasso/early_stack.S: https://review.coreboot.org/c/coreboot/+/33759/13/src/soc/amd/picasso/early… PS13, Line 31: Extra space. https://review.coreboot.org/c/coreboot/+/33759/13/src/soc/amd/picasso/early… PS13, Line 32: * may be enabled. This could be made more elegant for more Current limit is 96 columns, please use full new size. Same in next comment. https://review.coreboot.org/c/coreboot/+/33759/13/src/soc/amd/picasso/hybri… File src/soc/amd/picasso/hybrid_romstage.c: https://review.coreboot.org/c/coreboot/+/33759/13/src/soc/amd/picasso/hybri… PS13, Line 4: * Copyright (C) 2019 Advanced Micro Devices, Inc. In romstage.h you placed this line after previous copyright, here you placed it before. Examining other code, it looks like placing newer copyrights after older copyrights is the norm. Please change order. -- To view, visit https://review.coreboot.org/c/coreboot/+/33759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976 Gerrit-Change-Number: 33759 Gerrit-PatchSet: 13 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 05 Sep 2019 14:02:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: cpu/intel/car: Skip stack integrity check if FSP_USES_CB_STACK is enable
by Subrata Banik (Code Review) 05 Sep '19

05 Sep '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35165 ) Change subject: cpu/intel/car: Skip stack integrity check if FSP_USES_CB_STACK is enable ...................................................................... cpu/intel/car: Skip stack integrity check if FSP_USES_CB_STACK is enable With FSP2.1 FSP_USES_CB_STACK likely to be enable. Impacted platforms are CML and ICL. Don't need to run code logic to check the integrity of stack if FSP and coreboot both likely to make use of common stack. Notified by CONFIG_FSP_USES_CB_STACK, its expected to print "Smashed stack detected in romstage!" msg multiple time in that case. This patch fixes CML/ICL platform printing "Smashed stack detected in romstage!" multiple times. This prints might be misleading. TEST=Build and boot CML-Hatch With this CL No "Smashed stack detected in romstage!" msg in serial log. Without this CL "Smashed stack detected in romstage!" 64 times in serial log after FSP-M returns into coreboot. Change-Id: I943eff1225b976dc4440a6ca6d02ceea378319f8 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/cpu/intel/car/romstage.c 1 file changed, 13 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/35165/1 diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 547b121..78b2b8d 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -54,10 +54,19 @@ mainboard_romstage_entry(); /* Check the stack. */ - for (i = 0; i < num_guards; i++) { - if (stack_base[i] == stack_guard) - continue; - printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n"); + /* + * Don't need to run below logic to check the integrity of stack + * if FSP and coreboot both likely to make use of common stack. + * Notified by CONFIG_FSP_USES_CB_STACK, its expected to print + * "Smashed stack detected in romstage!" msg many times in that case. + */ + if (!CONFIG(FSP_USES_CB_STACK)) { + for (i = 0; i < num_guards; i++) { + if (stack_base[i] == stack_guard) + continue; + printk(BIOS_DEBUG, "Smashed stack detected in" + "romstage!\n"); + } } if (CONFIG(SMM_TSEG)) -- To view, visit https://review.coreboot.org/c/coreboot/+/35165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I943eff1225b976dc4440a6ca6d02ceea378319f8 Gerrit-Change-Number: 35165 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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