coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: [WIP For squash with I9c084ff]: Implement RESET_VECTOR_IN_RAM
by Kyösti Mälkki (Code Review) 05 Sep '19

05 Sep '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35264 ) Change subject: [WIP For squash with I9c084ff]: Implement RESET_VECTOR_IN_RAM ...................................................................... Patch Set 1: Marshall; squashed as requested, using my old Change-Id. I will push update after rebasing and/or merging some related work. -- To view, visit https://review.coreboot.org/c/coreboot/+/35264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If272118dd80e559f8fe45e24e10fa28c5b7bd1f9 Gerrit-Change-Number: 35264 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Sep 2019 19:18:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1344
by Furquan Shaikh (Code Review) 05 Sep '19

05 Sep '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35245 ) Change subject: src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1344 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5784eb8c0f7c6e56950dad5c8254e00aa73cef4 Gerrit-Change-Number: 35245 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Sep 2019 17:03:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1344
by Tim Wawrzynczak (Code Review) 05 Sep '19

05 Sep '19

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35245 ) Change subject: src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1344 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5784eb8c0f7c6e56950dad5c8254e00aa73cef4 Gerrit-Change-Number: 35245 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Sep 2019 16:57:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1344
by Tim Wawrzynczak (Code Review) 05 Sep '19

05 Sep '19

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35245 ) Change subject: src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1344 ...................................................................... Patch Set 3: Verified new FSP with 300 cold reboot cycles of Helios -- To view, visit https://review.coreboot.org/c/coreboot/+/35245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5784eb8c0f7c6e56950dad5c8254e00aa73cef4 Gerrit-Change-Number: 35245 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 05 Sep 2019 16:57:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Create a hybrid romstage to begin in DRAM
by Kyösti Mälkki (Code Review) 05 Sep '19

05 Sep '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33759 ) Change subject: soc/amd/picasso: Create a hybrid romstage to begin in DRAM ...................................................................... Patch Set 13: (6 comments) https://review.coreboot.org/c/coreboot/+/33759/13//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/33759/13//COMMIT_MSG@22 PS13, Line 22: Remove all postcar support. At first appearance >50% of code line changes is about MTRRs and not about the entry to romstage like it should be. Could you please make first a separate commit that removes anything postcar related, while not adding any set_var_mtrr() here. Delay all that set_var_mtrr() (those are not merge-critical, just speed optimisations?) to be done much later in the patchtrain. I would really like to see mock emulation/qemu-picasso that build-tests these soc/amd/picasso changes until CRB board has landed on master. https://review.coreboot.org/c/coreboot/+/33759/13/src/soc/amd/picasso/Kconf… File src/soc/amd/picasso/Kconfig: https://review.coreboot.org/c/coreboot/+/33759/13/src/soc/amd/picasso/Kconf… PS13, Line 71: config POSTCAR_STAGE Hmm.. maybe POSTCAR_STAGE should have 'depends on !RESET_VECTOR_IN_RAM̈́' but we can deal with that separately. https://review.coreboot.org/c/coreboot/+/33759/13/src/soc/amd/picasso/Makef… File src/soc/amd/picasso/Makefile.inc: https://review.coreboot.org/c/coreboot/+/33759/13/src/soc/amd/picasso/Makef… PS13, Line 42: romstage-y += hybrid_romstage.c I see little point in renaming the file, we just start asking questions why you link in romstage-y class... It also makes gerrit introduce it as separate file now, it could not detect romstage.c being renamed to hybrid_romstage.c, too many changes. https://review.coreboot.org/c/coreboot/+/33759/13/src/soc/amd/picasso/hybri… File src/soc/amd/picasso/hybrid_romstage.c: https://review.coreboot.org/c/coreboot/+/33759/13/src/soc/amd/picasso/hybri… PS13, Line 4: * Copyright (C) 2019 Advanced Micro Devices, Inc. > In romstage.h you placed this line after previous copyright, here you placed it before. […] I believe there is decision to no longer add these, but refer to AUTHORS and git blame. https://review.coreboot.org/c/coreboot/+/33759/13/src/soc/amd/picasso/hybri… PS13, Line 66: CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); Sorry.. all the caps makes my eyes bleed, and I did not check how all these macros are defined now. This is what I meant about delaying any set_var_mtrr() to be done later. https://review.coreboot.org/c/coreboot/+/33759/13/src/soc/amd/picasso/hybri… PS13, Line 125: romstage_soc_early_init(); PCI MMCONF setup needs to happen earlier. -- To view, visit https://review.coreboot.org/c/coreboot/+/33759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976 Gerrit-Change-Number: 33759 Gerrit-PatchSet: 13 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 05 Sep 2019 15:51:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: [TESTONLY] enable microcode update
by Rizwan Qureshi (Code Review) 05 Sep '19

05 Sep '19

Rizwan Qureshi has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/27370 ) Change subject: soc/intel/skylake: [TESTONLY] enable microcode update ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/27370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic492a8600c7400055ce4b950408f33c6463e0f92 Gerrit-Change-Number: 27370 Gerrit-PatchSet: 43 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/poppy:[TESTONLY] Add FMAP regions required for microcode up...
by Rizwan Qureshi (Code Review) 05 Sep '19

05 Sep '19

Rizwan Qureshi has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/27366 ) Change subject: mb/google/poppy:[TESTONLY] Add FMAP regions required for microcode update ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/27366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If275b3014bfb679bae980e4238e6a428f06c6e32 Gerrit-Change-Number: 27366 Gerrit-PatchSet: 42 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Rizwan Qureshi (Code Review) 05 Sep '19

05 Sep '19

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 43: (3 comments) https://review.coreboot.org/c/coreboot/+/27369/30/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/ucode_update.c: https://review.coreboot.org/c/coreboot/+/27369/30/src/soc/intel/common/base… PS30, Line 108: printk(BIOS_ERR, "Staging area could not be initialized!\n"); > be found ? Done https://review.coreboot.org/c/coreboot/+/27369/30/src/soc/intel/common/base… PS30, Line 118: int check_and_update_ucode(void) > it does more than that. Done https://review.coreboot.org/c/coreboot/+/27369/30/src/soc/intel/common/base… PS30, Line 163: if (staging_rev != current_ucode || current_ucode != slot_rev || > If you want to handle a corrupted RW ucode this way, you'll need […] Made the MCU checking simpler using memcmp. -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 43 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Thu, 05 Sep 2019 15:30:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Create a hybrid romstage to begin in DRAM
by Marshall Dawson (Code Review) 05 Sep '19

05 Sep '19

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33759 ) Change subject: soc/amd/picasso: Create a hybrid romstage to begin in DRAM ...................................................................... Patch Set 13: (5 comments) > Is the name hibrid_romstage going to be final? I remember some discussions about using some different name. If so, shouldn't you change file name and the commit message?> I'm flexible on the name but I've heard no better suggestions. Although it uses nearly all the romstage build infrastructure, I think it's important to try to draw a distinction between this implementation and a traditional romstage. If you're thinking of what I'd coined "pspstage", if it comes about, that's a completely separate entity and 0% romstage, with the makefile calling a new create_class_compiler, pspstage += <name> for all source, new environment definitions, etc. A pspstage approach is my current long-term preference. https://review.coreboot.org/c/coreboot/+/33759/13/src/soc/amd/picasso/early… File src/soc/amd/picasso/early_stack.S: https://review.coreboot.org/c/coreboot/+/33759/13/src/soc/amd/picasso/early… PS13, Line 31: > Extra space. It's not extra. Using a double space after a period, and between sentences, was always the norm for typewritten text. https://review.coreboot.org/c/coreboot/+/33759/13/src/soc/amd/picasso/early… PS13, Line 32: * may be enabled. This could be made more elegant for more > Current limit is 96 columns, please use full new size. Same in next comment. Although the limit is 96, it's still not preferred. 96 should only be used when 80 affects readability. https://review.coreboot.org/c/coreboot/+/33759/13/src/soc/amd/picasso/hybri… File src/soc/amd/picasso/hybrid_romstage.c: https://review.coreboot.org/c/coreboot/+/33759/13/src/soc/amd/picasso/hybri… PS13, Line 4: * Copyright (C) 2019 Advanced Micro Devices, Inc. > In romstage.h you placed this line after previous copyright, here you placed it before. […] This line wasn't added. The two copyrights used to be AMD 2015-2016 and Intel 2015. I can't look at this file and determine what Intel might wish to claim ownership of, but OTOH I'm not wishing to remove their name from the list. However, I was comfortable making the claim that 100% of the AMD work is relevant to 2019. So the change was to replace "2015-2016" with "2019". I prefer keeping AMD's name first. If you really want a change, I'll put the copyright back to 2015 again. https://review.coreboot.org/c/coreboot/+/33759/9/src/soc/amd/picasso/reset_… File src/soc/amd/picasso/reset_vector.S: https://review.coreboot.org/c/coreboot/+/33759/9/src/soc/amd/picasso/reset_… PS9, Line 111: .byte 0x00, 0x9b, 0xaf, 0x00 > So far I haven't needed it bigger than 64K but I specifically gave myself the option. […] Done https://review.coreboot.org/c/coreboot/+/33759/9/src/soc/amd/picasso/romsta… File src/soc/amd/picasso/romstage.c: https://review.coreboot.org/c/coreboot/+/33759/9/src/soc/amd/picasso/romsta… PS9, Line 49: || (CONFIG_DCACHE_RAM_BASE >= CONFIG_ROMSTAGE_ADDR \ > Comparisons should place the constant on the right side of the test OBE -- To view, visit https://review.coreboot.org/c/coreboot/+/33759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976 Gerrit-Change-Number: 33759 Gerrit-PatchSet: 13 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 05 Sep 2019 15:19:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Comment-In-Reply-To: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP For squash with I9c084ff]: Implement RESET_VECTOR_IN_RAM
by Marshall Dawson (Code Review) 05 Sep '19

05 Sep '19

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35264 ) Change subject: [WIP For squash with I9c084ff]: Implement RESET_VECTOR_IN_RAM ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/35264/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35264/1//COMMIT_MSG@7 PS1, Line 7: RESET_VECTOR_IN_RAM For what it's worth, this name was originally chosen when I was trying to keep all code outside of soc//picasso as untouched as possible. With the current patch stack integrating it more into the [arch|cpu]/x86, and the fact that it's addressing and AMD PSP design, I like the name less now. -- To view, visit https://review.coreboot.org/c/coreboot/+/35264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If272118dd80e559f8fe45e24e10fa28c5b7bd1f9 Gerrit-Change-Number: 35264 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Sep 2019 15:16:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit September 2019