coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: superio/smsc/lpc47b397: fix regression in ops override
by Felix Held (Code Review) 06 Sep '19

06 Sep '19

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35282 ) Change subject: superio/smsc/lpc47b397: fix regression in ops override ...................................................................... superio/smsc/lpc47b397: fix regression in ops override b0d868e8fe3f9a13f9be109fc3b73dfa949bec15 introduced a regression Change-Id: I231888f2702027a80f25eb418c4e4703e55db920 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/superio/smsc/lpc47b397/superio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/35282/1 diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index ad8153f..4b9e345 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -139,7 +139,7 @@ { NULL, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, 0x07f8, }, { NULL, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x07ff, 0x07ff, }, - { NULL_hwm, LPC47B397_HWM, PNP_IO0, 0x07f0, }, + { &ops_hwm, LPC47B397_HWM, PNP_IO0, 0x07f0, }, { NULL, LPC47B397_RT, PNP_IO0, 0x0780, }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/35282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I231888f2702027a80f25eb418c4e4703e55db920 Gerrit-Change-Number: 35282 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/superio/aspeed/ast2400: Add Autogen ACPI Code
by Christian Walter (Code Review) 06 Sep '19

06 Sep '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33253 Change subject: src/superio/aspeed/ast2400: Add Autogen ACPI Code ...................................................................... src/superio/aspeed/ast2400: Add Autogen ACPI Code Once the Autogen ACPI Code is merged, we can use this to autogenerate the ACPI Code for the AST2400. This is WIP. Has been tested w/ AST2400. Change-Id: I2ef49bb6f733994b249ae46f0460234380b552b8 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/superio/aspeed/ast2400/Makefile.inc M src/superio/aspeed/ast2400/superio.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/33253/1 diff --git a/src/superio/aspeed/ast2400/Makefile.inc b/src/superio/aspeed/ast2400/Makefile.inc index a6f8b20..9a1a8f5 100644 --- a/src/superio/aspeed/ast2400/Makefile.inc +++ b/src/superio/aspeed/ast2400/Makefile.inc @@ -16,3 +16,4 @@ ## ramstage-$(CONFIG_SUPERIO_ASPEED_AST2400) += superio.c +ramstage-$(CONFIG_SUPERIO_ASPEED_AST2400) += ../../common/ssdt.c diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index dcb14fa..c4d0c72 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -22,6 +22,7 @@ #include <console/console.h> #include <string.h> #include <pc80/keyboard.h> +#include <superio/common/ssdt.h> #include "ast2400.h" static void ast2400_init(struct device *dev) @@ -36,6 +37,13 @@ } } +#if CONFIG(HAVE_ACPI_TABLES) +static const char *aspeed_ast2400_name(const struct device *dev) +{ + return "SIO0"; +} +#endif + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, @@ -43,6 +51,10 @@ .enable = pnp_enable, .init = ast2400_init, .ops_pnp_mode = &pnp_conf_mode_a5a5_aa, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = superio_common_fill_ssdt_generator, + .acpi_name = aspeed_ast2400_name, +#endif }; static struct pnp_info pnp_dev_info[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ef49bb6f733994b249ae46f0460234380b552b8 Gerrit-Change-Number: 33253 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/tpm/tss/tcg-2.0/tss_marshaling.c: Increase supported algorithms
by Frans Hendriks (Code Review) 06 Sep '19

06 Sep '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35276 ) Change subject: security/tpm/tss/tcg-2.0/tss_marshaling.c: Increase supported algorithms ...................................................................... security/tpm/tss/tcg-2.0/tss_marshaling.c: Increase supported algorithms Function marshal_TPMT_HA() supports SHA-256 only. Add support for more algorithms BUG=N/A TEST=Build binary and verified logging on Facebook FBG-1701 Change-Id: Ife8d44484c7a7cb717035e5ae0870bbee205661b Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/security/tpm/tss/tcg-2.0/tss_marshaling.c 1 file changed, 23 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/35276/1 diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index ec3cd8b..1bf211a 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -83,9 +83,30 @@ int rc = 0; rc |= marshal_TPMI_ALG_HASH(ob, tpmtha->hashAlg); - rc |= obuf_write(ob, tpmtha->digest.sha256, + switch (tpmtha->hashAlg) { + case TPM_ALG_SHA1: + rc |= obuf_write(ob, tpmtha->digest.sha1, tlcl_get_hash_size_from_algo(tpmtha->hashAlg)); - + break; + case TPM_ALG_SHA256: + rc |= obuf_write(ob, tpmtha->digest.sha256, + tlcl_get_hash_size_from_algo(tpmtha->hashAlg)); + break; + case TPM_ALG_SM3_256: + rc |= obuf_write(ob, tpmtha->digest.sm3_256, + tlcl_get_hash_size_from_algo(tpmtha->hashAlg)); + break; + case TPM_ALG_SHA384: + rc |= obuf_write(ob, tpmtha->digest.sha384, + tlcl_get_hash_size_from_algo(tpmtha->hashAlg)); + break; + case TPM_ALG_SHA512: + rc |= obuf_write(ob, tpmtha->digest.sha512, + tlcl_get_hash_size_from_algo(tpmtha->hashAlg)); + break; + default: + rc = -1; + } return rc; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife8d44484c7a7cb717035e5ae0870bbee205661b Gerrit-Change-Number: 35276 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: Fix USB enumeration issue
by Ran Bi (Code Review) 06 Sep '19

06 Sep '19

Ran Bi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35150 ) Change subject: soc/mediatek: Fix USB enumeration issue ...................................................................... soc/mediatek: Fix USB enumeration issue Some USB3.0 devices are failed to enumerate after USB reset, and xhci port status register show device is disconnected. After measure USB signal, we can find usb disconnect threshold is lower and disconnect event is triggered unexpectedly. USB designer suggest to change discth to 15. BUG=b:122047652 TEST=emerge-kukui coreboot chromeos-bootimage Change-Id: I0e8556035b49d693a42cbe1099a6882a1c0ed0d1 Signed-off-by: Changqi Hu <changqi.hu(a)mediatek.com> --- M src/soc/mediatek/common/include/soc/usb_common.h M src/soc/mediatek/common/usb.c 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/35150/1 diff --git a/src/soc/mediatek/common/include/soc/usb_common.h b/src/soc/mediatek/common/include/soc/usb_common.h old mode 100644 new mode 100755 index 8a36c6a..22704e7 --- a/src/soc/mediatek/common/include/soc/usb_common.h +++ b/src/soc/mediatek/common/include/soc/usb_common.h @@ -70,6 +70,8 @@ #define PA6_RG_U2_ISO_EN (0x1 << 31) #define PA6_RG_U2_BC11_SW_EN (0x1 << 23) #define PA6_RG_U2_OTG_VBUSCMP_EN (0x1 << 20) +#define PA6_RG_U2_DISCTH (0xf << 4) +#define PA6_RG_U2_DISCTH_VAL(x) ((0xf & (x)) << 4) #define PA6_RG_U2_SQTH (0xf << 0) #define PA6_RG_U2_SQTH_VAL(x) ((0xf & (x)) << 0) diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c old mode 100644 new mode 100755 index dcb9307..f5263fb --- a/src/soc/mediatek/common/usb.c +++ b/src/soc/mediatek/common/usb.c @@ -76,6 +76,10 @@ /* Set USB 2.0 slew rate value */ clrsetbits_le32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4)); + + /*Set USB 2.0 disconnect threshold*/ + clrsetbits_le32(&phy->u2phy.usbphyacr6, + PA6_RG_U2_DISCTH, PA6_RG_U2_DISCTH_VAL(15)); } static void u3phy_power_on(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/35150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e8556035b49d693a42cbe1099a6882a1c0ed0d1 Gerrit-Change-Number: 35150 Gerrit-PatchSet: 1 Gerrit-Owner: Ran Bi <ran.bi(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86: Make X86 stages select ARCH_X86
by HAOUAS Elyes (Code Review) 06 Sep '19

06 Sep '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31316 ) Change subject: arch/x86: Make X86 stages select ARCH_X86 ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic77b696f493d7648f317f0ba0a27fdee5212961e Gerrit-Change-Number: 31316 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 06 Sep 2019 08:15:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/variants/helios: Update SPD sources
by Frank Chu (Code Review) 06 Sep '19

06 Sep '19

Frank Chu has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/33953 ) Change subject: mb/google/hatch/variants/helios: Update SPD sources ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/33953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cb4e46c7c4da72d8fb029f1b8e8c3b06d1ab156 Gerrit-Change-Number: 33953 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Marx Wang <marx.wang(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/hatch/variants/helios: Update SPD sources
by Frank Chu (Code Review) 06 Sep '19

06 Sep '19

Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33953 ) Change subject: mb/google/hatch/variants/helios: Update SPD sources ...................................................................... Patch Set 3: Because coreboot 34251/34252 CL have fix this issue, so abandon this CL -- To view, visit https://review.coreboot.org/c/coreboot/+/33953 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9cb4e46c7c4da72d8fb029f1b8e8c3b06d1ab156 Gerrit-Change-Number: 33953 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Marx Wang <marx.wang(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 06 Sep 2019 07:45:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2
by Furquan Shaikh (Code Review) 06 Sep '19

06 Sep '19

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/34743 ) Change subject: mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2 ...................................................................... mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2 Applying first tuned DPTF parameters and TDP PL1/PL2 values for helios. BUG=b:138752455 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: Ic7a96c33ce710c32b57e2ad8066830ff83398c57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34743 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/helios/overridetree.cb 2 files changed, 104 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl index f1f0943..30dcf13 100644 --- a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl @@ -13,4 +13,104 @@ * GNU General Public License for more details. */ -#include <baseboard/acpi/dptf.asl> +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 105 +#define DPTF_CPU_ACTIVE_AC0 55 +#define DPTF_CPU_ACTIVE_AC1 50 +#define DPTF_CPU_ACTIVE_AC2 45 +#define DPTF_CPU_ACTIVE_AC3 30 +#define DPTF_CPU_ACTIVE_AC4 20 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_PASSIVE 0 +#define DPTF_TSR0_CRITICAL 0 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_PASSIVE 45 +#define DPTF_TSR1_CRITICAL 0 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 100, 80, 60, 55, 40, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 90, 69, 56, 46, 36, 30, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 30, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 60, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on Ambient (TSR0) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR1) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 8000, /* PowerLimitMinimum */ + 13000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 64000, /* PowerLimitMinimum */ + 64000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index 71e4856..b3da8c9 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -1,4 +1,7 @@ chip soc/intel/cannonlake + register "tdp_pl1_override" = "13" + register "tdp_pl2_override" = "64" + register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, -- To view, visit https://review.coreboot.org/c/coreboot/+/34743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a96c33ce710c32b57e2ad8066830ff83398c57 Gerrit-Change-Number: 34743 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2
by Furquan Shaikh (Code Review) 06 Sep '19

06 Sep '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34743 ) Change subject: mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2 ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/c/coreboot/+/34743/2/src/mainboard/google/hatch… File src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl: https://review.coreboot.org/c/coreboot/+/34743/2/src/mainboard/google/hatch… PS2, Line 26: #define DPTF_TSR0_PASSIVE 0 : #define DPTF_TSR0_CRITICAL 0 > Are they correct? Done https://review.coreboot.org/c/coreboot/+/34743/2/src/mainboard/google/hatch… PS2, Line 31: #define DPTF_TSR1_PASSIVE 45 : #define DPTF_TSR1_CRITICAL 0 > Are they correct? Done https://review.coreboot.org/c/coreboot/+/34743/1/src/mainboard/google/hatch… File src/mainboard/google/hatch/variants/helios/overridetree.cb: https://review.coreboot.org/c/coreboot/+/34743/1/src/mainboard/google/hatch… PS1, Line 2: 8 > ok,PL1 change to 13w, thanks Done -- To view, visit https://review.coreboot.org/c/coreboot/+/34743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a96c33ce710c32b57e2ad8066830ff83398c57 Gerrit-Change-Number: 34743 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 06 Sep 2019 07:00:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Comment-In-Reply-To: Philip Chen <philipchen(a)google.com> Comment-In-Reply-To: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2
by Furquan Shaikh (Code Review) 06 Sep '19

06 Sep '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34743 ) Change subject: mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2 ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/c/coreboot/+/34743/1/src/mainboard/google/hatch… File src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl: https://review.coreboot.org/c/coreboot/+/34743/1/src/mainboard/google/hatch… PS1, Line 36: 8000 > Is this correct? Done https://review.coreboot.org/c/coreboot/+/34743/1/src/mainboard/google/hatch… PS1, Line 37: 13000 > In RFQ, it is evaluated that the system must conform to the "Skin pass" state, and the CPU wattage n […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/34743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a96c33ce710c32b57e2ad8066830ff83398c57 Gerrit-Change-Number: 34743 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 06 Sep 2019 07:00:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Comment-In-Reply-To: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit September 2019