coreboot-gerrit September 2019

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Change in ...coreboot[master]: soc/amd/picasso: Update calculation for TSC frequency
by Marshall Dawson (Code Review) 09 Sep '19

09 Sep '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33765 Change subject: soc/amd/picasso: Update calculation for TSC frequency ...................................................................... soc/amd/picasso: Update calculation for TSC frequency Remove the Family 15h step of finding the number of boost states and get the frequency directly out of the Pstate0 register. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I909743483309279eb8c3bf68852d6082381f0dff --- M src/soc/amd/picasso/tsc_freq.c 1 file changed, 3 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/33765/1 diff --git a/src/soc/amd/picasso/tsc_freq.c b/src/soc/amd/picasso/tsc_freq.c index 29121b9..2277b33 100644 --- a/src/soc/amd/picasso/tsc_freq.c +++ b/src/soc/amd/picasso/tsc_freq.c @@ -19,26 +19,16 @@ #include <cpu/amd/msr.h> #include <cpu/x86/tsc.h> #include <console/console.h> -#include <soc/pci_devs.h> -#include <device/pci_ops.h> unsigned long tsc_freq_mhz(void) { msr_t msr; uint8_t cpufid; uint8_t cpudid; - uint8_t boost_states; + uint8_t high_state; - /* - * See the Family 15h Models 70h-7Fh BKDG (PID 55072) definition for - * MSR0000_0010. The TSC increments at the P0 frequency. According - * to the "Software P-state Numbering" section, P0 is the highest - * non-boosted state. freq = 100MHz * (CpuFid + 10h) / (2^(CpuDid)). - */ - boost_states = (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL) - >> 2) & 0x7; - - msr = rdmsr(PSTATE_0_MSR + boost_states); + high_state = rdmsr(PS_LIM_REG).lo & 0x7; + msr = rdmsr(PSTATE_0_MSR + high_state); if (!(msr.hi & 0x80000000)) die("Unknown error: cannot determine P-state 0\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/33765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I909743483309279eb8c3bf68852d6082381f0dff Gerrit-Change-Number: 33765 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/lpc: Add decode disable function
by Marshall Dawson (Code Review) 09 Sep '19

09 Sep '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35270 ) Change subject: soc/amd/common/lpc: Add decode disable function ...................................................................... soc/amd/common/lpc: Add decode disable function It is already trivial to set D14F3x44 to 0, but add a function to wipe both that and the settings in D14F3x48, along with x48's associated addresses. Change-Id: Ibec25562b2a1568681aea7caf86f00094c436a50 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/lpc.h M src/soc/amd/common/block/lpc/lpc_util.c 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/35270/1 diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 6b6745d..0f4f616 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -68,6 +68,7 @@ #define DECODE_IO_PORT_ENABLE2 BIT(18) #define DECODE_IO_PORT_ENABLE1 BIT(17) #define DECODE_IO_PORT_ENABLE0 BIT(16) +#define LPC_SYNC_TIMEOUT_COUNT_MASK 0xff #define LPC_SYNC_TIMEOUT_COUNT_ENABLE BIT(7) #define LPC_DECODE_RTC_IO_ENABLE BIT(6) #define DECODE_MEM_PORT_ENABLE0 BIT(5) @@ -134,6 +135,7 @@ #define PREFETCH_EN_SPI_FROM_HOST BIT(0) #define T_START_ENH BIT(3) +void lpc_disable_decodes(void); /* LPC is typically enabled very early, but this function is last opportunity */ void soc_late_lpc_bridge_enable(void); void lpc_enable_port80(void); diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index 008d14c..485eeda 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -170,6 +170,21 @@ pci_write_config32(_LPCB_DEV, LPC_IO_PORT_DECODE_ENABLE, decodes); } +void lpc_disable_decodes(void) +{ + uint32_t reg; + + lpc_enable_decode(0); + reg = pci_read_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE); + reg &= LPC_SYNC_TIMEOUT_COUNT_MASK + LPC_SYNC_TIMEOUT_COUNT_ENABLE; + pci_write_config32(_LPCB_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, reg); + + /* D14F3x48 enables ranges configured in additional registers */ + pci_write_config32(_LPCB_DEV, LPC_MEM_PORT1, 0); + pci_write_config32(_LPCB_DEV, LPC_MEM_PORT0, 0); + pci_write_config32(_LPCB_DEV, LPC_WIDEIO2_GENERIC_PORT, 0); +} + uintptr_t lpc_spibase(void) { u32 base, enables; -- To view, visit https://review.coreboot.org/c/coreboot/+/35270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibec25562b2a1568681aea7caf86f00094c436a50 Gerrit-Change-Number: 35270 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common: Add missing stdint.h to lpc.h
by Marshall Dawson (Code Review) 09 Sep '19

09 Sep '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35269 ) Change subject: soc/amd/common: Add missing stdint.h to lpc.h ...................................................................... soc/amd/common: Add missing stdint.h to lpc.h Change-Id: If33765b6dc4236c4b38860bfc4f2cef9b226b81d Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/lpc.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/35269/1 diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index ab913b2..6b6745d 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -17,6 +17,7 @@ #define __AMDBLOCKS_LPC_H__ #include <types.h> +#include <stdint.h> /* PCI registers for D14F3 */ #define LPC_PCI_CONTROL 0x40 -- To view, visit https://review.coreboot.org/c/coreboot/+/35269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If33765b6dc4236c4b38860bfc4f2cef9b226b81d Gerrit-Change-Number: 35269 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] arch/x86: Refactor CAR_GLOBAL quirk for FSP1.0
by Kyösti Mälkki (Code Review) 09 Sep '19

09 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35140 ) Change subject: [WIP] arch/x86: Refactor CAR_GLOBAL quirk for FSP1.0 ...................................................................... [WIP] arch/x86: Refactor CAR_GLOBAL quirk for FSP1.0 These platforms return to romstage from FSP only after already having torn CAR down. A copy of the entire CAR region is available and discoverable via HOB. Previously, CBMEM console detected on-the-fly that CAR migration had happened and relocated cbmem_console_p accoringlin with car_sync_var(). However, if the CAR_GLOBAL pointing to another object inside CAR is a relative offset instead, we have a more generic solution that can be used with timestamps code as well. Change-Id: Ica877b47e68d56189e9d998b5630019d4328a419 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/arm/include/arch/early_variables.h M src/arch/arm64/include/arch/early_variables.h M src/arch/mips/include/arch/early_variables.h M src/arch/ppc64/include/arch/early_variables.h M src/arch/riscv/include/arch/early_variables.h M src/arch/x86/include/arch/early_variables.h M src/cpu/x86/car.c M src/lib/cbmem_console.c 8 files changed, 49 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/35140/1 diff --git a/src/arch/arm/include/arch/early_variables.h b/src/arch/arm/include/arch/early_variables.h index 9f06923..e559e9b 100644 --- a/src/arch/arm/include/arch/early_variables.h +++ b/src/arch/arm/include/arch/early_variables.h @@ -18,7 +18,9 @@ static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) -#define car_sync_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) +#define car_get_reloc_ptr car_get_var +#define car_set_reloc_ptr car_set_var + #endif diff --git a/src/arch/arm64/include/arch/early_variables.h b/src/arch/arm64/include/arch/early_variables.h index 9f06923..e559e9b 100644 --- a/src/arch/arm64/include/arch/early_variables.h +++ b/src/arch/arm64/include/arch/early_variables.h @@ -18,7 +18,9 @@ static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) -#define car_sync_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) +#define car_get_reloc_ptr car_get_var +#define car_set_reloc_ptr car_set_var + #endif diff --git a/src/arch/mips/include/arch/early_variables.h b/src/arch/mips/include/arch/early_variables.h index 8fc9c19..32f4b6b 100644 --- a/src/arch/mips/include/arch/early_variables.h +++ b/src/arch/mips/include/arch/early_variables.h @@ -19,7 +19,9 @@ static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) -#define car_sync_var(var) (var) #define car_set_var(var, val) { (var) = (val); } +#define car_get_reloc_ptr car_get_var +#define car_set_reloc_ptr car_set_var + #endif /* __MIPS_ARCH_EARLY_VARIABLES_H */ diff --git a/src/arch/ppc64/include/arch/early_variables.h b/src/arch/ppc64/include/arch/early_variables.h index 22c3750..539e7f9 100644 --- a/src/arch/ppc64/include/arch/early_variables.h +++ b/src/arch/ppc64/include/arch/early_variables.h @@ -19,8 +19,9 @@ #define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) -#define car_sync_var(var) (var) - #define car_set_var(var, val) do { (var) = (val); } while (0) +#define car_get_reloc_ptr car_get_var +#define car_set_reloc_ptr car_set_var + #endif diff --git a/src/arch/riscv/include/arch/early_variables.h b/src/arch/riscv/include/arch/early_variables.h index acc5ac3..69f5f56 100644 --- a/src/arch/riscv/include/arch/early_variables.h +++ b/src/arch/riscv/include/arch/early_variables.h @@ -21,7 +21,9 @@ #define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) -#define car_sync_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) +#define car_get_reloc_ptr car_get_var +#define car_set_reloc_ptr car_set_var + #endif diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index 3910a82..4b29fa3 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -33,19 +33,23 @@ /* Get the correct pointer for the CAR global variable. */ void *car_get_var_ptr(void *var); -/* Get and update a CAR_GLOBAL pointing elsewhere in car.global_data*/ -void *car_sync_var_ptr(void *var); - /* Return 1 when currently running with globals in Cache-as-RAM, 0 otherwise. */ int car_active(void); /* Get and set a primitive type global variable. */ #define car_get_var(var) \ (*(typeof(var) *)car_get_var_ptr(&(var))) -#define car_sync_var(var) \ - (*(typeof(var) *)car_sync_var_ptr(&(var))) #define car_set_var(var, val) car_get_var(var) = (val) +/* Get and set a CAR_GLOBAL pointing elsewhere inside CAR. */ +#if CONFIG(PLATFORM_USES_FSP1_0) +void *car_get_reloc_ptr(void *var); +void car_set_reloc_ptr(void *var, void *tgt); +#else +#define car_get_reloc_ptr car_get_var +#define car_set_reloc_ptr car_set_var +#endif + static inline size_t car_data_size(void) { size_t car_size = _car_relocatable_data_size; @@ -66,9 +70,11 @@ #define CAR_GLOBAL #define car_get_var(var) (var) -#define car_sync_var(var) (var) #define car_set_var(var, val) (var) = (val) +#define car_get_reloc_ptr car_get_var +#define car_set_reloc_ptr car_set_var + static inline void *car_get_var_ptr(void *var) { return var; diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index 6fc6168..285e29f 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -77,42 +77,31 @@ return &migrated_base[offset]; } +#if CONFIG(PLATFORM_USES_FSP1_0) /* - * Update a CAR_GLOBAL variable var, originally pointing to CAR region, - * with the address in migrated CAR region in DRAM. + * Pointers to CAR_GLOBALs use relative addressing, this way discovery + * of objects that are not CAR_GLOBALs themselves, remain discoverable + * after CAR migration has happened. */ -void *car_sync_var_ptr(void *var) +void car_set_reloc_ptr(void *var, void *dst) { - void **mig_var = car_get_var_ptr(var); - void *_car_start = _car_relocatable_data_start; - void *_car_end = _car_relocatable_data_end; - - /* Not moved or migrated yet. */ - if (mig_var == var) - return mig_var; - - /* - * Migrate the cbmem console pointer for FSP 1.0 platforms. Otherwise, - * keep console buffer in CAR until cbmemc_reinit() moves it. - */ - if (*mig_var == _preram_cbmem_console) { - if (CONFIG(PLATFORM_USES_FSP1_0)) - *mig_var += (char *)mig_var - (char *)var; - return mig_var; - } - - /* It's already pointing outside car.global_data. */ - if (*mig_var < _car_start || *mig_var > _car_end) - return mig_var; - - /* Move the pointer by the same amount the variable storing it was - * moved by. - */ - *mig_var += (char *)mig_var - (char *)var; - - return mig_var; + uintptr_t *mig_var = car_get_var_ptr(var); + if (dst) + *mig_var = (uintptr_t)dst - (uintptr_t)mig_var; + else + *mig_var = 0; } +void *car_get_reloc_ptr(void *var) +{ + uintptr_t *mig_var = car_get_var_ptr(var); + if (*mig_var) + return (void *)((uintptr_t)mig_var + *mig_var); + else + return NULL; +} +#endif + int car_active(void) { return !car_migrated; diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index df2d1ff..1987a99 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -73,12 +73,12 @@ static struct cbmem_console *current_console(void) { - return car_sync_var(cbmem_console_p); + return car_get_reloc_ptr(cbmem_console_p); } static void current_console_set(struct cbmem_console *new_console_p) { - car_set_var(cbmem_console_p, new_console_p); + car_set_reloc_ptr(cbmem_console_p, new_console_p); } static int buffer_valid(struct cbmem_console *cbm_cons_p, u32 total_space) -- To view, visit https://review.coreboot.org/c/coreboot/+/35140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica877b47e68d56189e9d998b5630019d4328a419 Gerrit-Change-Number: 35140 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Add cpuid for older device
by Richard Spiegel (Code Review) 09 Sep '19

09 Sep '19

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35273 ) Change subject: soc/amd/picasso: Add cpuid for older device ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/35273/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35273/2//COMMIT_MSG@8 PS2, Line 8: Could you explain why? -- To view, visit https://review.coreboot.org/c/coreboot/+/35273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0961369b9cc9cfe1b0c09ebc50e6966ccd2e919 Gerrit-Change-Number: 35273 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Mon, 09 Sep 2019 22:11:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/amd/picasso: Update PCI bridge devices
by Richard Spiegel (Code Review) 09 Sep '19

09 Sep '19

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34425 ) Change subject: src/amd/picasso: Update PCI bridge devices ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/c/coreboot/+/34425/12/src/soc/amd/picasso/inclu… File src/soc/amd/picasso/include/soc/pci_devs.h: https://review.coreboot.org/c/coreboot/+/34425/12/src/soc/amd/picasso/inclu… PS12, Line 157: 0x1 redefining device 1, already used with GPP bridges. -- To view, visit https://review.coreboot.org/c/coreboot/+/34425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fa9d52ce113eacdc5c9ba31ab46b6428a7d6ca9 Gerrit-Change-Number: 34425 Gerrit-PatchSet: 12 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 09 Sep 2019 22:09:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: intel/fsp_broadwell_de: Add early timestamps
by Kyösti Mälkki (Code Review) 09 Sep '19

09 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35279 ) Change subject: intel/fsp_broadwell_de: Add early timestamps ...................................................................... intel/fsp_broadwell_de: Add early timestamps Modify intel/fsp_broadwell_de such that timestamp_init() is before raminit (and CAR teardown of FSP1.0), adding two new early timestamps while doing so. Other FSP1.0 platforms fsp_baytrail and fsp_rangeley already do it this way. Change-Id: I3b73e4a61622f789a49973a43b21e8028bcb8ca8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/fsp_broadwell_de/romstage/romstage.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/35279/1 diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 1f71c98..5c9682a 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -104,6 +104,10 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header) { post_code(0x40); + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + if (!CONFIG(INTEGRATED_UART)) { /* Enable decoding of I/O locations for Super I/O devices */ pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), @@ -123,6 +127,8 @@ init_rtc(); setup_gpio_io_address(); + timestamp_add_now(TS_BEFORE_INITRAM); + /* * Call early init to initialize memory and chipset. This function returns * to the romstage_main_continue function with a pointer to the HOB @@ -144,7 +150,6 @@ void *cbmem_hob_ptr; post_code(0x4a); - timestamp_init(get_initial_timestamp()); timestamp_add_now(TS_AFTER_INITRAM); printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", __func__, (u32) status, (u32) hob_list_ptr); -- To view, visit https://review.coreboot.org/c/coreboot/+/35279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b73e4a61622f789a49973a43b21e8028bcb8ca8 Gerrit-Change-Number: 35279 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/fsp_broadwell_de: Enable CONSOLE_CBMEM by default
by Kyösti Mälkki (Code Review) 09 Sep '19

09 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35284 ) Change subject: intel/fsp_broadwell_de: Enable CONSOLE_CBMEM by default ...................................................................... intel/fsp_broadwell_de: Enable CONSOLE_CBMEM by default In the very early days of FSP 1.0 this did not work so we kept it disabled. Change-Id: I8a88be6df335598d4c6007a8b7ff307b293e1f97 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/fsp_broadwell_de/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/35284/1 diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index c388525..9c91d7c 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -77,10 +77,6 @@ help Use Broadwell-DE Integrated UART ports @3F8h and 2F8h. -config CONSOLE_CBMEM - bool "Send console output to a CBMEM buffer" - default n - config SERIRQ_CONTINUOUS_MODE bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/35284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a88be6df335598d4c6007a8b7ff307b293e1f97 Gerrit-Change-Number: 35284 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Allow coreboot to handle SPI lockdown
by Subrata Banik (Code Review) 09 Sep '19

09 Sep '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35299 ) Change subject: soc/intel/cannonlake: Allow coreboot to handle SPI lockdown ...................................................................... soc/intel/cannonlake: Allow coreboot to handle SPI lockdown This patch disables FSP-S SPI lockdown UPDs and lets coreboot perform SPI lockdown (i.e.flash register DLOCK, FLOCKDN, and WRSDIS before end of post) in ramstage. BUG=b:138200201 TEST=FSP debug build suggests those UPDs are disable now. Change-Id: Id7a6b9859e058b9f1ec1bd45d2c388c02b8ac18c Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 2 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/35299/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 5cdddc6..9495f84 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -419,30 +419,24 @@ params->PchLockDownBiosLock = 0; params->PchLockDownRtcMemoryLock = 0; /* - * TODO: Disable SpiFlashCfgLockDown config after FSP provides - * dedicated UPD - * * Skip SPI Flash Lockdown from inside FSP. * Making this config "0" means FSP won't set the FLOCKDN bit * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). * So, it becomes coreboot's responsibility to set this bit * before end of POST for security concerns. */ - // params->SpiFlashCfgLockDown = 0; + params->SpiFlashCfgLockDown = 0; } else { tconfig->PchLockDownGlobalSmi = 1; tconfig->PchLockDownBiosInterface = 1; params->PchLockDownBiosLock = 1; params->PchLockDownRtcMemoryLock = 1; /* - * TODO: Enable SpiFlashCfgLockDown config after FSP provides - * dedicated UPD - * * Enable SPI Flash Lockdown from inside FSP. * Making this config "1" means FSP will set the FLOCKDN bit * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). */ - // params->SpiFlashCfgLockDown = 1; + params->SpiFlashCfgLockDown = 1; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/35299 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7a6b9859e058b9f1ec1bd45d2c388c02b8ac18c Gerrit-Change-Number: 35299 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/spd_bin: Extend DDR4 spd information
by EricR Lai (Code Review) 09 Sep '19

09 Sep '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35206 ) Change subject: lib/spd_bin: Extend DDR4 spd information ...................................................................... lib/spd_bin: Extend DDR4 spd information From DDR4 SPD spec: Byte 4 (0x004): SDRAM Density and Banks Bits [7, 6]: 00 = 0 (no bank groups) 01 = 1 (2 bank groups) 10 = 2 (4 bank groups) 11 = reserved Bit [5, 4] : 00 = 2 (4 banks) 01 = 3 (8 banks) All others reserved Separate DDR3 and DDR4 banks. And extened rows, cols and ranks. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 --- M src/lib/spd_bin.c 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/35206/1 diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 1598ff1..e2a811a 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -36,10 +36,11 @@ void print_spd_info(uint8_t spd[]) { const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + const int ddr4_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 }; const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 128 }; - const int spd_rows[8] = {12, 13, 14, 15, 16, 17, -1, -1 }; - const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; - const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; + const int spd_rows[8] = { 12, 13, 14, 15, 16, 17, 18, -1 }; + const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; + const int spd_ranks[8] = { 1, 2, 3, 4, 5, 6, 7, 8 }; const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; char spd_name[DDR4_SPD_PART_LEN+1] = { 0 }; @@ -74,6 +75,7 @@ memcpy(spd_name, &spd[DDR4_SPD_PART_OFF], DDR4_SPD_PART_LEN); spd_name[DDR4_SPD_PART_LEN] = 0; ranks = (spd[SPD_ORGANIZATION] >> 3) & 7; + banks = ddr4_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; devw = spd_devw[spd[12] & 7]; busw = spd_busw[spd[13] & 7]; break; -- To view, visit https://review.coreboot.org/c/coreboot/+/35206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 Gerrit-Change-Number: 35206 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2019