coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/skylake: Add option to disabble HyperTreading
by Patrick Rudolph (Code Review) 10 Sep '19

10 Sep '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35208 ) Change subject: soc/intel/skylake: Add option to disabble HyperTreading ...................................................................... soc/intel/skylake: Add option to disabble HyperTreading Needs test on KBL. Change-Id: I3ebab68ff868c78105bb4b35abffb92f3ccf1705 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/romstage/romstage_fsp20.c 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/35208/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 9cb8d45..8bf66f3 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -78,6 +78,11 @@ select TSC_SYNC_MFENCE select UDELAY_TSC +config FSP_HYPERTHREADING + bool "Enable HyperThreading" + depends on SOC_INTEL_KABYLAKE + default y + config CPU_INTEL_NUM_FIT_ENTRIES int default 10 diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index ecd1428..f3f8063 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -251,6 +251,7 @@ m_cfg->PchHpetDeviceNumber = 15; m_cfg->PchHpetFunctionNumber = 0; } + m_cfg->HyperThreading = CONFIG(FSP_HYPERTHREADING); } static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/35208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ebab68ff868c78105bb4b35abffb92f3ccf1705 Gerrit-Change-Number: 35208 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Add GPIO table and initialize for Mono Lake Tested on Mono Lake
by Jingle Hsu (Code Review) 10 Sep '19

10 Sep '19

Jingle Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35309 ) Change subject: Add GPIO table and initialize for Mono Lake Tested on Mono Lake ...................................................................... Add GPIO table and initialize for Mono Lake Tested on Mono Lake Change-Id: Ibb1332d953c73925371ae22710dcd09ea0e70d73 Signed-off-by: jinglehsuwiwynn <jinglehsuwiwynn(a)github.com> --- A src/mainboard/ocp/monolake/gpio.h M src/mainboard/ocp/monolake/romstage.c 2 files changed, 106 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/35309/1 diff --git a/src/mainboard/ocp/monolake/gpio.h b/src/mainboard/ocp/monolake/gpio.h new file mode 100644 index 0000000..f7bf8ce --- /dev/null +++ b/src/mainboard/ocp/monolake/gpio.h @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Wiwynn Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpio.h> + +#ifndef MONOLAKE_GPIO_H +#define MONOLAKE_GPIO_H + +static const struct gpio_config gpio_tables[] = { + {0, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {1, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {2, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {3, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {4, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {5, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {6, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {7, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {8, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {9, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {10, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {11, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {12, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {13, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {14, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {15, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {16, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + {17, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {18, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {19, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {20, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {21, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {22, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {23, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {24, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {25, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {26, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {27, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {28, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {29, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + {30, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {31, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {32, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {33, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + {34, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {35, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {36, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {37, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {38, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {39, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {40, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {41, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {42, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {43, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {44, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {45, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {46, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + {47, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {48, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {49, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {50, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {51, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {52, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {53, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {54, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {55, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {56, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {57, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {58, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {59, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {60, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {61, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {62, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {63, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {64, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {65, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {66, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {67, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {68, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {69, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {70, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {71, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {72, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {73, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {74, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {75, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {0xff, GPIO_LIST_END, 0, 0, 0, 0}, +}; + +#endif \ No newline at end of file diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c index 8625868..63bf548 100644 --- a/src/mainboard/ocp/monolake/romstage.c +++ b/src/mainboard/ocp/monolake/romstage.c @@ -24,6 +24,8 @@ #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/lpc.h> +#include <soc/gpio.h> +#include "gpio.h" /* Define the strings for UPD variables that could be customized */ #define FSP_VAR_HYPERTHREADING "HyperThreading" @@ -59,6 +61,9 @@ // IPMI through BIC pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC, 0x0c0ca1); + + // Initialize GPIOs + init_gpios(gpio_tables); } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/35309 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb1332d953c73925371ae22710dcd09ea0e70d73 Gerrit-Change-Number: 35309 Gerrit-PatchSet: 1 Gerrit-Owner: Jingle Hsu Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Rizwan Qureshi (Code Review) 10 Sep '19

10 Sep '19

Hello Patrick Rudolph, Aaron Durbin, dhaval v sharma, Subrata Banik, Patrick Rudolph, Paul Menzel, Duncan Laurie, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Varshit B Pandya, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/27369 to look at the new patch set (#44). Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... soc/intel/basecode: Add support for updating ucode loaded via FIT Intel’s FIT (Firmware Interface Table) based MCU (microcode/pcode patch) loading mechanism patches the microcode before CPU reset. In the current Chromebooks field updatable FW has to be first verified by vboot. Since the MCU is loaded before reset vboot cannot verify the same and hence we end up restricting FIT based MCU update only from RO. This patch implements a scheme which will allow chromebooks to update MCU in the field. Create 2 bootblocks (use INTEL_ADD_TOP_SWAP_BOOTBLOCK) each containing their own FIT table. First bootblock FIT has pointers to MCUs (in microcode_blob.bin) which resides in RO section. This is will be used in the recovery scenario. Second bootblock (Normal mode) is identical to the first one except the FIT. Insert an additional pointer to a MCU that will reside in a staging area. Use the CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG config to insert the address of the staging area into FIT. Top swap control bit in RTC BUC register (0x3414) is used to switch between the two bootblocks. Reserve a region in the FMAP which is equal to or greater than the MCU size specified in the BWG for a particular SoC (e.g., for Skylake/Kaby Lake it is 192K). This is a RW region just like the RW_MRC_CACHE. MCU from RW-A/RW-B will be copied to this region during boot. Protect this staging area with a FPR. Basic update flow: In non-recovery mode, Once a slot has been selected and loaded, check if the current slot MCU and RW staging MCU are same. If so, update the staging area with the MCU found in the current slot and reset the system. Also, make sure that the top is enabled in normal/developer mode and disabled in recovery mode. In order to enable the update feature: * The mainboard chromeos.fmd should include a new region for staging MCU e.g, RW_UCODE_STAGED. * Select config TOP_SWAP_BASED_VBOOT_UCODE_UPDATE. * Implement a call to check_and_update_ucode() and handle the failure appropriately. Add documentation to describing the MCU update procedure. TEST=Create an FW image for soraka and flash, create a chromeos-firmwareupdate shellball with a newer MCU and perform an update. Make sue that the currently loaded microcode version matches the one in firmwareupdate. Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: dhaval v sharma <dhaval.v.sharma(a)intel.com> Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> --- M Documentation/soc/intel/index.md A Documentation/soc/intel/ucode_update/flash_layout.svg A Documentation/soc/intel/ucode_update/microcode_update_model.md A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/ucode_update.c A src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h 7 files changed, 644 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27369/44 -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 44 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: selfboot: remove bounce buffers
by Yu-Ping Wu (Code Review) 10 Sep '19

10 Sep '19

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28647 ) Change subject: selfboot: remove bounce buffers ...................................................................... Patch Set 28: (1 comment) https://review.coreboot.org/c/coreboot/+/28647/28/src/lib/selfboot.c File src/lib/selfboot.c: https://review.coreboot.org/c/coreboot/+/28647/28/src/lib/selfboot.c@152 PS28, Line 152: for (first_segment = seg = cbfssegs;; ++seg) { I happened to see this CL. Do we still need this for loop after this change? -- To view, visit https://review.coreboot.org/c/coreboot/+/28647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I602feb32f35e8af1d0dc4ea9f25464872c9b824c Gerrit-Change-Number: 28647 Gerrit-PatchSet: 28 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 10 Sep 2019 09:19:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Rizwan Qureshi (Code Review) 10 Sep '19

10 Sep '19

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 43: > Patch Set 43: > > > Patch Set 43: > > > > If a patchset doesn't build don't expect somebody to review it. > > Why is the documentation in a different patch set? > > the errors don't seem to be related to this change, will have a look anyways. > Will squash the documentation in to this one as well. > > i386-elf-ld.bfd: /cb-build/coreboot-gerrit.0/chromeos/GOOGLE_FALCO/bootblock/cpu/intel/microcode/microcode.o: in function `intel_microcode_load_unlocked': > /home/coreboot/slave-root/workspace/coreboot-gerrit/src/cpu/intel/microcode/microcode.c:80: multiple definition of `intel_microcode_load_unlocked'; /cb-build/coreboot-gerrit.0/chromeos/GOOGLE_FALCO/bootblock/cpu/intel/haswell/bootblock.o:/home/coreboot/slave-root/workspace/coreboot-gerrit/src/cpu/intel/microcode/microcode.c:80: first defined here > i386-elf-ld.bfd: /cb-build/coreboot-gerrit.0/chromeos/GOOGLE_FALCO/bootblock/cpu/intel/microcode/microcode.o: in function `get_current_microcode_rev': > /home/coreboot/slave-root/workspace/coreboot-gerrit/src/cpu/intel/microcode/microcode.c:128: multiple definition of `get_current_microcode_rev'; /cb-build/coreboot-gerrit.0/chromeos/GOOGLE_FALCO/bootblock/cpu/intel/haswell/bootblock.o:/home/coreboot/slave-root/workspace/coreboot-gerrit/src/cpu/intel/microcode/microcode.c:128: first defined here > i386-elf-ld.bfd: /cb-build/coreboot-gerrit.0/chromeos/GOOGLE_FALCO/bootblock/cpu/intel/microcode/microcode.o: in function `get_microcode_rev': > /home/coreboot/slave-root/workspace/coreboot-gerrit/src/cpu/intel/microcode/microcode.c:133: multiple definition of `get_microcode_rev'; /cb-build/coreboot-gerrit.0/chromeos/GOOGLE_FALCO/bootblock/cpu/intel/haswell/bootblock.o:/home/coreboot/slave-root/workspace/coreboot-gerrit/src/cpu/intel/microcode/microcode.c:133: first defined here Aah, they are because of the previous patch in the train -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 43 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Tue, 10 Sep 2019 08:14:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Rizwan Qureshi (Code Review) 10 Sep '19

10 Sep '19

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 43: > Patch Set 43: > > If a patchset doesn't build don't expect somebody to review it. > Why is the documentation in a different patch set? the errors don't seem to be related to this change, will have a look anyways. Will squash the documentation in to this one as well. i386-elf-ld.bfd: /cb-build/coreboot-gerrit.0/chromeos/GOOGLE_FALCO/bootblock/cpu/intel/microcode/microcode.o: in function `intel_microcode_load_unlocked': /home/coreboot/slave-root/workspace/coreboot-gerrit/src/cpu/intel/microcode/microcode.c:80: multiple definition of `intel_microcode_load_unlocked'; /cb-build/coreboot-gerrit.0/chromeos/GOOGLE_FALCO/bootblock/cpu/intel/haswell/bootblock.o:/home/coreboot/slave-root/workspace/coreboot-gerrit/src/cpu/intel/microcode/microcode.c:80: first defined here i386-elf-ld.bfd: /cb-build/coreboot-gerrit.0/chromeos/GOOGLE_FALCO/bootblock/cpu/intel/microcode/microcode.o: in function `get_current_microcode_rev': /home/coreboot/slave-root/workspace/coreboot-gerrit/src/cpu/intel/microcode/microcode.c:128: multiple definition of `get_current_microcode_rev'; /cb-build/coreboot-gerrit.0/chromeos/GOOGLE_FALCO/bootblock/cpu/intel/haswell/bootblock.o:/home/coreboot/slave-root/workspace/coreboot-gerrit/src/cpu/intel/microcode/microcode.c:128: first defined here i386-elf-ld.bfd: /cb-build/coreboot-gerrit.0/chromeos/GOOGLE_FALCO/bootblock/cpu/intel/microcode/microcode.o: in function `get_microcode_rev': /home/coreboot/slave-root/workspace/coreboot-gerrit/src/cpu/intel/microcode/microcode.c:133: multiple definition of `get_microcode_rev'; /cb-build/coreboot-gerrit.0/chromeos/GOOGLE_FALCO/bootblock/cpu/intel/haswell/bootblock.o:/home/coreboot/slave-root/workspace/coreboot-gerrit/src/cpu/intel/microcode/microcode.c:133: first defined here -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 43 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Tue, 10 Sep 2019 08:12:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Patrick Rudolph (Code Review) 10 Sep '19

10 Sep '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 43: If a patchset doesn't build don't expect somebody to review it. Why is the documentation in a different patch set? -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 43 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Tue, 10 Sep 2019 06:58:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "intel/fsp2_0: Move temporary RAM to .bss with FSP_USES_CB_STACK"
by Lean Sheng Tan (Code Review) 10 Sep '19

10 Sep '19

Hello Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Nathaniel L Desimone, Subrata Banik, Marshall Dawson, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35324 to review the following change. Change subject: Revert "intel/fsp2_0: Move temporary RAM to .bss with FSP_USES_CB_STACK" ...................................................................... Revert "intel/fsp2_0: Move temporary RAM to .bss with FSP_USES_CB_STACK" This reverts commit c9871505f115f0e5722bf23b13f4390c8d76d0da. Reason for revert: <INSERT REASONING HERE> Change-Id: I46889a3860a0704f9011c8227005207dcb740d0e --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/memory_init.c 2 files changed, 12 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/35324/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 541ec47..3fb39d5 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -152,11 +152,6 @@ without reinitializing stack pointer. This feature is supported Icelake onwards. -config FSP_TEMP_RAM_SIZE - hex - default 0x10000 - depends on FSP_USES_CB_STACK - config VERIFY_HOBS bool "Verify the FSP hand-off-blocks" default n diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 9789c96..0797c2e 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -34,8 +34,6 @@ #include <fsp/memory_init.h> #include <types.h> -static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); - /* TPM MRC hash functionality depends on vboot starting before memory init. */ _Static_assert(!CONFIG(FSP2_0_USES_TPM_MRC_HASH) || CONFIG(VBOOT_STARTS_IN_BOOTBLOCK), @@ -163,7 +161,6 @@ return CB_SUCCESS; } - static enum cb_err setup_fsp_stack_frame(FSPM_ARCH_UPD *arch_upd, const struct memranges *memmap) { @@ -171,6 +168,17 @@ uintptr_t stack_end; /* + * FSP 2.1 version would use same stack as coreboot instead of + * setting up seprate stack frame. FSP 2.1 would not relocate stack + * top and does not reinitialize stack pointer. + */ + if (CONFIG(FSP_USES_CB_STACK)) { + arch_upd->StackBase = (void *)_car_stack_start; + arch_upd->StackSize = CONFIG_DCACHE_BSP_STACK_SIZE; + return CB_SUCCESS; + } + + /* * FSPM_UPD passed here is populated with default values * provided by the blob itself. We let FSPM use top of CAR * region of the size it requests. @@ -189,19 +197,8 @@ bool s3wake, uint32_t fsp_version, const struct memranges *memmap) { - /* - * FSP 2.1 version would use same stack as coreboot instead of - * setting up separate stack frame. FSP 2.1 would not relocate stack - * top and does not reinitialize stack pointer. The parameters passed - * as StackBase and StackSize are actually for temporary RAM and HOBs - * and are not related to FSP stack at all. - */ - if (CONFIG(FSP_USES_CB_STACK)) { - arch_upd->StackBase = temp_ram; - arch_upd->StackSize = sizeof(temp_ram); - } else if (setup_fsp_stack_frame(arch_upd, memmap)) { + if (setup_fsp_stack_frame(arch_upd, memmap)) return CB_ERR; - } fsp_fill_mrc_cache(arch_upd, fsp_version); -- To view, visit https://review.coreboot.org/c/coreboot/+/35324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46889a3860a0704f9011c8227005207dcb740d0e Gerrit-Change-Number: 35324 Gerrit-PatchSet: 1 Gerrit-Owner: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/fsp2_0: Move temporary RAM to .bss with FSP_USES_CB_STACK
by Kyösti Mälkki (Code Review) 10 Sep '19

10 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35233 ) Change subject: intel/fsp2_0: Move temporary RAM to .bss with FSP_USES_CB_STACK ...................................................................... intel/fsp2_0: Move temporary RAM to .bss with FSP_USES_CB_STACK The documentation for StackBase and StackSize in FSPM_ARCH_UPD is confusing. Previously the region was shared for heap and stack, starting with FSP2.1 only for heap (or 'temporary RAM') for HOBs. Moving the allocation outside DCACHE_BSP_STACK_SIZE allows use of stack guards and reduces amount of reserved CAR for bootblock and verstage, as the new allocation in .bss is only taken in romstage. Change-Id: I4cffcc73a89cb97ab7759dd373196ce9753a6307 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/intel/fsp2_0/memory_init.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/icelake/Kconfig 3 files changed, 15 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/35233/1 diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 0797c2e..dbaecdb 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -34,6 +34,8 @@ #include <fsp/memory_init.h> #include <types.h> +static char temp_ram[0x20000]; + /* TPM MRC hash functionality depends on vboot starting before memory init. */ _Static_assert(!CONFIG(FSP2_0_USES_TPM_MRC_HASH) || CONFIG(VBOOT_STARTS_IN_BOOTBLOCK), @@ -161,6 +163,7 @@ return CB_SUCCESS; } + static enum cb_err setup_fsp_stack_frame(FSPM_ARCH_UPD *arch_upd, const struct memranges *memmap) { @@ -168,17 +171,6 @@ uintptr_t stack_end; /* - * FSP 2.1 version would use same stack as coreboot instead of - * setting up seprate stack frame. FSP 2.1 would not relocate stack - * top and does not reinitialize stack pointer. - */ - if (CONFIG(FSP_USES_CB_STACK)) { - arch_upd->StackBase = (void *)_car_stack_start; - arch_upd->StackSize = CONFIG_DCACHE_BSP_STACK_SIZE; - return CB_SUCCESS; - } - - /* * FSPM_UPD passed here is populated with default values * provided by the blob itself. We let FSPM use top of CAR * region of the size it requests. @@ -197,8 +189,19 @@ bool s3wake, uint32_t fsp_version, const struct memranges *memmap) { - if (setup_fsp_stack_frame(arch_upd, memmap)) + /* + * FSP 2.1 version would use same stack as coreboot instead of + * setting up separate stack frame. FSP 2.1 would not relocate stack + * top and does not reinitialize stack pointer. The parameters passed + * as StackBase and StackSize are actually for temporary RAM and HOBs + * and are not related to FSP stack at all. + */ + if (CONFIG(FSP_USES_CB_STACK)) { + arch_upd->StackBase = temp_ram; + arch_upd->StackSize = sizeof(temp_ram); + } else if (setup_fsp_stack_frame(arch_upd, memmap)) { return CB_ERR; + } fsp_fill_mrc_cache(arch_upd, fsp_version); diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index d949fff..2c5a884 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -119,7 +119,6 @@ config DCACHE_BSP_STACK_SIZE hex - default 0x20000 if FSP_USES_CB_STACK default 0x4000 help The amount of anticipated stack usage in CAR by bootblock and diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 1bd478c..399a59c 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -70,7 +70,6 @@ config DCACHE_BSP_STACK_SIZE hex - default 0x20000 if FSP_USES_CB_STACK default 0x4000 help The amount of anticipated stack usage in CAR by bootblock and -- To view, visit https://review.coreboot.org/c/coreboot/+/35233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cffcc73a89cb97ab7759dd373196ce9753a6307 Gerrit-Change-Number: 35233 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Update southbridge
by Richard Spiegel (Code Review) 10 Sep '19

10 Sep '19

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33770 ) Change subject: soc/amd/picasso: Update southbridge ...................................................................... Patch Set 14: (1 comment) https://review.coreboot.org/c/coreboot/+/33770/13/src/soc/amd/picasso/inclu… File src/soc/amd/picasso/include/soc/southbridge.h: https://review.coreboot.org/c/coreboot/+/33770/13/src/soc/amd/picasso/inclu… PS13, Line 229: 0x5b > You're right. […] LOL... last code was mine... Initial code was AMD's, one AOAC at a time. I made it all together to save wait time, though maintained registers definitions as per AMD. I like your new way. -- To view, visit https://review.coreboot.org/c/coreboot/+/33770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69dfc4a875006639aa330385680d150331840e40 Gerrit-Change-Number: 33770 Gerrit-PatchSet: 14 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 10 Sep 2019 00:01:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Comment-In-Reply-To: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: comment

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