coreboot-gerrit September 2019

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Change in coreboot[master]: soc/intel/common/block/cse: Move me_read_config32() to common code
by Sridhar Siricilla (Code Review) 11 Sep '19

11 Sep '19

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35225 ) Change subject: soc/intel/common/block/cse: Move me_read_config32() to common code ...................................................................... soc/intel/common/block/cse: Move me_read_config32() to common code me_read_config32() is defined in multiple places, move it to common location. Also, move HFSTS macros specific to CSE PCI config header into common header file. Change-Id: Icdbfb6b30a007d469b5e018a313c14586addb130 Signed-off-by: sridhar <sridhar.siricilla(a)intel.com> --- M src/soc/intel/apollolake/cse.c M src/soc/intel/cannonlake/me.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/skylake/include/soc/me.h M src/soc/intel/skylake/me.c 6 files changed, 51 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35225/1 diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index 82226ec..32e9222 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -28,12 +28,6 @@ #include <device/pci_ops.h> #include <stdint.h> -#define PCI_ME_HFSTS1 0x40 -#define PCI_ME_HFSTS2 0x48 -#define PCI_ME_HFSTS3 0x60 -#define PCI_ME_HFSTS4 0x64 -#define PCI_ME_HFSTS5 0x68 -#define PCI_ME_HFSTS6 0x6c #define MKHI_GROUP_ID_MCA 0x0a #define READ_FILE 0x02 @@ -49,6 +43,8 @@ #define FUSE_LOCK_FILE "/fpf/intel/SocCfgLock" +#define dump_status(index, hfs_reg) me_read_config32(hfs_reg) + /* Status values are made in such a way erase is not needed */ static enum fuse_flash_state { FUSE_FLASH_FUSED = 0xfc, @@ -186,15 +182,6 @@ printk(BIOS_CRIT, "failed to save FPF state\n"); } -static uint32_t dump_status(int index, int reg_addr) -{ - uint32_t reg = pci_read_config32(PCH_DEV_CSE, reg_addr); - - printk(BIOS_DEBUG, "CSE FWSTS%d: 0x%08x\n", index, reg); - - return reg; -} - static void dump_cse_version(void *unused) { int res; diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index b8b4245d..dab909b 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -32,16 +32,6 @@ ME_WSTATE_NORMAL = 0x05, }; -/* HFSTS register offsets in PCI config space */ -enum { - PCI_ME_HFSTS1 = 0x40, - PCI_ME_HFSTS2 = 0x48, - PCI_ME_HFSTS3 = 0x60, - PCI_ME_HFSTS4 = 0x64, - PCI_ME_HFSTS5 = 0x68, - PCI_ME_HFSTS6 = 0x6C, -}; - /* Host Firmware Status Register 1 */ union hfsts1 { uint32_t raw; @@ -155,11 +145,6 @@ } __packed fields; }; -static uint32_t me_read_config32(int offset) -{ - return pci_read_config32(PCH_DEV_CSE, offset); -} - /* * From reading the documentation, this should work for both WHL and CML * platforms. Also, calling this function from dump_me_status() does not diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 97989f7..69cb273 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -507,6 +507,39 @@ return 0; } +uint32_t me_read_config32(int offset) +{ + uint32_t reg; + + reg = pci_read_config32(PCH_DEV_CSE, offset); + + if (!CONFIG(CONSOLE_SERIAL)) + { + uint8_t index; + + if( offset == PCI_ME_HFSTS1) + index = 1; + else if (offset == PCI_ME_HFSTS2) + index = 2; + else if (offset == PCI_ME_HFSTS3) + index = 3; + else if (offset == PCI_ME_HFSTS4) + index = 4; + else if (offset == PCI_ME_HFSTS5) + index = 5; + else if (offset == PCI_ME_HFSTS6) + index = 6; + else + index = 0; + + if (index != 0) + printk(BIOS_DEBUG, "CSE FWSTS%d: 0x%08x\n", index, reg); + else + printk(BIOS_DEBUG, "CSE [0x%x]=0x%08x\n", offset, reg); + } + return reg; +} + #if ENV_RAMSTAGE diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 371a781..9409ce5 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -53,7 +53,23 @@ */ int heci_reset(void); +/* + * Reads config value from a specified offset in the HECI Configuration + * + */ +uint32_t me_read_config32(int offset); + #define BIOS_HOST_ADDR 0x00 #define HECI_MKHI_ADDR 0x07 +/* HFSTS register offsets in PCI config space */ +enum { + PCI_ME_HFSTS1 = 0x40, + PCI_ME_HFSTS2 = 0x48, + PCI_ME_HFSTS3 = 0x60, + PCI_ME_HFSTS4 = 0x64, + PCI_ME_HFSTS5 = 0x68, + PCI_ME_HFSTS6 = 0x6C, +}; + #endif // SOC_INTEL_COMMON_MSR_H diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index 5a9acd5..fbe5033 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -21,7 +21,6 @@ /* * Management Engine PCI registers */ -#define PCI_ME_HFSTS1 0x40 #define ME_HFS_CWS_RESET 0 #define ME_HFS_CWS_INIT 1 #define ME_HFS_CWS_REC 2 @@ -169,7 +168,6 @@ } __packed fields; }; -#define PCI_ME_HFSTS3 0x60 #define ME_HFS3_FW_SKU_CONSUMER 0x2 #define ME_HFS3_FW_SKU_CORPORATE 0x3 @@ -186,9 +184,6 @@ } __packed fields; }; -#define PCI_ME_HFSTS4 0x64 -#define PCI_ME_HFSTS5 0x68 -#define PCI_ME_HFSTS6 0x6c #define ME_HFS6_FPF_NOT_COMMITTED 0x0 #define ME_HFS6_FPF_ERROR 0x2 diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index f7aa584..e8d75e3 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -26,10 +26,6 @@ #include <stdlib.h> #include <string.h> -static inline u32 me_read_config32(int offset) -{ - return pci_read_config32(PCH_DEV_CSE, offset); -} /* HFSTS1[3:0] Current Working State Values */ static const char *const me_cws_values[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/35225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdbfb6b30a007d469b5e018a313c14586addb130 Gerrit-Change-Number: 35225 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

6 54

Change in coreboot[master]: src/soc/intel/common/itss: Add support to get IRQ configuration for P...
by Aamir Bohra (Code Review) 11 Sep '19

11 Sep '19

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34089 ) Change subject: src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices ...................................................................... Patch Set 19: (2 comments) https://review.coreboot.org/c/coreboot/+/34089/18/src/soc/intel/common/bloc… File src/soc/intel/common/block/itss/irq.c: https://review.coreboot.org/c/coreboot/+/34089/18/src/soc/intel/common/bloc… PS18, Line 41: > it can extend beyond the 8 IRQ assingments. […] Done, Added a print to indicate the conflict. https://review.coreboot.org/c/coreboot/+/34089/18/src/soc/intel/common/bloc… PS18, Line 99: index > ok, I can add a return in else here. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/34089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7066432ff5f0d7017ac5a44922ca69f07da9556 Gerrit-Change-Number: 34089 Gerrit-PatchSet: 19 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 11 Sep 2019 09:21:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: src/soc/intel/common/itss: Add support to get IRQ configuration for P...
by Aamir Bohra (Code Review) 11 Sep '19

11 Sep '19

Hello Patrick Rudolph, Karthik Ramasubramanian, Paul Fagerburg, Subrata Banik, Arthur Heymans, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34089 to look at the new patch set (#19). Change subject: src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices ...................................................................... src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices Add implementation to fill PCI IRQ table. Each IRQ entry in the table would have information on PCI device number, bus number, irq number and INTx mapping information. This table will be used by FSP as interrupt config to program ITSS PIRx register and also to program interrupt pin for LPSS controllers. Change-Id: Ib7066432ff5f0d7017ac5a44922ca69f07da9556 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- A src/soc/intel/common/block/include/intelblocks/irq.h M src/soc/intel/common/block/itss/Kconfig M src/soc/intel/common/block/itss/Makefile.inc A src/soc/intel/common/block/itss/irq.c 4 files changed, 183 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/34089/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/34089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7066432ff5f0d7017ac5a44922ca69f07da9556 Gerrit-Change-Number: 34089 Gerrit-PatchSet: 19 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: arch/x86: Fix .bss section in CAR
by Kyösti Mälkki (Code Review) 11 Sep '19

11 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35034 ) Change subject: arch/x86: Fix .bss section in CAR ...................................................................... arch/x86: Fix .bss section in CAR Fix clearing CAR region, 'stosl' stores 4 bytes at a time. Restrict the use of symbol names _car_global_[start|end] to be used exclusively with CAR_GLOBAL_MIGRATION=y. They just alias the start and end of .bss section in CAR. Change-Id: I36c858a4f181516d4c61f9fd1d5005c7d2c06057 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/assembly_entry.S M src/arch/x86/car.ld M src/arch/x86/include/arch/early_variables.h M src/arch/x86/include/arch/symbols.h M src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S M src/soc/intel/quark/romstage/fsp2_0.c 6 files changed, 38 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/35034/1 diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 4ead9ea..b3871d6 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -35,12 +35,13 @@ /* reset stack pointer to CAR stack */ mov $_car_stack_end, %esp - /* clear CAR_GLOBAL area as it is not shared */ + /* clear .bss section as it is not shared */ cld xor %eax, %eax - movl $(_car_global_end), %ecx - movl $(_car_global_start), %edi + movl $(_ebss), %ecx + movl $(_bss), %edi sub %edi, %ecx + shrl $2, %ecx rep stosl #if ((ENV_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \ diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 822f7fd..bc0090b 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -68,11 +68,13 @@ . += 80; _car_ehci_dbg_info_end = .; - /* _car_global_start and _car_global_end provide symbols to per-stage + /* _bss and _ebss provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram * cbmem console. This is useful for clearing this area on a per-stage * basis when more than one stage uses cache-as-ram for CAR_GLOBALs. */ - _car_global_start = .; + + . = ALIGN(ARCH_POINTER_ALIGN_SIZE); + _bss = .; #if ENV_STAGE_HAS_BSS_SECTION /* Allow global uninitialized variables for stages without CAR teardown. */ *(.bss) @@ -80,10 +82,12 @@ *(.sbss) *(.sbss.*) #else + _car_global_start = .; *(.car.global_data); + _car_global_end = .; #endif . = ALIGN(ARCH_POINTER_ALIGN_SIZE); - _car_global_end = .; + _ebss = .; #if CONFIG(CAR_GLOBAL_MIGRATION) _car_stack_start = .; diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index b5db194..9e0441c 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -22,6 +22,15 @@ #if ENV_ROMSTAGE && CONFIG(CAR_GLOBAL_MIGRATION) +/* + * The _car_global_[start|end]symbols cover CAR data which is relocatable + * once memory comes online. Variables with CAR_GLOBAL decoration + * reside within this region. + */ +extern char _car_global_start[]; +extern char _car_global_end[]; +#define _car_global_size (_car_global_end - _car_global_start) + asm(".section .car.global_data,\"w\",@nobits"); asm(".previous"); #ifdef __clang__ diff --git a/src/arch/x86/include/arch/symbols.h b/src/arch/x86/include/arch/symbols.h index 5d65a7b..3f2e978 100644 --- a/src/arch/x86/include/arch/symbols.h +++ b/src/arch/x86/include/arch/symbols.h @@ -27,25 +27,26 @@ #define _car_region_size (_car_region_end - _car_region_start) /* - * This is the stack used under CONFIG_C_ENVIRONMENT_BOOTBLOCK for - * all stages that execute when cache-as-ram is up. + * This is the stack area used for all stages that execute when cache-as-ram + * is up. Area is not cleared in between stages. */ extern char _car_stack_start[]; extern char _car_stack_end[]; #define _car_stack_size (_car_stack_end - _car_stack_start) +/* + * This is the .bss section cleared between each stage. It is not + * available in romstage if CAR_GLOBAL_MIGRATION is enabled. + */ +extern char _bss[]; +extern char _ebss[]; +#define _bss_size (_ebss - _bss) + +extern char _car_unallocated_start; + extern char _car_ehci_dbg_info_start[]; extern char _car_ehci_dbg_info_end[]; #define _car_ehci_dbg_info_size \ (_car_ehci_dbg_info_end - _car_ehci_dbg_info_start) -/* - * The _car_global_[start|end]symbols cover CAR data which is relocatable - * once memory comes online. Variables with CAR_GLOBAL decoration - * reside within this region. - */ -extern char _car_global_start[]; -extern char _car_global_end[]; -#define _car_global_size (_car_global_end - _car_global_start) - #endif diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S index 9a8ab5b..091fc4a 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S @@ -89,11 +89,11 @@ /* Setup bootblock stack */ mov %edx, %esp - /* clear CAR_GLOBAL area as it is not shared */ + /* clear .bss section as it is not shared */ cld xor %eax, %eax - movl $(_car_global_end), %ecx - movl $(_car_global_start), %edi + movl $(_ebss), %ecx + movl $(_bss), %edi sub %edi, %ecx shrl $2, %ecx rep stosl diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index e6da5dd..0cf2d80 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -14,6 +14,7 @@ */ #include <arch/cpu.h> +#include <arch/early_variables.h> #include <arch/romstage.h> #include <arch/symbols.h> #include <console/console.h> @@ -142,10 +143,10 @@ aupd->StackBase); printk(BIOS_SPEW, "| |\n"); printk(BIOS_SPEW, "+-------------------+ 0x%p\n", - _car_global_end); + _bss); printk(BIOS_SPEW, "| coreboot data |\n"); printk(BIOS_SPEW, "+-------------------+ 0x%p\n", - _car_stack_end); + _car_stack_start); printk(BIOS_SPEW, "| coreboot stack |\n"); printk(BIOS_SPEW, "+-------------------+ 0x80000000 - ESRAM start\n\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/35034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36c858a4f181516d4c61f9fd1d5005c7d2c06057 Gerrit-Change-Number: 35034 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: arch/x86: Drop _car_relocatable_data symbols
by Kyösti Mälkki (Code Review) 11 Sep '19

11 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35033 ) Change subject: arch/x86: Drop _car_relocatable_data symbols ...................................................................... arch/x86: Drop _car_relocatable_data symbols These have become aliases to _car_global_[start|end]. Change-Id: Ibdcaaafdc0e4c6df4a795474903768230d41680d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/car.ld M src/arch/x86/include/arch/early_variables.h M src/arch/x86/include/arch/symbols.h M src/cpu/amd/car/post_cache_as_ram.c M src/cpu/x86/car.c M src/drivers/intel/fsp2_0/memory_init.c M src/soc/intel/quark/romstage/fsp2_0.c 7 files changed, 18 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/35033/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 25b667c..822f7fd 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -68,8 +68,6 @@ . += 80; _car_ehci_dbg_info_end = .; - _car_relocatable_data_start = .; - /* _car_global_start and _car_global_end provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram * cbmem console. This is useful for clearing this area on a per-stage @@ -82,18 +80,18 @@ *(.sbss) *(.sbss.*) #else - /* .car.global_data objects only around when - * CONFIG_CAR_GLOBAL_MIGRATION is employed. */ *(.car.global_data); #endif . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _car_global_end = .; - _car_relocatable_data_end = .; #if CONFIG(CAR_GLOBAL_MIGRATION) _car_stack_start = .; _car_stack_end = _car_region_end; +#else + _car_unallocated_start = .; #endif + _car_region_end = . + CONFIG_DCACHE_RAM_SIZE - (. - _car_region_start); } diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index 3910a82..b5db194 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -48,13 +48,13 @@ static inline size_t car_data_size(void) { - size_t car_size = _car_relocatable_data_size; - return ALIGN_UP(car_size, 64); + size_t car_size = _car_global_size; + return ALIGN(car_size, 64); } static inline size_t car_object_offset(void *ptr) { - return (char *)ptr - &_car_relocatable_data_start[0]; + return (char *)ptr - &_car_global_start[0]; } #else diff --git a/src/arch/x86/include/arch/symbols.h b/src/arch/x86/include/arch/symbols.h index 97a07c0..5d65a7b 100644 --- a/src/arch/x86/include/arch/symbols.h +++ b/src/arch/x86/include/arch/symbols.h @@ -40,16 +40,10 @@ (_car_ehci_dbg_info_end - _car_ehci_dbg_info_start) /* - * The _car_relocatable_data_[start|end] symbols cover CAR data which is - * relocatable once memory comes online. Variables with CAR_GLOBAL decoration - * reside within this region. The _car_global_[start|end] is a subset of the - * relocatable region which excludes the timestamp region because of - * intricacies in the timestamp code. + * The _car_global_[start|end]symbols cover CAR data which is relocatable + * once memory comes online. Variables with CAR_GLOBAL decoration + * reside within this region. */ -extern char _car_relocatable_data_start[]; -extern char _car_relocatable_data_end[]; -#define _car_relocatable_data_size \ - (_car_relocatable_data_end - _car_relocatable_data_start) extern char _car_global_start[]; extern char _car_global_end[]; #define _car_global_size (_car_global_end - _car_global_start) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index dfa4c3d..bf701ff 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -107,11 +107,11 @@ void *migrated_car = (void *)(CONFIG_RAMTOP - car_size); print_car_debug("Copying data from cache to RAM..."); - memcpy_(migrated_car, _car_relocatable_data_start, car_size); + memcpy_(migrated_car, _car_global_start, car_size); print_car_debug(" Done\n"); print_car_debug("Verifying data integrity in RAM..."); - if (memcmp_(migrated_car, _car_relocatable_data_start, car_size) == 0) + if (memcmp_(migrated_car, _car_global_start, car_size) == 0) print_car_debug(" Done\n"); else print_car_debug(" FAILED\n"); diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index 6fc6168..62ab83b 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -46,8 +46,8 @@ { char *migrated_base = NULL; int offset; - void *_car_start = _car_relocatable_data_start; - void *_car_end = _car_relocatable_data_end; + void *_car_start = _car_global_start; + void *_car_end = _car_global_end; /* If the cache-as-ram has not been migrated return the pointer * passed in. */ @@ -84,8 +84,8 @@ void *car_sync_var_ptr(void *var) { void **mig_var = car_get_var_ptr(var); - void *_car_start = _car_relocatable_data_start; - void *_car_end = _car_relocatable_data_end; + void *_car_start = _car_global_start; + void *_car_end = _car_global_end; /* Not moved or migrated yet. */ if (mig_var == var) @@ -134,7 +134,7 @@ return; } - memcpy(migrated_base, _car_relocatable_data_start, car_size); + memcpy(migrated_base, _car_global_start, car_size); /* Mark that the data has been moved. */ car_migrated = ~0; diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 0797c2e..17686c8 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -404,7 +404,7 @@ /* Build up memory map of romstage address space including CAR. */ memranges_init_empty(&memmap, &freeranges[0], ARRAY_SIZE(freeranges)); memranges_insert(&memmap, (uintptr_t)_car_region_start, - _car_relocatable_data_end - _car_region_start, 0); + _car_unallocated_start - _car_region_start, 0); memranges_insert(&memmap, (uintptr_t)_program, REGION_SIZE(program), 0); if (!CONFIG(FSP_M_XIP)) diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 0489621..e6da5dd 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -142,7 +142,7 @@ aupd->StackBase); printk(BIOS_SPEW, "| |\n"); printk(BIOS_SPEW, "+-------------------+ 0x%p\n", - _car_relocatable_data_end); + _car_global_end); printk(BIOS_SPEW, "| coreboot data |\n"); printk(BIOS_SPEW, "+-------------------+ 0x%p\n", _car_stack_end); -- To view, visit https://review.coreboot.org/c/coreboot/+/35033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdcaaafdc0e4c6df4a795474903768230d41680d Gerrit-Change-Number: 35033 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: Revert "mb/google/hatch: Distinguish SKU1 and 2 for eMMC and SSD resp...
by Peichao Li (Code Review) 11 Sep '19

11 Sep '19

Hello Marco Chen, Philip Chen, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Martin Roth, Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35325 to review the following change. Change subject: Revert "mb/google/hatch: Distinguish SKU1 and 2 for eMMC and SSD respectively" ...................................................................... Revert "mb/google/hatch: Distinguish SKU1 and 2 for eMMC and SSD respectively" This reverts commit 0328a723b8d5d874e1528cda09a9e85d436a66f8. Reason for revert: <INSERT REASONING HERE> Change-Id: Iaa14b9c154d7965f84e26481817555556195f1da --- M src/mainboard/google/hatch/variants/akemi/Makefile.inc M src/mainboard/google/hatch/variants/akemi/gpio.c D src/mainboard/google/hatch/variants/akemi/variant.c 3 files changed, 24 insertions(+), 204 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35325/1 diff --git a/src/mainboard/google/hatch/variants/akemi/Makefile.inc b/src/mainboard/google/hatch/variants/akemi/Makefile.inc index 6cabe91..2f590bf 100644 --- a/src/mainboard/google/hatch/variants/akemi/Makefile.inc +++ b/src/mainboard/google/hatch/variants/akemi/Makefile.inc @@ -21,4 +21,3 @@ bootblock-y += gpio.c ramstage-y += gpio.c -ramstage-y += variant.c diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index 27b49e5..5a58839 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -19,148 +19,6 @@ #include <commonlib/helpers.h> #include <console/console.h> -static const struct pad_config ssd_sku_gpio_table[] = { - /* A0 : NC */ - PAD_NC(GPP_A0, NONE), - /* A6 : NC */ - PAD_NC(GPP_A6, NONE), - /* A8 : NC */ - PAD_NC(GPP_A8, NONE), - /* A10 : NC */ - PAD_NC(GPP_A10, NONE), - /* A11 : NC */ - PAD_NC(GPP_A11, NONE), - /* A12 : NC */ - PAD_NC(GPP_A12, NONE), - /* A18 : NC */ - PAD_NC(GPP_A18, NONE), - /* A19 : NC */ - PAD_NC(GPP_A19, NONE), - /* A22 : NC */ - PAD_NC(GPP_A22, NONE), - /* A23 : NC */ - PAD_NC(GPP_A23, NONE), - /* B20 : NC */ - PAD_NC(GPP_B20, NONE), - /* B21 : NC */ - PAD_NC(GPP_B21, NONE), - /* B22 : NC */ - PAD_NC(GPP_B22, NONE), - /* C11 : NC */ - PAD_NC(GPP_C11, NONE), - /* C15 : NC */ - PAD_NC(GPP_C15, NONE), - /* F1 : NC */ - PAD_NC(GPP_F1, NONE), - /* F3 : MEM_STRAP_3 */ - PAD_CFG_GPI(GPP_F3, NONE, PLTRST), - /* F10 : MEM_STRAP_2 */ - PAD_CFG_GPI(GPP_F10, NONE, PLTRST), - /* F11 : NC */ - PAD_NC(GPP_F11, NONE), - /* F12 : NC */ - PAD_NC(GPP_F12, NONE), - /* F13 : NC */ - PAD_NC(GPP_F13, NONE), - /* F14 : NC */ - PAD_NC(GPP_F14, NONE), - /* F15 : NC */ - PAD_NC(GPP_F15, NONE), - /* F16 : NC */ - PAD_NC(GPP_F16, NONE), - /* F17 : NC */ - PAD_NC(GPP_F17, NONE), - /* F18 : NC */ - PAD_NC(GPP_F18, NONE), - /* F19 : NC */ - PAD_NC(GPP_F19, NONE), - /* F20 : NC */ - PAD_NC(GPP_F20, NONE), - /* F21 : NC */ - PAD_NC(GPP_F21, NONE), - /* F22 : NC */ - PAD_NC(GPP_F22, NONE), - /* H6 : NC */ - PAD_NC(GPP_H6, NONE), - /* H7 : NC */ - PAD_NC(GPP_H7, NONE), - /* H19 : MEM_STRAP_0 */ - PAD_CFG_GPI(GPP_H19, NONE, PLTRST), - /* H22 : MEM_STRAP_1 */ - PAD_CFG_GPI(GPP_H22, NONE, PLTRST), -}; - -static const struct pad_config emmc_sku_gpio_table[] = { - /* A0 : NC */ - PAD_NC(GPP_A0, NONE), - /* A6 : NC */ - PAD_NC(GPP_A6, NONE), - /* A8 : NC */ - PAD_NC(GPP_A8, NONE), - /* A10 : NC */ - PAD_NC(GPP_A10, NONE), - /* A11 : NC */ - PAD_NC(GPP_A11, NONE), - /* A12 : NC */ - PAD_NC(GPP_A12, NONE), - /* A18 : NC */ - PAD_NC(GPP_A18, NONE), - /* A19 : NC */ - PAD_NC(GPP_A19, NONE), - /* A22 : NC */ - PAD_NC(GPP_A22, NONE), - /* A23 : NC */ - PAD_NC(GPP_A23, NONE), - /* B20 : NC */ - PAD_NC(GPP_B20, NONE), - /* B21 : NC */ - PAD_NC(GPP_B21, NONE), - /* B22 : NC */ - PAD_NC(GPP_B22, NONE), - /* C11 : NC */ - PAD_NC(GPP_C11, NONE), - /* C15 : NC */ - PAD_NC(GPP_C15, NONE), - /* F1 : NC */ - PAD_NC(GPP_F1, NONE), - /* F3 : MEM_STRAP_3 */ - PAD_CFG_GPI(GPP_F3, NONE, PLTRST), - /* F10 : MEM_STRAP_2 */ - PAD_CFG_GPI(GPP_F10, NONE, PLTRST), - /* F11 : EMMC_CMD ==> EMMC_CMD */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), - /* F12 : EMMC_DATA0 ==> EMMC_DAT0 */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - /* F13 : EMMC_DATA1 ==> EMMC_DAT1 */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - /* F14 : EMMC_DATA2 ==> EMMC_DAT2 */ - PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), - /* F15 : EMMC_DATA3 ==> EMMC_DAT3 */ - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - /* F16 : EMMC_DATA4 ==> EMMC_DAT4 */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), - /* F17 : EMMC_DATA5 ==> EMMC_DAT5 */ - PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), - /* F18 : EMMC_DATA6 ==> EMMC_DAT6 */ - PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), - /* F19 : EMMC_DATA7 ==> EMMC_DAT7 */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* F20 : EMMC_RCLK ==> EMMC_RCLK */ - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - /* F21 : EMMC_CLK ==> EMMC_CLK */ - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - /* F22 : EMMC_RESET# ==> EMMC_RST_L */ - PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), - /* H6 : NC */ - PAD_NC(GPP_H6, NONE), - /* H7 : NC */ - PAD_NC(GPP_H7, NONE), - /* H19 : MEM_STRAP_0 */ - PAD_CFG_GPI(GPP_H19, NONE, PLTRST), - /* H22 : MEM_STRAP_1 */ - PAD_CFG_GPI(GPP_H22, NONE, PLTRST), -}; - static const struct pad_config gpio_table[] = { /* A0 : NC */ PAD_NC(GPP_A0, NONE), @@ -234,17 +92,6 @@ const struct pad_config *override_gpio_table(size_t *num) { - uint32_t sku_id = get_board_sku(); - /* For SSD SKU */ - if (sku_id == 2) { - *num = ARRAY_SIZE(ssd_sku_gpio_table); - return ssd_sku_gpio_table; - } - /* For eMMC SKU */ - if (sku_id == 1) { - *num = ARRAY_SIZE(emmc_sku_gpio_table); - return emmc_sku_gpio_table; - } *num = ARRAY_SIZE(gpio_table); return gpio_table; } @@ -281,6 +128,30 @@ PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), /* F2 : MEM_CH_SEL */ PAD_CFG_GPI(GPP_F2, NONE, PLTRST), + /* F11 : EMMC_CMD ==> EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 ==> EMMC_DAT0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 ==> EMMC_DAT1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 ==> EMMC_DAT2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 ==> EMMC_DAT3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 ==> EMMC_DAT4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 ==> EMMC_DAT5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 ==> EMMC_DAT6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 ==> EMMC_DAT7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK ==> EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK ==> EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RESET# ==> EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/hatch/variants/akemi/variant.c b/src/mainboard/google/hatch/variants/akemi/variant.c deleted file mode 100644 index 0717e81..0000000 --- a/src/mainboard/google/hatch/variants/akemi/variant.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2019 Google LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <baseboard/variants.h> -#include <chip.h> -#include <soc/pci_devs.h> -#include <ec/google/chromeec/ec.h> - -void variant_devtree_update(void) -{ - uint32_t sku_id; - struct device *emmc_host; - struct device *ssd_host; - config_t *cfg = config_of_path(SA_DEVFN_ROOT); - emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC); - ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA); - - /* SKU ID 2 doesn't have a eMMC device, hence disable it. */ - sku_id = get_board_sku(); - if (sku_id == 2) { - if (emmc_host == NULL) - return; - emmc_host->enabled = 0; - cfg->ScsEmmcHs400Enabled = 0; - } - - /* SKU ID 1 doesn't have a SSD device, hence disable it. */ - if (sku_id == 1) { - if (ssd_host == NULL) - return; - ssd_host->enabled = 0; - cfg->SataSalpSupport = 0; - cfg->SataMode = 0; - cfg->SataPortsEnable[1] = 0; - cfg->SataPortsDevSlp[1] = 0; - cfg->satapwroptimize = 0; - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/35325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa14b9c154d7965f84e26481817555556195f1da Gerrit-Change-Number: 35325 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Guohui Zhou <guohui.zhou(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: arch/x86: Move ehci_dbg_info outside _car_relocatable_data
by Kyösti Mälkki (Code Review) 11 Sep '19

11 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35288 ) Change subject: arch/x86: Move ehci_dbg_info outside _car_relocatable_data ...................................................................... arch/x86: Move ehci_dbg_info outside _car_relocatable_data As code already used CBMEM hooks to switch from CAR to CBMEM it was never necessary to have the structure declared inside _car_relocatable_data. Switch to use car_[get|set]_ptr is mostly for consistency, but should also enable use of usbdebug with FSP1.0 romstage. Change-Id: I636251085d84e52a71a1d5d27d795bb94a07422d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/car.ld M src/drivers/usb/ehci_debug.c 2 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35288/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index fe0e723..d3d1443 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -63,13 +63,13 @@ TIMESTAMP(., 0x200) - _car_relocatable_data_start = .; - _car_ehci_dbg_info_start = .; /* Reserve sizeof(struct ehci_dbg_info). */ . += 80; _car_ehci_dbg_info_end = .; + _car_relocatable_data_start = .; + /* _car_global_start and _car_global_end provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram * cbmem console. This is useful for clearing this area on a per-stage diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 638b7c7..0596795 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -67,7 +67,7 @@ static inline struct ehci_debug_info *dbgp_ehci_info(void) { - if (car_get_var(glob_dbg_info_p) == NULL) { + if (car_get_ptr(glob_dbg_info_p) == NULL) { struct ehci_debug_info *info; if (ENV_BOOTBLOCK || ENV_VERSTAGE || ENV_ROMSTAGE) { /* The message likely does not show if we hit this. */ @@ -77,9 +77,9 @@ } else { info = &glob_dbg_info; } - car_set_var(glob_dbg_info_p, info); + car_set_ptr(glob_dbg_info_p, info); } - return car_get_var(glob_dbg_info_p); + return car_get_ptr(glob_dbg_info_p); } static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug) @@ -716,7 +716,7 @@ if (dbg_info_cbmem == NULL) return; memcpy(dbg_info_cbmem, dbg_info, sizeof(*dbg_info)); - car_set_var(glob_dbg_info_p, dbg_info_cbmem); + car_set_ptr(glob_dbg_info_p, dbg_info_cbmem); return; } @@ -724,7 +724,7 @@ /* Use state in CBMEM. */ dbg_info_cbmem = cbmem_find(CBMEM_ID_EHCI_DEBUG); if (dbg_info_cbmem) - car_set_var(glob_dbg_info_p, dbg_info_cbmem); + car_set_ptr(glob_dbg_info_p, dbg_info_cbmem); } rv = usbdebug_hw_init(false); -- To view, visit https://review.coreboot.org/c/coreboot/+/35288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I636251085d84e52a71a1d5d27d795bb94a07422d Gerrit-Change-Number: 35288 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: timestamps: Make ENV_ROMSTAGE_OR_BEFORE improvements
by Kyösti Mälkki (Code Review) 11 Sep '19

11 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35032 ) Change subject: timestamps: Make ENV_ROMSTAGE_OR_BEFORE improvements ...................................................................... timestamps: Make ENV_ROMSTAGE_OR_BEFORE improvements Keep track of the active timestamp table location using a CAR_GLOBAL variable. Done this way, the entire table can be located outside _car_relocatable_data and we just switch the pointer to CBMEM and copy the data before CAR gets torn down. TBD: This probably breaks FSP1_0 which returns to coreboot proper only after tearing down CAR. I have an idea how to fix it though. Change-Id: I87370f62db23318069b6fd56ba0d1171d619cb8a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/car.ld M src/include/timestamp.h M src/lib/timestamp.c 3 files changed, 24 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/35032/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index d19818c..25b667c 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -60,17 +60,16 @@ . += 32; _epdpt = .; #endif - _car_relocatable_data_start = .; - /* The timestamp implementation relies on this storage to be around - * after migration. One of the fields indicates not to use it as the - * backing store once cbmem comes online. Therefore, this data needs - * to reside in the migrated area (between _car_relocatable_data_start - * and _car_relocatable_data_end). */ + TIMESTAMP(., 0x200) + _car_ehci_dbg_info_start = .; /* Reserve sizeof(struct ehci_dbg_info). */ . += 80; _car_ehci_dbg_info_end = .; + + _car_relocatable_data_start = .; + /* _car_global_start and _car_global_end provide symbols to per-stage * variables that are not shared like the timestamp and the pre-ram * cbmem console. This is useful for clearing this area on a per-stage diff --git a/src/include/timestamp.h b/src/include/timestamp.h index 04d5c12..1fa568c 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -22,11 +22,10 @@ #if CONFIG(COLLECT_TIMESTAMPS) /* * timestamp_init() needs to be called once for each of these cases: - * 1. __PRE_RAM__ (bootblock, romstage, verstage, etc) and - * 2. !__PRE_RAM__ (ramstage) + * 1. ENV_ROMSTAGE_OR_BEFORE (bootblock, romstage, verstage, etc) and + * 2. ENV_RAMSTAGE (ramstage) * The latter is taken care of by the generic coreboot infrastructure so - * it's up to the chipset/arch to call timestamp_init() in *one* of - * the __PRE_RAM__ stages. If multiple calls are made timestamps will be lost. + * it's up to the chipset/arch to call timestamp_init() in the former stages. */ void timestamp_init(uint64_t base); /* diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 89152fd..3e9914e 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -41,7 +41,7 @@ DECLARE_OPTIONAL_REGION(timestamp); -#if defined(__PRE_RAM__) +#if ENV_ROMSTAGE_OR_BEFORE #define USE_TIMESTAMP_REGION (REGION_SIZE(timestamp) > 0) #else #define USE_TIMESTAMP_REGION 0 @@ -58,6 +58,10 @@ */ static struct timestamp_cache timestamp_cache; +/* This points to the active timestamp_table and can change within a stage. + as CBMEM comes available. */ +static struct timestamp_table *glob_ts_table CAR_GLOBAL; + enum { TIMESTAMP_CACHE_UNINITIALIZED = 0, TIMESTAMP_CACHE_INITIALIZED, @@ -87,7 +91,7 @@ } else if (USE_TIMESTAMP_REGION) { if (REGION_SIZE(timestamp) < sizeof(*ts_cache)) BUG(); - ts_cache = car_get_var_ptr((void *)_timestamp); + ts_cache = (void *)_timestamp; } return ts_cache; @@ -128,30 +132,21 @@ static struct timestamp_table *timestamp_table_get(void) { - MAYBE_STATIC_BSS struct timestamp_table *ts_table = NULL; + struct timestamp_table *ts_table; struct timestamp_cache *ts_cache; + ts_table = car_get_var(glob_ts_table); if (ts_table != NULL) return ts_table; ts_cache = timestamp_cache_get(); + if (ts_cache) + ts_table = &ts_cache->table; - if (ts_cache == NULL) { - if (HAS_CBMEM) - ts_table = cbmem_find(CBMEM_ID_TIMESTAMP); - return ts_table; - } + if (ts_table == NULL && HAS_CBMEM) + ts_table = cbmem_find(CBMEM_ID_TIMESTAMP); - /* Cache is required. */ - if (ts_cache->cache_state != TIMESTAMP_CACHE_NOT_NEEDED) - return &ts_cache->table; - - /* Cache shouldn't be used but there's no backing store. */ - if (!HAS_CBMEM) - return NULL; - - ts_table = cbmem_find(CBMEM_ID_TIMESTAMP); - + car_set_var(glob_ts_table, ts_table); return ts_table; } @@ -237,7 +232,7 @@ uint32_t i; struct timestamp_cache *ts_cache; struct timestamp_table *ts_cache_table; - struct timestamp_table *ts_cbmem_table = NULL; + struct timestamp_table *ts_cbmem_table; if (!timestamp_should_run()) return; @@ -270,6 +265,7 @@ if (ts_cbmem_table == NULL) { printk(BIOS_ERR, "ERROR: No timestamp table allocated\n"); + car_set_var(glob_ts_table, ts_cbmem_table); return; } @@ -309,6 +305,7 @@ ts_cbmem_table->tick_freq_mhz = timestamp_tick_freq_mhz(); /* Cache no longer required. */ + car_set_var(glob_ts_table, ts_cbmem_table); ts_cache_table->num_entries = 0; ts_cache->cache_state = TIMESTAMP_CACHE_NOT_NEEDED; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35032 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87370f62db23318069b6fd56ba0d1171d619cb8a Gerrit-Change-Number: 35032 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

6 25

Change in coreboot[master]: src: Remobe unneeded include <arch/interrupt.h>
by HAOUAS Elyes (Code Review) 11 Sep '19

11 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34933 ) Change subject: src: Remobe unneeded include <arch/interrupt.h> ...................................................................... src: Remobe unneeded include <arch/interrupt.h> Change-Id: I3323d25b72dab2f9bc8a575ba41faf059ee1ffc4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/intel/gma/intel_ddi.c M src/include/device/azalia_device.h M src/mainboard/apple/macbook21/mainboard.c M src/mainboard/google/beltino/mainboard.c M src/mainboard/google/butterfly/mainboard.c M src/mainboard/google/parrot/mainboard.c M src/mainboard/google/slippy/mainboard.c M src/mainboard/google/stout/mainboard.c M src/mainboard/intel/baskingridge/mainboard.c M src/mainboard/intel/bayleybay_fsp/mainboard.c M src/mainboard/intel/camelbackmountain_fsp/mainboard.c M src/mainboard/intel/emeraldlake2/mainboard.c M src/mainboard/intel/wtm2/mainboard.c M src/mainboard/kontron/986lcd-m/mainboard.c M src/mainboard/packardbell/ms2290/mainboard.c M src/mainboard/roda/rk886ex/mainboard.c M src/mainboard/samsung/lumpy/mainboard.c M src/mainboard/siemens/mc_bdx1/mainboard.c M src/mainboard/siemens/mc_tcu3/mainboard.c 19 files changed, 0 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/34933/1 diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index 471a5d2..3ab0022 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -33,7 +33,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <arch/acpi.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <smbios.h> #include <device/pci.h> diff --git a/src/include/device/azalia_device.h b/src/include/device/azalia_device.h index 343e261..cbc5b4e 100644 --- a/src/include/device/azalia_device.h +++ b/src/include/device/azalia_device.h @@ -19,7 +19,6 @@ #include <types.h> #include <arch/acpi.h> #include <device/mmio.h> -#include <arch/interrupt.h> #include <device/device.h> void azalia_audio_init(struct device *dev); diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index 798fc12..52b4f04 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -18,7 +18,6 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <arch/interrupt.h> #include <northbridge/intel/i945/i945.h> #include <arch/acpigen.h> #include <drivers/intel/gma/int15.h> diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index 7bda2f6..fd74a6e 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <arch/acpi.h> #include <arch/io.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <device/device.h> #include <device/pci_def.h> diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index c298689..067ea4e 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -24,7 +24,6 @@ #include <fmap.h> #include <arch/acpi.h> #include <arch/io.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include "onboard.h" #include "ec.h" diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 8c3ad63..533eb23 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -21,7 +21,6 @@ #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> #include <arch/io.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include "onboard.h" #include "ec.h" diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index b98fc8a..e40d722 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -22,7 +22,6 @@ #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> #include <arch/io.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <southbridge/intel/lynxpoint/pch.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c index 05de8cb..ac35602 100644 --- a/src/mainboard/google/stout/mainboard.c +++ b/src/mainboard/google/stout/mainboard.c @@ -20,7 +20,6 @@ #include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <southbridge/intel/bd82x6x/pch.h> #include <device/pci.h> diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index 49e66bf..6b10bb4 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -21,7 +21,6 @@ #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> #include <arch/io.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <southbridge/intel/lynxpoint/pch.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/bayleybay_fsp/mainboard.c b/src/mainboard/intel/bayleybay_fsp/mainboard.c index 16c1844..991e851a 100644 --- a/src/mainboard/intel/bayleybay_fsp/mainboard.c +++ b/src/mainboard/intel/bayleybay_fsp/mainboard.c @@ -21,7 +21,6 @@ #if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> /* diff --git a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c index ee9f36e..4bd71bf 100644 --- a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c +++ b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c @@ -21,7 +21,6 @@ #if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> /* diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index d07da83..848f6de 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -20,7 +20,6 @@ #include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <southbridge/intel/bd82x6x/pch.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index 4bfd039..21321ac 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -21,7 +21,6 @@ #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> #include <arch/io.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c index 73d5997..85b704e 100644 --- a/src/mainboard/kontron/986lcd-m/mainboard.c +++ b/src/mainboard/kontron/986lcd-m/mainboard.c @@ -21,7 +21,6 @@ #include <drivers/intel/gma/int15.h> #include <pc80/mc146818rtc.h> #include <arch/io.h> -#include <arch/interrupt.h> /* Hardware Monitor */ diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 785e6e8..508488a 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -25,7 +25,6 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <ec/acpi/ec.h> #include <drivers/intel/gma/int15.h> -#include <arch/interrupt.h> #include <pc80/keyboard.h> #include <cpu/x86/lapic.h> #include <device/pci.h> diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c index 91c11d5..922eba2 100644 --- a/src/mainboard/roda/rk886ex/mainboard.c +++ b/src/mainboard/roda/rk886ex/mainboard.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <device/device.h> #include <arch/io.h> -#include <arch/interrupt.h> #include <drivers/intel/gma/int15.h> #include <ec/acpi/ec.h> diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index 8664217..893830e 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -21,7 +21,6 @@ #include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <ec/smsc/mec1308/ec.h> #include "ec.h" diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c index 2bb9852..5cef53c 100644 --- a/src/mainboard/siemens/mc_bdx1/mainboard.c +++ b/src/mainboard/siemens/mc_bdx1/mainboard.c @@ -27,7 +27,6 @@ #include <x86emu/x86emu.h> #endif #include <device/mmio.h> -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <hwilib.h> #include <i210.h> diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c index 169b04d..a50a53e 100644 --- a/src/mainboard/siemens/mc_tcu3/mainboard.c +++ b/src/mainboard/siemens/mc_tcu3/mainboard.c @@ -22,7 +22,6 @@ #if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif -#include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <hwilib.h> #include <i210.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/34933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3323d25b72dab2f9bc8a575ba41faf059ee1ffc4 Gerrit-Change-Number: 34933 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mediatek/mt8183: Use different DRAM frequencies for eMCP DDR
by Yu-Ping Wu (Code Review) 11 Sep '19

11 Sep '19

Yu-Ping Wu has uploaded a new patch set (#20) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34990 ) Change subject: mediatek/mt8183: Use different DRAM frequencies for eMCP DDR ...................................................................... mediatek/mt8183: Use different DRAM frequencies for eMCP DDR Devices using eMCP may run at a high DRAM frequency (e.g., 3600Mbps) while those with discrete DRAM can only run at 3200Mbps. This patch enables 3600Mbps for eMCP DDR for better system performance. BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test passes on Kukui Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/emi.c 1 file changed, 21 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/34990/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/34990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656 Gerrit-Change-Number: 34990 Gerrit-PatchSet: 20 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: SJ Huang <sj.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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