coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

1 participants
1442 discussions

Change in coreboot[master]: Revert "security/tpm/tss/tcg-2.0: Add multi digits support to tlcl_ex...
by Julius Werner (Code Review) 12 Sep '19

12 Sep '19

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35351 ) Change subject: Revert "security/tpm/tss/tcg-2.0: Add multi digits support to tlcl_extend()" ...................................................................... Revert "security/tpm/tss/tcg-2.0: Add multi digits support to tlcl_extend()" This reverts commit fdb9805d6884090fd7bf62dbdf9c858692e55fb4. CB:33252 wasn't reviewed by a TPM maintainer and breaks abstraction layers (pulling TSS-details into TSPI, completely changing interpretation of the arguments to tlcl_extend() based on TSS version). It's also not clear why it was implemented the way it was (should have been much easier and cleaner ways to achieve the same thing). Since the author is not reacting, let's revert it for now. It can be cleaned up and resubmitted later. Change-Id: Ice44f55c75a0acc07794fe41c757a7bca75406eb --- M src/security/tpm/tspi/tspi.c M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_structures.h 3 files changed, 13 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/35351/1 diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index e64e04f..4698a4d 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -4,7 +4,6 @@ * Copyright (c) 2013 The Chromium OS Authors. All rights reserved. * Copyright 2017 Facebook Inc. * Copyright 2018 Siemens AG - * Copyright 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,7 +20,6 @@ #include <security/tpm/tspi.h> #include <security/tpm/tss.h> #include <stdlib.h> -#include <string.h> #if CONFIG(VBOOT) #include <vb2_api.h> #include <vb2_sha.h> @@ -211,28 +209,7 @@ if (!digest) return TPM_E_IOERROR; -#if CONFIG(TPM2) - TPML_DIGEST_VALUES tpml_digests; - - tpml_digests.count = 1; - switch (digest_algo) { - case VB2_HASH_SHA1: - tpml_digests.digests[0].hashAlg = TPM_ALG_SHA1; - memcpy(tpml_digests.digests[0].digest.sha1, - digest, SHA1_DIGEST_SIZE); - break; - case VB2_HASH_SHA256: - tpml_digests.digests[0].hashAlg = TPM_ALG_SHA256; - memcpy(tpml_digests.digests[0].digest.sha256, - digest, SHA256_DIGEST_SIZE); - break; - default: - return TPM_E_IOERROR; - } - result = tlcl_extend(pcr, (uint8_t *)&tpml_digests, NULL); -#else result = tlcl_extend(pcr, digest, NULL); -#endif if (result != TPM_SUCCESS) return result; diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index d9deba5..16e40fe 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -127,68 +127,24 @@ } /* - * The caller will provide the digest in a 32 byte buffer + * The caller will provide the digest in a 32 byte buffer, let's consider it a + * sha256 digest. */ uint32_t tlcl_extend(int pcr_num, const uint8_t *in_digest, uint8_t *out_digest) { struct tpm2_pcr_extend_cmd pcr_ext_cmd; struct tpm2_response *response; - int i; - TPML_DIGEST_VALUES *tpml_digests; pcr_ext_cmd.pcrHandle = HR_PCR + pcr_num; - tpml_digests = (TPML_DIGEST_VALUES *)in_digest; - pcr_ext_cmd.digests.count = tpml_digests->count; - - for (i = 0; i < tpml_digests->count ; i++) { - pcr_ext_cmd.digests.digests[i].hashAlg = - tpml_digests->digests[i].hashAlg; - switch (tpml_digests->digests[i].hashAlg) { - case TPM_ALG_SHA1: - memcpy(pcr_ext_cmd.digests.digests[i].digest.sha1, - tpml_digests->digests[i].digest.sha1, - SHA1_DIGEST_SIZE); - break; - case TPM_ALG_SHA256: - memcpy(pcr_ext_cmd.digests.digests[i].digest.sha256, - tpml_digests->digests[i].digest.sha256, - SHA256_DIGEST_SIZE); - break; - case TPM_ALG_SHA384: - memcpy(pcr_ext_cmd.digests.digests[i].digest.sha384, - tpml_digests->digests[i].digest.sha384, - SHA384_DIGEST_SIZE); - break; - case TPM_ALG_SHA512: - memcpy(pcr_ext_cmd.digests.digests[i].digest.sha512, - tpml_digests->digests[i].digest.sha512, - SHA512_DIGEST_SIZE); - break; - case TPM_ALG_SM3_256: - memcpy(pcr_ext_cmd.digests.digests[i].digest.sm3_256, - tpml_digests->digests[i].digest.sm3_256, - SM3_256_DIGEST_SIZE); - break; - } - } + pcr_ext_cmd.digests.count = 1; + pcr_ext_cmd.digests.digests[0].hashAlg = TPM_ALG_SHA256; + memcpy(pcr_ext_cmd.digests.digests[0].digest.sha256, in_digest, + sizeof(pcr_ext_cmd.digests.digests[0].digest.sha256)); response = tpm_process_command(TPM2_PCR_Extend, &pcr_ext_cmd); - /* - * Check if we are invalidating the pcrs, ignore the error if this is - * the case - */ - if ((tpml_digests->count == 1) && - (tpml_digests->digests[0].hashAlg == TPM_ALG_ERROR) && - response && (response->hdr.tpm_code & ~TPM_RC_N_MASK) == - (TPM_RC_P | TPM_RC_HASH)) { - printk(BIOS_SPEW, "%s: TPM_RC_HASH returned this is" - " expected\n", __func__); - return TPM_SUCCESS; - } - - printk(BIOS_INFO, "%s: response is 0x%x\n", + printk(BIOS_INFO, "%s: response is %x\n", __func__, response ? response->hdr.tpm_code : -1); if (!response || response->hdr.tpm_code) return TPM_E_IOERROR; diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 1530613..6a017bbb 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -97,12 +97,6 @@ space is defined by the lower 16 bits. */ #define TPM_CC_VENDOR_BIT_MASK 0x20000000 -/* Table 15 - TPM_RC Constants (Actions) */ -#define RC_FMT1 (TPM_RC)(0x080) -#define TPM_RC_HASH (TPM_RC)(RC_FMT1 + 0x003) -#define TPM_RC_P (TPM_RC)(0x040) -#define TPM_RC_N_MASK (TPM_RC)(0xF00) - /* Startup values. */ #define TPM_SU_CLEAR 0 #define TPM_SU_STATE 1 @@ -317,13 +311,12 @@ TPM2B b; } TPM2B_MAX_NV_BUFFER; -/* Table 66 - TPMU_HA Union */ +/* + * This is a union, but as of now we support just one digest - sha256, so + * there is just one element. + */ typedef union { - uint8_t sha1[SHA1_DIGEST_SIZE]; - uint8_t sha256[SHA256_DIGEST_SIZE]; - uint8_t sm3_256[SM3_256_DIGEST_SIZE]; - uint8_t sha384[SHA384_DIGEST_SIZE]; - uint8_t sha512[SHA512_DIGEST_SIZE]; + uint8_t sha256[SHA256_DIGEST_SIZE]; } TPMU_HA; typedef struct { @@ -331,10 +324,9 @@ TPMU_HA digest; } TPMT_HA; -/* Table 96 -- TPML_DIGEST_VALUES Structure <I/O> */ typedef struct { uint32_t count; - TPMT_HA digests[HASH_COUNT]; + TPMT_HA digests[1]; /* Limit max number of hashes to 1. */ } TPML_DIGEST_VALUES; struct nv_read_response { -- To view, visit https://review.coreboot.org/c/coreboot/+/35351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice44f55c75a0acc07794fe41c757a7bca75406eb Gerrit-Change-Number: 35351 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: [TEST-ONLY] Distinguish SKU1 and 2 for eMMC and SSD respectively
by Peichao Li (Code Review) 12 Sep '19

12 Sep '19

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35204 ) Change subject: [TEST-ONLY] Distinguish SKU1 and 2 for eMMC and SSD respectively ...................................................................... [TEST-ONLY] Distinguish SKU1 and 2 for eMMC and SSD respectively 1. SKU1 for eMMC 2. SKU2 for SSD BUG=b:132918661 TEST=Verify SSD is disabled when SKU ID = 2/4/21/22 Signed-off-by: Peichao Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I827e6f1420801d43e0eb4708b8b8ad1692ef7e9f --- M src/mainboard/google/hatch/variants/akemi/Makefile.inc M src/mainboard/google/hatch/variants/akemi/gpio.c A src/mainboard/google/hatch/variants/akemi/variant.c 3 files changed, 206 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/35204/1 diff --git a/src/mainboard/google/hatch/variants/akemi/Makefile.inc b/src/mainboard/google/hatch/variants/akemi/Makefile.inc index 2f590bf..6cabe91 100644 --- a/src/mainboard/google/hatch/variants/akemi/Makefile.inc +++ b/src/mainboard/google/hatch/variants/akemi/Makefile.inc @@ -21,3 +21,4 @@ bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += variant.c diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index 5a58839..4fa443f 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -19,6 +19,148 @@ #include <commonlib/helpers.h> #include <console/console.h> +static const struct pad_config ssd_sku_gpio_table[] = { +/* A0 : NC */ + PAD_NC(GPP_A0, NONE), + /* A6 : NC */ + PAD_NC(GPP_A6, NONE), + /* A8 : NC */ + PAD_NC(GPP_A8, NONE), + /* A10 : NC */ + PAD_NC(GPP_A10, NONE), + /* A11 : NC */ + PAD_NC(GPP_A11, NONE), + /* A12 : NC */ + PAD_NC(GPP_A12, NONE), + /* A18 : NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : NC */ + PAD_NC(GPP_A19, NONE), + /* A22 : NC */ + PAD_NC(GPP_A22, NONE), + /* A23 : NC */ + PAD_NC(GPP_A23, NONE), + /* B20 : NC */ + PAD_NC(GPP_B20, NONE), + /* B21 : NC */ + PAD_NC(GPP_B21, NONE), + /* B22 : NC */ + PAD_NC(GPP_B22, NONE), + /* C11 : NC */ + PAD_NC(GPP_C11, NONE), + /* C15 : NC */ + PAD_NC(GPP_C15, NONE), + /* F1 : NC */ + PAD_NC(GPP_F1, NONE), + /* F3 : MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F10 : MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* F11 : NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : NC */ + PAD_NC(GPP_F12, NONE), + /* F13 : NC */ + PAD_NC(GPP_F13, NONE), + /* F14 : NC */ + PAD_NC(GPP_F14, NONE), + /* F15 : NC */ + PAD_NC(GPP_F15, NONE), + /* F16 : NC */ + PAD_NC(GPP_F16, NONE), + /* F17 : NC */ + PAD_NC(GPP_F17, NONE), + /* F18 : NC */ + PAD_NC(GPP_F18, NONE), + /* F19 : NC */ + PAD_NC(GPP_F19, NONE), + /* F20 : NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : NC */ + PAD_NC(GPP_F22, NONE), + /* H6 : NC */ + PAD_NC(GPP_H6, NONE), + /* H7 : NC */ + PAD_NC(GPP_H7, NONE), + /* H19 : MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H22 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), +}; + +static const struct pad_config emmc_sku_gpio_table[] = { + /* A0 : NC */ + PAD_NC(GPP_A0, NONE), + /* A6 : NC */ + PAD_NC(GPP_A6, NONE), + /* A8 : NC */ + PAD_NC(GPP_A8, NONE), + /* A10 : NC */ + PAD_NC(GPP_A10, NONE), + /* A11 : NC */ + PAD_NC(GPP_A11, NONE), + /* A12 : NC */ + PAD_NC(GPP_A12, NONE), + /* A18 : NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : NC */ + PAD_NC(GPP_A19, NONE), + /* A22 : NC */ + PAD_NC(GPP_A22, NONE), + /* A23 : NC */ + PAD_NC(GPP_A23, NONE), + /* B20 : NC */ + PAD_NC(GPP_B20, NONE), + /* B21 : NC */ + PAD_NC(GPP_B21, NONE), + /* B22 : NC */ + PAD_NC(GPP_B22, NONE), + /* C11 : NC */ + PAD_NC(GPP_C11, NONE), + /* C15 : NC */ + PAD_NC(GPP_C15, NONE), + /* F1 : NC */ + PAD_NC(GPP_F1, NONE), + /* F3 : MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F10 : MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* F11 : EMMC_CMD ==> EMMC_CMD */ + PAD_CFG_NF(GPP_F11,UP_20K, DEEP, NF1), + /* F12 : EMMC_DATA0 ==> EMMC_DAT0 */ + PAD_CFG_NF(GPP_F12,UP_20K, DEEP, NF1), + /* F13 : EMMC_DATA1 ==> EMMC_DAT1 */ + PAD_CFG_NF(GPP_F13,UP_20K, DEEP, NF1), + /* F14 : EMMC_DATA2 ==> EMMC_DAT2 */ + PAD_CFG_NF(GPP_F14,UP_20K, DEEP, NF1), + /* F15 : EMMC_DATA3 ==> EMMC_DAT3 */ + PAD_CFG_NF(GPP_F15,UP_20K, DEEP, NF1), + /* F16 : EMMC_DATA4 ==> EMMC_DAT4 */ + PAD_CFG_NF(GPP_F16,UP_20K, DEEP, NF1), + /* F17 : EMMC_DATA5 ==> EMMC_DAT5 */ + PAD_CFG_NF(GPP_F17,UP_20K, DEEP, NF1), + /* F18 : EMMC_DATA6 ==> EMMC_DAT6 */ + PAD_CFG_NF(GPP_F18,UP_20K, DEEP, NF1), + /* F19 : EMMC_DATA7 ==> EMMC_DAT7 */ + PAD_CFG_NF(GPP_F19,UP_20K, DEEP, NF1), + /* F20 : EMMC_RCLK ==> EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, DN_20K, DEEP, NF1), + /* F21 : EMMC_CLK ==> EMMC_CLK */ + PAD_CFG_NF(GPP_F21, DN_20K, DEEP, NF1), + /* F22 : EMMC_RESET# ==> EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* H6 : NC */ + PAD_NC(GPP_H6, NONE), + /* H7 : NC */ + PAD_NC(GPP_H7, NONE), + /* H19 : MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H22 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), +}; + static const struct pad_config gpio_table[] = { /* A0 : NC */ PAD_NC(GPP_A0, NONE), @@ -92,6 +234,17 @@ const struct pad_config *override_gpio_table(size_t *num) { + uint32_t sku_id = get_board_sku(); + /* For SSD SKU */ + if (sku_id == 2) { + *num = ARRAY_SIZE(ssd_sku_gpio_table); + return ssd_sku_gpio_table; + } + /* For eMMC SKU */ + if (sku_id == 1) { + *num = ARRAY_SIZE(emmc_sku_gpio_table); + return emmc_sku_gpio_table; + } *num = ARRAY_SIZE(gpio_table); return gpio_table; } @@ -128,30 +281,6 @@ PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), /* F2 : MEM_CH_SEL */ PAD_CFG_GPI(GPP_F2, NONE, PLTRST), - /* F11 : EMMC_CMD ==> EMMC_CMD */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), - /* F12 : EMMC_DATA0 ==> EMMC_DAT0 */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - /* F13 : EMMC_DATA1 ==> EMMC_DAT1 */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - /* F14 : EMMC_DATA2 ==> EMMC_DAT2 */ - PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), - /* F15 : EMMC_DATA3 ==> EMMC_DAT3 */ - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - /* F16 : EMMC_DATA4 ==> EMMC_DAT4 */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), - /* F17 : EMMC_DATA5 ==> EMMC_DAT5 */ - PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), - /* F18 : EMMC_DATA6 ==> EMMC_DAT6 */ - PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), - /* F19 : EMMC_DATA7 ==> EMMC_DAT7 */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* F20 : EMMC_RCLK ==> EMMC_RCLK */ - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - /* F21 : EMMC_CLK ==> EMMC_CLK */ - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - /* F22 : EMMC_RESET# ==> EMMC_RST_L */ - PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), }; const struct pad_config *variant_early_gpio_table(size_t *num) diff --git a/src/mainboard/google/hatch/variants/akemi/variant.c b/src/mainboard/google/hatch/variants/akemi/variant.c new file mode 100644 index 0000000..1c4e420 --- /dev/null +++ b/src/mainboard/google/hatch/variants/akemi/variant.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <soc/pci_devs.h> +#include <ec/google/chromeec/ec.h> +void variant_devtree_update(void) +{ + uint32_t sku_id; + struct device *emmc_host; + + struct device *ssd_host; + config_t *cfg = config_of_path(SA_DEVFN_ROOT); + emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC); + ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA); + + + /* SKU ID 2 doesn't have a eMMC device, hence disable it. */ + sku_id = get_board_sku(); + if (sku_id == 2) { + if (emmc_host == NULL) + return; + emmc_host->enabled = 0; + cfg->ScsEmmcHs400Enabled = 0; + } + + /* SKU ID 1 doesn't have a SSD device, hence disable it. */ + + if (sku_id == 1) { + if (ssd_host == NULL) + return; + ssd_host->enabled = 0; + cfg->SataSalpSupport = 0; + cfg->SataMode = 0; + cfg->SataPortsEnable[1] = 0; + cfg->SataPortsDevSlp[1] = 0; + cfg->satapwroptimize = 0; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I827e6f1420801d43e0eb4708b8b8ad1692ef7e9f Gerrit-Change-Number: 35204 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

7 50

Change in coreboot[master]: futility: Use HOSTPKGCONFIG for host PKG_CONFIG
by Patrick Georgi (Code Review) 11 Sep '19

11 Sep '19

Hello Manoj Gupta, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35316 to review the following change. Change subject: futility: Use HOSTPKGCONFIG for host PKG_CONFIG ...................................................................... futility: Use HOSTPKGCONFIG for host PKG_CONFIG futility is built for the host. However, when cross-compiling, the target's pkg-config is called to get the library paths which can add paths from the cross-compilation tree instead of host. e.g. /build/elm/usr/bin/pkg-config gets called instead of /usr/bin/pkg-config . /build/elm/usr/bin/pkg-config adds the paths specific to the cross-compilation target e.g. /build/elm/usr/lib instead of /usr/lib. This causes linker to complain that files in library paths do not match the architecture. BFD produces a warning while LLD errors out. Fix this by passing PKG_CONFIG from host when building futility. BUG=chromium:999217 TEST=coreboot builds BRANCH=None Cq-Depend: chromium:1778519 Change-Id: Id3afbf25001cf3daa72f36a290c93136cf9f162d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/futility/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/35316/1 diff --git a/util/futility/Makefile.inc b/util/futility/Makefile.inc index 782953e..87764a7 100644 --- a/util/futility/Makefile.inc +++ b/util/futility/Makefile.inc @@ -5,6 +5,7 @@ unset CFLAGS LDFLAGS; $(MAKE) -C $(VBOOT_SOURCE) \ BUILD=$(abspath $@/../..) \ CC="$(HOSTCC)" \ + PKG_CONFIG="$(HOSTPKGCONFIG)" \ V=$(V) \ $(abspath $@) -- To view, visit https://review.coreboot.org/c/coreboot/+/35316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3afbf25001cf3daa72f36a290c93136cf9f162d Gerrit-Change-Number: 35316 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Manoj Gupta <manojgupta(a)google.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: intel/fsp2_0: Add help text for FSP_TEMP_RAM_SIZE Kconfig
by Subrata Banik (Code Review) 11 Sep '19

11 Sep '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35301 ) Change subject: intel/fsp2_0: Add help text for FSP_TEMP_RAM_SIZE Kconfig ...................................................................... intel/fsp2_0: Add help text for FSP_TEMP_RAM_SIZE Kconfig BUG=b:140268415 Change-Id: Ic1463181b4a9dca136d00cb2f7e3cce4f7e57bd6 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/drivers/intel/fsp2_0/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/35301/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 541ec47..d0d582f 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -156,6 +156,11 @@ hex default 0x10000 depends on FSP_USES_CB_STACK + help + The amount of anticipated heap usage in CAR by FSP to setup HOB. + This configuration is applicable with FSP specification using single + stack implementation. + Sync this value with Platform FSP integration guide recommendation. config VERIFY_HOBS bool "Verify the FSP hand-off-blocks" -- To view, visit https://review.coreboot.org/c/coreboot/+/35301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1463181b4a9dca136d00cb2f7e3cce4f7e57bd6 Gerrit-Change-Number: 35301 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: arch/x86: Cache the TSEG region at the top of ram
by Subrata Banik (Code Review) 11 Sep '19

11 Sep '19

Hello Kyösti Mälkki, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34995 to review the following change. Change subject: arch/x86: Cache the TSEG region at the top of ram ...................................................................... arch/x86: Cache the TSEG region at the top of ram This patch helps to save additional ~6ms of booting time in normal and s3 resume on CML-hatch. Change-Id: I59432c02e04af1b931d77de3f6652b0327ca82bb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/postcar_loader.c 1 file changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/34995/1 diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index bceed6c..408d155 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -20,6 +20,7 @@ #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/x86/smm.h> #include <program_loading.h> #include <rmodule.h> #include <romstage_handoff.h> @@ -149,6 +150,23 @@ set_var_mtrr(mtrr, base, size, MTRR_TYPE_WRPROT); } +/* + * Cache the TSEG region at the top of ram. This region is + * not restricted to SMM mode until SMM has been relocated. + * By setting the region to cacheable it provides faster access + * when relocating the SMM handler as well as using the TSEG + * region for other purposes. + */ +static void enable_tseg_cache(struct postcar_frame *pcf) +{ + uintptr_t smm_base; + size_t smm_size; + + smm_region(&smm_base, &smm_size); + postcar_frame_add_mtrr(pcf, smm_base, smm_size, + MTRR_TYPE_WRBACK); +} + void postcar_frame_setup_top_of_dram_usage(struct postcar_frame *pcf, uintptr_t addr, size_t size, int type) { @@ -159,6 +177,9 @@ */ if (!acpi_is_wakeup_s3()) enable_top_of_dram_cache(addr, size); + + enable_tseg_cache(pcf); + postcar_frame_add_mtrr(pcf, addr, size, type); } -- To view, visit https://review.coreboot.org/c/coreboot/+/34995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59432c02e04af1b931d77de3f6652b0327ca82bb Gerrit-Change-Number: 34995 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 49

Change in coreboot[master]: mb/google/hatch: Create dratini variant
by Chen Wisley (Code Review) 11 Sep '19

11 Sep '19

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35285 ) Change subject: mb/google/hatch: Create dratini variant ...................................................................... mb/google/hatch: Create dratini variant Create dratini variant BUG=none TEST=emerge-hatch coreboot, and boot into chromeos on proto board Change-Id: Ied1240d1be831568e4ab4695b893c3f48821f68b Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/dratini/Makefile.inc A src/mainboard/google/hatch/variants/dratini/gpio.c A src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/dratini/include/variant/ec.h A src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h A src/mainboard/google/hatch/variants/dratini/overridetree.cb 8 files changed, 371 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/35285/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 5c7c267..c4c9146 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -72,6 +72,7 @@ string depends on CHROMEOS default "AKEMI TEST 4326" if BOARD_GOOGLE_AKEMI + default "DRATINI TEST 4583" if BOARD_GOOGLE_DRATINI default "HATCH TEST 1823" if BOARD_GOOGLE_HATCH default "HELIOS TEST 0878" if BOARD_GOOGLE_HELIOS default "KINDRED TEST 2636" if BOARD_GOOGLE_KINDRED @@ -88,6 +89,7 @@ config MAINBOARD_PART_NUMBER string default "Akemi" if BOARD_GOOGLE_AKEMI + default "Dratini" if BOARD_GOOGLE_DRATINI default "Hatch" if BOARD_GOOGLE_HATCH default "Helios" if BOARD_GOOGLE_HELIOS default "Kindred" if BOARD_GOOGLE_KINDRED @@ -112,6 +114,7 @@ config VARIANT_DIR string default "akemi" if BOARD_GOOGLE_AKEMI + default "dratini" if BOARD_GOOGLE_DRATINI default "hatch" if BOARD_GOOGLE_HATCH default "helios" if BOARD_GOOGLE_HELIOS default "kindred" if BOARD_GOOGLE_KINDRED diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 85037d9..01b6ead 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -6,6 +6,12 @@ select BOARD_ROMSIZE_KB_16384 select SOC_INTEL_COMETLAKE +config BOARD_GOOGLE_DRATINI + bool "-> Dratini" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 + select SOC_INTEL_COMETLAKE + config BOARD_GOOGLE_HATCH bool "-> Hatch" select BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/variants/dratini/Makefile.inc b/src/mainboard/google/hatch/variants/dratini/Makefile.inc new file mode 100644 index 0000000..d82d797 --- /dev/null +++ b/src/mainboard/google/hatch/variants/dratini/Makefile.inc @@ -0,0 +1,25 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = 4G_2400 # 0b000 +SPD_SOURCES += empty_ddr4 # 0b001 +SPD_SOURCES += 8G_2400 # 0b010 +SPD_SOURCES += 8G_2666 # 0b011 +SPD_SOURCES += 16G_2400 # 0b100 +SPD_SOURCES += 16G_2666 # 0b101 +SPD_SOURCES += 8G_3200 # 0b110 +SPD_SOURCES += 16G_3200 # 0b111 + +bootblock-y += gpio.c +ramstage-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/dratini/gpio.c b/src/mainboard/google/hatch/variants/dratini/gpio.c new file mode 100644 index 0000000..003b7d1 --- /dev/null +++ b/src/mainboard/google/hatch/variants/dratini/gpio.c @@ -0,0 +1,138 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +static const struct pad_config gpio_table[] = { + /* A0 : NC */ + PAD_NC(GPP_A0, NONE), + /* A6 : NC */ + PAD_NC(GPP_A6, NONE), + /* A8 : NC */ + PAD_NC(GPP_A8, NONE), + /* A10 : NC */ + PAD_NC(GPP_A10, NONE), + /* A18 : NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : NC */ + PAD_NC(GPP_A19, NONE), + /* C15 : NC */ + PAD_NC(GPP_C15, NONE), + /* F1 : NC */ + PAD_NC(GPP_F1, NONE), + /* F3 : MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F10 : MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* F11 : EMMC_CMD ==> EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 ==> EMMC_DAT0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 ==> EMMC_DAT1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 ==> EMMC_DAT2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 ==> EMMC_DAT3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 ==> EMMC_DAT4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 ==> EMMC_DAT5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 ==> EMMC_DAT6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 ==> EMMC_DAT7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK ==> EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK ==> EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RESET# ==> EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* H19 : MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H22 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ +static const struct pad_config early_gpio_table[] = { + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), + /* F11 : EMMC_CMD ==> EMMC_CMD */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* F12 : EMMC_DATA0 ==> EMMC_DAT0 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* F13 : EMMC_DATA1 ==> EMMC_DAT1 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14 : EMMC_DATA2 ==> EMMC_DAT2 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* F15 : EMMC_DATA3 ==> EMMC_DAT3 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* F16 : EMMC_DATA4 ==> EMMC_DAT4 */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : EMMC_DATA5 ==> EMMC_DAT5 */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* F18 : EMMC_DATA6 ==> EMMC_DAT6 */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* F19 : EMMC_DATA7 ==> EMMC_DAT7 */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F20 : EMMC_RCLK ==> EMMC_RCLK */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EMMC_CLK ==> EMMC_CLK */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : EMMC_RESET# ==> EMMC_RST_L */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..31f72b3 --- /dev/null +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/dratini/include/variant/ec.h b/src/mainboard/google/hatch/variants/dratini/include/variant/ec.h new file mode 100644 index 0000000..768987d --- /dev/null +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h b/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h new file mode 100644 index 0000000..92f9d41 --- /dev/null +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_H19 +#define GPIO_MEM_CONFIG_1 GPP_H22 +#define GPIO_MEM_CONFIG_2 GPP_F10 +#define GPIO_MEM_CONFIG_3 GPP_F3 + +#endif diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb new file mode 100644 index 0000000..b2ec3d7 --- /dev/null +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -0,0 +1,135 @@ +chip soc/intel/cannonlake + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | FP MCU | + #| I2C0 | Touchpad | + #| I2C1 | Touch screen | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + # Enable eMMC HS400 + register "ScsEmmcHs400Enabled" = "1" + + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "wake" = "GPE0_DW0_21" + register "probed" = "1" + device i2c 15 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "has_power_resource" = "1" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "stop_off_delay_ms" = "5" + device i2c 10 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" + register "key.wake" = "GPE0_DW0_08" + register "key.wakeup_event_action" = "EV_ACT_ASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1a.0 on end # eMMC + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" + device spi 1 on end + end # FPMCU + end # GSPI #1 + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/35285 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied1240d1be831568e4ab4695b893c3f48821f68b Gerrit-Change-Number: 35285 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: mb/google/drallion: enable Elan and Melfas touch panel
by EricR Lai (Code Review) 11 Sep '19

11 Sep '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35305 ) Change subject: mb/google/drallion: enable Elan and Melfas touch panel ...................................................................... mb/google/drallion: enable Elan and Melfas touch panel Drallion uses the same touch panel as Sarien. Copy the deivce from Sarien. BUG=b:140415892 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I8e6d2dcf4bd2ed2325137a05811af03692d40342 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/35305/1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index e96f9d7..d8ef7a9 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -332,6 +332,37 @@ register "hid_desc_reg_offset" = "0x1" device i2c 0A on end end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN900C"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "generic.reset_delay_ms" = "10" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "generic.enable_delay_ms" = "55" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + register "generic.device_present_gpio" = "GPP_B4" + register "generic.device_present_gpio_invert" = "1" + device i2c 10 on end + end + chip drivers/i2c/generic + register "hid" = ""MLFS0000"" + register "desc" = ""Melfas Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "reset_delay_ms" = "10" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "enable_delay_ms" = "55" + register "has_power_resource" = "1" + register "device_present_gpio" = "GPP_B4" + register "device_present_gpio_invert" = "1" + device i2c 34 on end + end end # I2C #0 device pci 15.1 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/35305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e6d2dcf4bd2ed2325137a05811af03692d40342 Gerrit-Change-Number: 35305 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: superio/common: fix generic ssdt
by Michael Niewöhner (Code Review) 11 Sep '19

11 Sep '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35294 ) Change subject: superio/common: fix generic ssdt ...................................................................... superio/common: fix generic ssdt ITR2 is specified twice here, which leads to the following error message in Linux: [ 0.263591] ACPI BIOS Error (bug): Failure creating named object [\_SB.PCI0.LPCB.SIO0.ITR2], AE_ALREADY_EXISTS (20190509/dsfield-633) By comparing multiple dsdt/ssdt's I was able to guess how this (hopefully) should look like instead. WARNING: This is based on a guess! Please verify this! Change-Id: I4f3307d0992fcf5ad192f412c2bd15d02572a6b0 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/superio/common/generic.c 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/35294/1 diff --git a/src/superio/common/generic.c b/src/superio/common/generic.c index bffa9f3..1f8063f 100644 --- a/src/superio/common/generic.c +++ b/src/superio/common/generic.c @@ -115,11 +115,9 @@ FIELDLIST_OFFSET(0x70), FIELDLIST_NAMESTR("INTR", 4), FIELDLIST_OFFSET(0x71), - FIELDLIST_NAMESTR("INTT", 2), + FIELDLIST_NAMESTR("INTT", 4), FIELDLIST_OFFSET(0x72), - FIELDLIST_NAMESTR("ITR2", 4), - FIELDLIST_OFFSET(0x73), - FIELDLIST_NAMESTR("ITR2", 2), + FIELDLIST_NAMESTR("INT1", 8), FIELDLIST_OFFSET(0x74), FIELDLIST_NAMESTR("DMCH", 8), FIELDLIST_OFFSET(0xE0), -- To view, visit https://review.coreboot.org/c/coreboot/+/35294 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f3307d0992fcf5ad192f412c2bd15d02572a6b0 Gerrit-Change-Number: 35294 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: emulation/qemu-i440fx/northbridge.c: Fix minor whitespace
by Name of user not set (Code Review) 11 Sep '19

11 Sep '19

Name of user not set #1002476 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35311 ) Change subject: emulation/qemu-i440fx/northbridge.c: Fix minor whitespace ...................................................................... emulation/qemu-i440fx/northbridge.c: Fix minor whitespace Change-Id: Ifc3825119c8463a7d17a5c162330f49612ae1b85 Signed-off-by: Himanshu Sahdev <himanshusah(a)hcl.com> --- M src/mainboard/emulation/qemu-i440fx/northbridge.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/35311/1 diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 852800d..0bff4d7 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -72,7 +72,7 @@ for (i = 0; i < f.size / sizeof(*list); i++) { switch (list[i].type) { case 1: /* RAM */ - printk(BIOS_DEBUG, "QEMU: e820/ram: 0x%08llx +0x%08llx\n", + printk(BIOS_DEBUG, "QEMU: e820/ram: 0x%08llx + 0x%08llx\n", list[i].address, list[i].length); if (list[i].address == 0) { tomk = list[i].length / 1024; -- To view, visit https://review.coreboot.org/c/coreboot/+/35311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc3825119c8463a7d17a5c162330f49612ae1b85 Gerrit-Change-Number: 35311 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002476 Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb/asrock/h110m: Add STX variant
by Maxim Polyakov (Code Review) 11 Sep '19

11 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34904 ) Change subject: mb/asrock/h110m: Add STX variant ...................................................................... mb/asrock/h110m: Add STX variant Change-Id: If95c7ec78b8bee10ed7ae761754ba7f7d548aa55 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/Kconfig M src/mainboard/asrock/h110m/Kconfig.name M src/mainboard/asrock/h110m/Makefile.inc M src/mainboard/asrock/h110m/bootblock.c M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/asrock/h110m/include/gpio.h M src/mainboard/asrock/h110m/ramstage.c A src/mainboard/asrock/h110m/variants/dvs/gpio.c R src/mainboard/asrock/h110m/variants/dvs/hda_verb.c A src/mainboard/asrock/h110m/variants/dvs/overridetree.cb A src/mainboard/asrock/h110m/variants/stx/gpio.c A src/mainboard/asrock/h110m/variants/stx/hda_verb.c A src/mainboard/asrock/h110m/variants/stx/overridetree.cb 13 files changed, 979 insertions(+), 440 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/34904/1 diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index eebce57..1b4e263 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -1,4 +1,4 @@ -if BOARD_ASROCK_H110M_DVS +if BOARD_ASROCK_H110M_DVS || BOARD_ASROCK_H110M_STX config BOARD_SPECIFIC_OPTIONS def_bool y @@ -11,11 +11,13 @@ select INTEL_INT15 select SOC_INTEL_KABYLAKE select SKYLAKE_SOC_PCH_H + select MAINBOARD_USES_FSP2_0 select GENERIC_SPD_BIN - select SUPERIO_NUVOTON_NCT6791D - select SUPERIO_NUVOTON_NCT6791D_COM_A - select REALTEK_8168_RESET - select RT8168_SET_LED_MODE + select MAINBOARD_USES_IFD_GBE_REGION if BOARD_ASROCK_H110M_STX + select SUPERIO_NUVOTON_NCT6791D if BOARD_ASROCK_H110M_DVS + select SUPERIO_NUVOTON_NCT6791D_COM_A if BOARD_ASROCK_H110M_DVS + select REALTEK_8168_RESET if BOARD_ASROCK_H110M_DVS + select RT8168_SET_LED_MODE if BOARD_ASROCK_H110M_DVS config IRQ_SLOT_COUNT int @@ -25,9 +27,15 @@ string default "asrock/h110m" +config VARIANT_DIR + string + default "dvs" if BOARD_ASROCK_H110M_DVS + default "stx" if BOARD_ASROCK_H110M_STX + config MAINBOARD_PART_NUMBER string - default "H110M" + default "H110M-DVS" if BOARD_ASROCK_H110M_DVS + default "H110M-STX" if BOARD_ASROCK_H110M_STX config MAX_CPUS int @@ -37,6 +45,10 @@ string default "devicetree.cb" +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + config PRERAM_CBMEM_CONSOLE_SIZE hex default 0xd00 diff --git a/src/mainboard/asrock/h110m/Kconfig.name b/src/mainboard/asrock/h110m/Kconfig.name index 34c1a3c..c871b62 100644 --- a/src/mainboard/asrock/h110m/Kconfig.name +++ b/src/mainboard/asrock/h110m/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_ASROCK_H110M_DVS bool "H110M-DVS" + +config BOARD_ASROCK_H110M_STX + bool "H110M-STX" diff --git a/src/mainboard/asrock/h110m/Makefile.inc b/src/mainboard/asrock/h110m/Makefile.inc index ce6cf80..be9995e 100644 --- a/src/mainboard/asrock/h110m/Makefile.inc +++ b/src/mainboard/asrock/h110m/Makefile.inc @@ -16,8 +16,10 @@ subdirs-y += spd bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += mainboard.c ramstage-y += ramstage.c -ramstage-y += hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/h110m/bootblock.c b/src/mainboard/asrock/h110m/bootblock.c index 96ce205..d520996 100644 --- a/src/mainboard/asrock/h110m/bootblock.c +++ b/src/mainboard/asrock/h110m/bootblock.c @@ -16,22 +16,28 @@ #include <bootblock_common.h> #include <soc/gpio.h> -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct6791d/nct6791d.h> #include "include/gpio.h" +#include <superio/nuvoton/nct6791d/nct6791d.h> +#include <superio/nuvoton/common/nuvoton.h> static void early_config_superio(void) { - const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT6791D_SP1); - nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + if (CONFIG(BOARD_ASROCK_H110M_DVS)) { + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT6791D_SP1); + nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + } } static void early_config_gpio(void) { + const struct pad_config *pads; + size_t size; + /* This is a hack for FSP because it does things in MemoryInit() * which it shouldn't do. We have to prepare certain gpios here * because of the brokenness in FSP. */ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); + pads = get_early_gpio_table(&size); + gpio_configure_pads(pads, size); } void bootblock_mainboard_init(void) diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 3067ffe..9942233 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -145,119 +145,9 @@ }" register "EnableLan" = "0" - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V register "PmTimerDisabled" = "0" - # USB - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" - register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" - register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" - register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" - register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" - register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" - register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" - register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" - register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" - register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" - - # SATA - register "EnableSata" = "1" - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ \ - [0] = 1, \ - [1] = 1, \ - [2] = 1, \ - [3] = 1, \ - [4] = 1, \ - [5] = 1, \ - [6] = 1, \ - [7] = 1, \ - }" - - # PCH UART, SPI, I2C - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoPci, \ - [PchSerialIoIndexI2C1] = PchSerialIoPci, \ - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ - [PchSerialIoIndexSpi0] = PchSerialIoPci, \ - [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ - }" - - # Set params for PEG 0:1:0 - register "Peg0MaxLinkWidth" = "Peg0_x16" - # Configure PCIe clockgen in PCH - # PEG0 uses SRCCLKREQ0 and CLKSRC0 - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqNumber[0]" = "0" - register "PcieRpClkSrcNumber[0]" = "0" - - # Enable Root port 6(x1) for LAN. - register "PcieRpEnable[5]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[5]" = "1" - # Use SRCCLKREQ1# - register "PcieRpClkReqNumber[5]" = "1" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[5]" = "1" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[5]" = "1" - # Use CLK SRC 1 - register "PcieRpClkSrcNumber[5]" = "1" - - # Enable Root port 5 (x1) for PCIE slot. - register "PcieRpEnable[4]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[4]" = "1" - # Use SRCCLKREQ2# - register "PcieRpClkReqNumber[4]" = "2" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[4]" = "1" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[4]" = "1" - # Use CLK SRC 2 - register "PcieRpClkSrcNumber[4]" = "2" - # Use Hot Plug subsystem - register "PcieRpHotPlug[4]" = "1" - - # Enable Root port 7(x1) for PCIE slot. - register "PcieRpEnable[6]" = "1" - # Enable CLKREQ# - register "PcieRpClkReqSupport[6]" = "1" - # Use SRCCLKREQ3# - register "PcieRpClkReqNumber[6]" = "3" - # Enable Advanced Error Reporting - register "PcieRpAdvancedErrorReporting[6]" = "1" - # Enable Latency Tolerance Reporting Mechanism - register "PcieRpLtrEnable[6]" = "1" - # Use CLK SRC 3 - register "PcieRpClkSrcNumber[6]" = "3" - # Use Hot Plug subsystem - register "PcieRpHotPlug[6]" = "1" - - # PL2 override 91W - register "tdp_pl2_override" = "91" - # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" @@ -298,13 +188,13 @@ device pci 19.0 off end # UART #2 device pci 19.1 off end # I2C #5 device pci 19.2 off end # I2C #4 - device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.0 off end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 on end # PCI Express Port 6 - device pci 1c.6 on end # PCI Express Port 7 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 off end # PCI Express Port 10 @@ -317,70 +207,7 @@ device pci 1e.4 off end # eMMC device pci 1e.5 off end # SDIO device pci 1e.6 off end # SDCard - device pci 1f.0 on # LPC bridge - subsystemid 0x1849 0x1a43 - chip superio/nuvoton/nct6791d - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # Parallel - # global - irq 0x1c = 0x10 - irq 0x27 = 0x10 - irq 0x2a = 0x64 - # parallel port - io 0x60 = 0x0378 - irq 0x70 = 7 - drq 0x74 = 4 # No DMA - irq 0xf0 = 0x3c # Printer mode - end - device pnp 2e.2 on # UART A - io 0x60 = 0x03f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # IR - io 0x60 = 0x02f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 KBC - io 0x60 = 0x0060 - io 0x62 = 0x0064 - irq 0x70 = 1 # Keyboard - irq 0x72 = 12 # Mouse - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GPIO6 - device pnp 2e.107 off end # GPIO7 - device pnp 2e.207 off end # GPIO8 - device pnp 2e.8 off end # WDT - device pnp 2e.108 off end # GPIO0 - device pnp 2e.308 off end # GPIO base - device pnp 2e.408 off end # WDTMEM - device pnp 2e.708 off end # GPIO1 - device pnp 2e.9 off end # GPIO2 - device pnp 2e.109 off end # GPIO3 - device pnp 2e.209 off end # GPIO4 - device pnp 2e.309 off end # GPIO5 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HWM, LED - io 0x60 = 0x0290 - io 0x62 = 0 - irq 0x70 = 0 - end - device pnp 2e.d off end # BCLK, WDT2, WDT_MEM - device pnp 2e.e off end # CIR wake-up - device pnp 2e.f off end # GPIO PP/OD - device pnp 2e.14 off end # SVID, Port 80 UART - device pnp 2e.16 off end # DS5 - device pnp 2e.116 off end # DS3 - device pnp 2e.316 off end # PCHDSW - device pnp 2e.416 off end # DSWWOPT - device pnp 2e.516 off end # DS3OPT - device pnp 2e.616 off end # DSDSS - device pnp 2e.716 off end # DSPU - end # superio/nuvoton/nct6791d - chip drivers/pc80/tpm - device pnp 4e.0 on end # TPM module - end - end # LPC Interface + device pci 1f.0 on end # Chipset LPC/eSPI Controller device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller device pci 1f.3 on end # Intel HDA diff --git a/src/mainboard/asrock/h110m/include/gpio.h b/src/mainboard/asrock/h110m/include/gpio.h index 4ae9911..4cabfc5 100644 --- a/src/mainboard/asrock/h110m/include/gpio.h +++ b/src/mainboard/asrock/h110m/include/gpio.h @@ -13,260 +13,16 @@ * GNU General Public License for more details. */ -#ifndef _GPIO_DVS_H -#define _GPIO_DVS_H +#ifndef _PCH_GPIO_H +#define _PCH_GPIO_H #include <soc/gpe.h> #include <soc/gpio.h> -#define H110_PAD_DW0_DW1_CFG(val, config0, config1) \ +#define PCH_PAD_CFG(val, config0, config1) \ _PAD_CFG_STRUCT(val, config0, config1) -/* Pad configuration in ramstage. */ -static const struct pad_config gpio_table[] = { - /* GPIO Group GPP_A */ - H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ - H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ - H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ - H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ - H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ - H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ - H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ - H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ - H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ - H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ - H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN# */ - H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ - H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ - H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ - /* GPIO Group GPP_B */ - H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B4, 0x84000502, 0x00000034), /* CPU_GP3 */ - H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B12, 0x44000600, 0x0000003c), /* SLP_S0# */ - H110_PAD_DW0_DW1_CFG(GPP_B13, 0x44000600, 0x0000003d), /* PLTRST# */ - H110_PAD_DW0_DW1_CFG(GPP_B14, 0x84000600, 0x0000103e), /* SPKR */ - H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_B23, 0x84000a01, 0x00001047), /* PCHHOT# */ - /* GPIO Group GPP_C */ - H110_PAD_DW0_DW1_CFG(GPP_C0, 0x44000502, 0x00000048), /* SMBCLK */ - H110_PAD_DW0_DW1_CFG(GPP_C1, 0x44000502, 0x00000049), /* SMBDATA */ - H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C3, 0x44000502, 0x0000004b), /* SML0CLK */ - H110_PAD_DW0_DW1_CFG(GPP_C4, 0x44000502, 0x0000004c), /* SML0DATA */ - H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ - /* GPP_C6 - RESERVED */ - /* GPP_C7 - RESERVED */ - H110_PAD_DW0_DW1_CFG(GPP_C8, 0x84000502, 0x00000050), /* UART0_RXD */ - H110_PAD_DW0_DW1_CFG(GPP_C9, 0x84000600, 0x00000051), /* UART0_TXD */ - H110_PAD_DW0_DW1_CFG(GPP_C10, 0x84000600, 0x00000052), /* UART0_RTS# */ - H110_PAD_DW0_DW1_CFG(GPP_C11, 0x84000502, 0x00000053), /* UART0_CTS# */ - H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_C20, 0x84000502, 0x0000005c), /* UART2_RXD */ - H110_PAD_DW0_DW1_CFG(GPP_C21, 0x84000600, 0x0000005d), /* UART2_TXD */ - H110_PAD_DW0_DW1_CFG(GPP_C22, 0x84000600, 0x0000005e), /* UART2_RTS# */ - H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ - /* GPIO Group GPP_D */ - H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D5, 0x84000402, 0x00000065), /* I2S_SFRM */ - H110_PAD_DW0_DW1_CFG(GPP_D6, 0x84000600, 0x00000066), /* I2S_TXD */ - H110_PAD_DW0_DW1_CFG(GPP_D7, 0x84000502, 0x00000067), /* I2S_RXD */ - H110_PAD_DW0_DW1_CFG(GPP_D8, 0x84000402, 0x00000068), /* I2S_SCLK */ - H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D19, 0x84000500, 0x00003073), /* DMIC_CLK0 */ - H110_PAD_DW0_DW1_CFG(GPP_D20, 0x84000500, 0x00003074), /* DMIC_DATA0 */ - H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ - /* GPIO Group GPP_E */ - H110_PAD_DW0_DW1_CFG(GPP_E0, 0x84000502, 0x00003018), /* SATAXPCIE0 */ - H110_PAD_DW0_DW1_CFG(GPP_E1, 0x84000502, 0x00003019), /* SATAXPCIE1 */ - H110_PAD_DW0_DW1_CFG(GPP_E2, 0x84000502, 0x0000301a), /* SATAXPCIE2 */ - H110_PAD_DW0_DW1_CFG(GPP_E3, 0x84000500, 0x0000001b), /* CPU_GP0 */ - /* SATA_DEVSLP0 */ - H110_PAD_DW0_DW1_CFG(GPP_E4, 0x84000500, 0x0000001c), - /* SATA_DEVSLP1 */ - H110_PAD_DW0_DW1_CFG(GPP_E5, 0x84000500, 0x0000001d), - /* SATA_DEVSLP2 */ - H110_PAD_DW0_DW1_CFG(GPP_E6, 0x84000500, 0x0000001e), - H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_E8, 0x84000600, 0x00000020), /* SATA_LED# */ - H110_PAD_DW0_DW1_CFG(GPP_E9, 0x44000502, 0x00000021), /* USB_OC0# */ - H110_PAD_DW0_DW1_CFG(GPP_E10, 0x44000502, 0x00000022), /* USB_OC1# */ - H110_PAD_DW0_DW1_CFG(GPP_E11, 0x44000502, 0x00000023), /* USB_OC2# */ - H110_PAD_DW0_DW1_CFG(GPP_E12, 0x44000502, 0x00000024), /* USB_OC3# */ - /* GPIO Group GPP_F */ - H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F1, 0x84000502, 0x00003026), /* SATAXPCIE4 */ - H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F15, 0x44000502, 0x00000034), /* USB_OC4# */ - H110_PAD_DW0_DW1_CFG(GPP_F16, 0x44000502, 0x00000035), /* USB_OC5# */ - H110_PAD_DW0_DW1_CFG(GPP_F17, 0x44000502, 0x00000036), /* USB_OC6# */ - H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ - /* GPIO Group GPP_G */ - H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G19, 0x84000500, 0x00000050), /* SMI# */ - H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */ - /* GPIO Group GPP_H */ - H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */ - /* GPIO Group GPD */ - H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD2, 0x00000602, 0x00003c1a), /* LAN_WAKE# */ - H110_PAD_DW0_DW1_CFG(GPD3, 0x04000502, 0x0000301b), /* PWRBTN# */ - H110_PAD_DW0_DW1_CFG(GPD4, 0x04000600, 0x0000001c), /* SLP_S3# */ - H110_PAD_DW0_DW1_CFG(GPD5, 0x04000600, 0x0000001d), /* SLP_S4# */ - H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ - H110_PAD_DW0_DW1_CFG(GPD8, 0x04000600, 0x00000020), /* SUSCLK */ - H110_PAD_DW0_DW1_CFG(GPD9, 0x04000600, 0x00000021), /* SLP_WLAN# */ - H110_PAD_DW0_DW1_CFG(GPD10, 0x04000600, 0x00000022), /* SLP_S5# */ - H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */ - /* GPIO Group GPP_I */ - H110_PAD_DW0_DW1_CFG(GPP_I0, 0x84000502, 0x0000006d), /* DDPB_HPD0 */ - H110_PAD_DW0_DW1_CFG(GPP_I1, 0x84000502, 0x0000006e), /* DDPC_HPD1 */ - H110_PAD_DW0_DW1_CFG(GPP_I2, 0x84000500, 0x0000006f), /* DDPD_HPD2 */ - H110_PAD_DW0_DW1_CFG(GPP_I3, 0x84000502, 0x00000070), /* DDPE_HPD3 */ - H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ - /* DDPB_CTRLCLK */ - H110_PAD_DW0_DW1_CFG(GPP_I5, 0x84000500, 0x00000072), - /* DDPB_CTRLDATA */ - H110_PAD_DW0_DW1_CFG(GPP_I6, 0x84000500, 0x00001073), - /* DDPC_CTRLCLK */ - H110_PAD_DW0_DW1_CFG(GPP_I7, 0x84000500, 0x00000074), - /* DDPC_CTRLDATA */ - H110_PAD_DW0_DW1_CFG(GPP_I8, 0x84000500, 0x00001075), - /* DDPD_CTRLCLK */ - H110_PAD_DW0_DW1_CFG(GPP_I9, 0x84000500, 0x00000076), - /* DDPD_CTRLDATA */ - H110_PAD_DW0_DW1_CFG(GPP_I10, 0x84000500, 0x00001077), -}; - -/* Early pad configuration in romstage. */ -static const struct pad_config early_gpio_table[] = { - /* GPIO Group GPP_A */ - H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ - H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ - H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ - H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ - H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ - H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ - H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ - H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ - H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ - H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ - /* ---- */ - /* SUSWARN#/SUSPWRDNACK */ - H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), - H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ - H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ -}; +const struct pad_config *get_gpio_table(size_t *num); +const struct pad_config *get_early_gpio_table(size_t *num); #endif diff --git a/src/mainboard/asrock/h110m/ramstage.c b/src/mainboard/asrock/h110m/ramstage.c index c93e84c..eab6290 100644 --- a/src/mainboard/asrock/h110m/ramstage.c +++ b/src/mainboard/asrock/h110m/ramstage.c @@ -19,9 +19,12 @@ void mainboard_silicon_init_params(FSP_SIL_UPD *params) { + const struct pad_config *pads; + size_t size; /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. */ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + pads = get_gpio_table(&size); + gpio_configure_pads(pads, size); params->CdClock = 3; /* Enable Virtual Channel 1 */ diff --git a/src/mainboard/asrock/h110m/variants/dvs/gpio.c b/src/mainboard/asrock/h110m/variants/dvs/gpio.c new file mode 100644 index 0000000..f695d0e --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/dvs/gpio.c @@ -0,0 +1,266 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <commonlib/helpers.h> +#include "../../include/gpio.h" + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + PCH_PAD_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + PCH_PAD_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ + PCH_PAD_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ + PCH_PAD_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ + PCH_PAD_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ + PCH_PAD_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + PCH_PAD_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + PCH_PAD_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ + PCH_PAD_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + PCH_PAD_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + PCH_PAD_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + PCH_PAD_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ + PCH_PAD_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ + PCH_PAD_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN# */ + PCH_PAD_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ + PCH_PAD_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ + PCH_PAD_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ + PCH_PAD_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ + PCH_PAD_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ + PCH_PAD_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ + PCH_PAD_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ + PCH_PAD_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ + PCH_PAD_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ + PCH_PAD_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ + /* GPIO Group GPP_B */ + PCH_PAD_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ + PCH_PAD_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ + PCH_PAD_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ + PCH_PAD_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ + PCH_PAD_CFG(GPP_B4, 0x84000502, 0x00000034), /* CPU_GP3 */ + PCH_PAD_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ + PCH_PAD_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ + PCH_PAD_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ + PCH_PAD_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ + PCH_PAD_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ + PCH_PAD_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ + PCH_PAD_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ + PCH_PAD_CFG(GPP_B12, 0x44000600, 0x0000003c), /* SLP_S0# */ + PCH_PAD_CFG(GPP_B13, 0x44000600, 0x0000003d), /* PLTRST# */ + PCH_PAD_CFG(GPP_B14, 0x84000600, 0x0000103e), /* SPKR */ + PCH_PAD_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ + PCH_PAD_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ + PCH_PAD_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ + PCH_PAD_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ + PCH_PAD_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ + PCH_PAD_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ + PCH_PAD_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ + PCH_PAD_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ + PCH_PAD_CFG(GPP_B23, 0x84000a01, 0x00001047), /* PCHHOT# */ + /* GPIO Group GPP_C */ + PCH_PAD_CFG(GPP_C0, 0x44000502, 0x00000048), /* SMBCLK */ + PCH_PAD_CFG(GPP_C1, 0x44000502, 0x00000049), /* SMBDATA */ + PCH_PAD_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ + PCH_PAD_CFG(GPP_C3, 0x44000502, 0x0000004b), /* SML0CLK */ + PCH_PAD_CFG(GPP_C4, 0x44000502, 0x0000004c), /* SML0DATA */ + PCH_PAD_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PCH_PAD_CFG(GPP_C8, 0x84000502, 0x00000050), /* UART0_RXD */ + PCH_PAD_CFG(GPP_C9, 0x84000600, 0x00000051), /* UART0_TXD */ + PCH_PAD_CFG(GPP_C10, 0x84000600, 0x00000052), /* UART0_RTS# */ + PCH_PAD_CFG(GPP_C11, 0x84000502, 0x00000053), /* UART0_CTS# */ + PCH_PAD_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ + PCH_PAD_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ + PCH_PAD_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ + PCH_PAD_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ + PCH_PAD_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ + PCH_PAD_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ + PCH_PAD_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ + PCH_PAD_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ + PCH_PAD_CFG(GPP_C20, 0x84000502, 0x0000005c), /* UART2_RXD */ + PCH_PAD_CFG(GPP_C21, 0x84000600, 0x0000005d), /* UART2_TXD */ + PCH_PAD_CFG(GPP_C22, 0x84000600, 0x0000005e), /* UART2_RTS# */ + PCH_PAD_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ + /* GPIO Group GPP_D */ + PCH_PAD_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ + PCH_PAD_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ + PCH_PAD_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ + PCH_PAD_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ + PCH_PAD_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ + PCH_PAD_CFG(GPP_D5, 0x84000402, 0x00000065), /* I2S_SFRM */ + PCH_PAD_CFG(GPP_D6, 0x84000600, 0x00000066), /* I2S_TXD */ + PCH_PAD_CFG(GPP_D7, 0x84000502, 0x00000067), /* I2S_RXD */ + PCH_PAD_CFG(GPP_D8, 0x84000402, 0x00000068), /* I2S_SCLK */ + PCH_PAD_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ + PCH_PAD_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ + PCH_PAD_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ + PCH_PAD_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ + PCH_PAD_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ + PCH_PAD_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ + PCH_PAD_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ + PCH_PAD_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ + PCH_PAD_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ + PCH_PAD_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ + PCH_PAD_CFG(GPP_D19, 0x84000500, 0x00003073), /* DMIC_CLK0 */ + PCH_PAD_CFG(GPP_D20, 0x84000500, 0x00003074), /* DMIC_DATA0 */ + PCH_PAD_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ + PCH_PAD_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ + PCH_PAD_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ + /* GPIO Group GPP_E */ + PCH_PAD_CFG(GPP_E0, 0x84000502, 0x00003018), /* SATAXPCIE0 */ + PCH_PAD_CFG(GPP_E1, 0x84000502, 0x00003019), /* SATAXPCIE1 */ + PCH_PAD_CFG(GPP_E2, 0x84000502, 0x0000301a), /* SATAXPCIE2 */ + PCH_PAD_CFG(GPP_E3, 0x84000500, 0x0000001b), /* CPU_GP0 */ + PCH_PAD_CFG(GPP_E4, 0x84000500, 0x0000001c), /* SATA_DEVSLP0 */ + PCH_PAD_CFG(GPP_E5, 0x84000500, 0x0000001d), /* SATA_DEVSLP1 */ + PCH_PAD_CFG(GPP_E6, 0x84000500, 0x0000001e), /* SATA_DEVSLP2 */ + PCH_PAD_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ + PCH_PAD_CFG(GPP_E8, 0x84000600, 0x00000020), /* SATA_LED# */ + PCH_PAD_CFG(GPP_E9, 0x44000502, 0x00000021), /* USB_OC0# */ + PCH_PAD_CFG(GPP_E10, 0x44000502, 0x00000022), /* USB_OC1# */ + PCH_PAD_CFG(GPP_E11, 0x44000502, 0x00000023), /* USB_OC2# */ + PCH_PAD_CFG(GPP_E12, 0x44000502, 0x00000024), /* USB_OC3# */ + /* GPIO Group GPP_F */ + PCH_PAD_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ + PCH_PAD_CFG(GPP_F1, 0x84000502, 0x00003026), /* SATAXPCIE4 */ + PCH_PAD_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ + PCH_PAD_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ + PCH_PAD_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ + PCH_PAD_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ + PCH_PAD_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ + PCH_PAD_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ + PCH_PAD_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ + PCH_PAD_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ + PCH_PAD_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ + PCH_PAD_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ + PCH_PAD_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ + PCH_PAD_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ + PCH_PAD_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ + PCH_PAD_CFG(GPP_F15, 0x44000502, 0x00000034), /* USB_OC4# */ + PCH_PAD_CFG(GPP_F16, 0x44000502, 0x00000035), /* USB_OC5# */ + PCH_PAD_CFG(GPP_F17, 0x44000502, 0x00000036), /* USB_OC6# */ + PCH_PAD_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ + PCH_PAD_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ + PCH_PAD_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ + PCH_PAD_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ + PCH_PAD_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ + PCH_PAD_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ + /* GPIO Group GPP_G */ + PCH_PAD_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ + PCH_PAD_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ + PCH_PAD_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ + PCH_PAD_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ + PCH_PAD_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ + PCH_PAD_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ + PCH_PAD_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ + PCH_PAD_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ + PCH_PAD_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ + PCH_PAD_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ + PCH_PAD_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ + PCH_PAD_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ + PCH_PAD_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ + PCH_PAD_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ + PCH_PAD_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ + PCH_PAD_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ + PCH_PAD_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */ + PCH_PAD_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ + PCH_PAD_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */ + PCH_PAD_CFG(GPP_G19, 0x84000500, 0x00000050), /* SMI# */ + PCH_PAD_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ + PCH_PAD_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ + PCH_PAD_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ + PCH_PAD_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */ + /* GPIO Group GPP_H */ + PCH_PAD_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ + PCH_PAD_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */ + PCH_PAD_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ + PCH_PAD_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ + PCH_PAD_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */ + PCH_PAD_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */ + PCH_PAD_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */ + PCH_PAD_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */ + PCH_PAD_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */ + PCH_PAD_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */ + PCH_PAD_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */ + PCH_PAD_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */ + PCH_PAD_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ + PCH_PAD_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */ + PCH_PAD_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */ + PCH_PAD_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */ + PCH_PAD_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */ + PCH_PAD_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */ + PCH_PAD_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */ + PCH_PAD_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */ + PCH_PAD_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ + PCH_PAD_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ + PCH_PAD_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */ + PCH_PAD_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */ + /* GPIO Group GPD */ + PCH_PAD_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ + PCH_PAD_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */ + PCH_PAD_CFG(GPD2, 0x00000602, 0x00003c1a), /* LAN_WAKE# */ + PCH_PAD_CFG(GPD3, 0x04000502, 0x0000301b), /* PWRBTN# */ + PCH_PAD_CFG(GPD4, 0x04000600, 0x0000001c), /* SLP_S3# */ + PCH_PAD_CFG(GPD5, 0x04000600, 0x0000001d), /* SLP_S4# */ + PCH_PAD_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */ + PCH_PAD_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ + PCH_PAD_CFG(GPD8, 0x04000600, 0x00000020), /* SUSCLK */ + PCH_PAD_CFG(GPD9, 0x04000600, 0x00000021), /* SLP_WLAN# */ + PCH_PAD_CFG(GPD10, 0x04000600, 0x00000022), /* SLP_S5# */ + PCH_PAD_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */ + /* GPIO Group GPP_I */ + PCH_PAD_CFG(GPP_I0, 0x84000502, 0x0000006d), /* DDPB_HPD0 */ + PCH_PAD_CFG(GPP_I1, 0x84000502, 0x0000006e), /* DDPC_HPD1 */ + PCH_PAD_CFG(GPP_I2, 0x84000500, 0x0000006f), /* DDPD_HPD2 */ + PCH_PAD_CFG(GPP_I3, 0x84000502, 0x00000070), /* DDPE_HPD3 */ + PCH_PAD_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ + PCH_PAD_CFG(GPP_I5, 0x84000500, 0x00000072), /* DDPB_CTRLCLK */ + PCH_PAD_CFG(GPP_I6, 0x84000500, 0x00001073), /* DDPB_CTRLDATA */ + PCH_PAD_CFG(GPP_I7, 0x84000500, 0x00000074), /* DDPC_CTRLCLK */ + PCH_PAD_CFG(GPP_I8, 0x84000500, 0x00001075), /* DDPC_CTRLDATA */ + PCH_PAD_CFG(GPP_I9, 0x84000500, 0x00000076), /* DDPD_CTRLCLK */ + PCH_PAD_CFG(GPP_I10, 0x84000500, 0x00001077), /* DDPD_CTRLDATA */ +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + /* GPIO Group GPP_A */ + PCH_PAD_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + PCH_PAD_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ + PCH_PAD_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ + PCH_PAD_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ + PCH_PAD_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ + PCH_PAD_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + PCH_PAD_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + PCH_PAD_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + PCH_PAD_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + PCH_PAD_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + /* ---- */ + PCH_PAD_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ + PCH_PAD_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ + PCH_PAD_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ +}; + +const struct pad_config *get_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *get_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} \ No newline at end of file diff --git a/src/mainboard/asrock/h110m/hda_verb.c b/src/mainboard/asrock/h110m/variants/dvs/hda_verb.c similarity index 100% rename from src/mainboard/asrock/h110m/hda_verb.c rename to src/mainboard/asrock/h110m/variants/dvs/hda_verb.c diff --git a/src/mainboard/asrock/h110m/variants/dvs/overridetree.cb b/src/mainboard/asrock/h110m/variants/dvs/overridetree.cb new file mode 100644 index 0000000..aad1374 --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/dvs/overridetree.cb @@ -0,0 +1,207 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Intel Corporation. +## Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +chip soc/intel/skylake + + # USB + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # SATA + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + + # PCH UART, SPI, I2C + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + # Set params for PEG 0:1:0 + register "Peg0MaxLinkWidth" = "Peg0_x16" + # Configure PCIe clockgen in PCH + # PEG0 uses SRCCLKREQ0 and CLKSRC0 + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "0" + register "PcieRpClkSrcNumber[0]" = "0" + + # Enable Root port 5 (x1) for PCIE slot. + register "PcieRpEnable[4]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[4]" = "1" + # Use SRCCLKREQ2# + register "PcieRpClkReqNumber[4]" = "2" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[4]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[4]" = "1" + # Use CLK SRC 2 + register "PcieRpClkSrcNumber[4]" = "2" + # Use Hot Plug subsystem + register "PcieRpHotPlug[4]" = "1" + + # Enable Root port 6 (x1) for LAN. + register "PcieRpEnable[5]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[5]" = "1" + # Use SRCCLKREQ1# + register "PcieRpClkReqNumber[5]" = "1" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[5]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[5]" = "1" + # Use CLK SRC 1 + register "PcieRpClkSrcNumber[5]" = "1" + + # Enable Root port 7 (x1) for PCIE slot. + register "PcieRpEnable[6]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[6]" = "1" + # Use SRCCLKREQ3# + register "PcieRpClkReqNumber[6]" = "3" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[6]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[6]" = "1" + # Use CLK SRC 3 + register "PcieRpClkSrcNumber[6]" = "3" + # Use Hot Plug subsystem + register "PcieRpHotPlug[6]" = "1" + + # PL2 override 91W + register "tdp_pl2_override" = "91" + + device domain 0 on + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 on end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on # Chipset LPC/eSPI Controller + subsystemid 0x1849 0x1a43 + chip superio/nuvoton/nct6791d + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel + # global + irq 0x1c = 0x10 + irq 0x27 = 0x10 + irq 0x2a = 0x64 + # parallel port + io 0x60 = 0x0378 + irq 0x70 = 7 + drq 0x74 = 4 # No DMA + irq 0xf0 = 0x3c # Printer mode + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # IR + io 0x60 = 0x02f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 off end # GPIO1 + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 off end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end # superio/nuvoton/nct6791d + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM module + end + end # LPC Interface + end +end diff --git a/src/mainboard/asrock/h110m/variants/stx/gpio.c b/src/mainboard/asrock/h110m/variants/stx/gpio.c new file mode 100644 index 0000000..472db6c --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/stx/gpio.c @@ -0,0 +1,268 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <commonlib/helpers.h> +#include "../../include/gpio.h" + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPP_A ------- */ + PCH_PAD_CFG(GPP_A0, 0x84000502, 0x00000000), /* RCIN# */ + PCH_PAD_CFG(GPP_A1, 0x84000402, 0x00003000), /* LAD0 */ + PCH_PAD_CFG(GPP_A2, 0x84000402, 0x00003000), /* LAD1 */ + PCH_PAD_CFG(GPP_A3, 0x84000402, 0x00003000), /* LAD2 */ + PCH_PAD_CFG(GPP_A4, 0x84000402, 0x00003000), /* LAD3 */ + PCH_PAD_CFG(GPP_A5, 0x84000600, 0x00000000), /* LFRAME# */ + PCH_PAD_CFG(GPP_A6, 0x84000400, 0x00000000), /* SERIRQ */ + PCH_PAD_CFG(GPP_A7, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A8, 0x84000500, 0x00000000), /* CLKRUN# */ + PCH_PAD_CFG(GPP_A9, 0x84000600, 0x00001000), /* CLKOUT_LPC0 */ + PCH_PAD_CFG(GPP_A10, 0x84000600, 0x00001000), /* CLKOUT_LPC1 */ + PCH_PAD_CFG(GPP_A11, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A12, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A13, 0x44000600, 0x00000000), /* SUSWARN#/SUSPWRDNACK */ + PCH_PAD_CFG(GPP_A14, 0x44000600, 0x00000000), /* SUS_STAT# */ + PCH_PAD_CFG(GPP_A15, 0x44000502, 0x00003000), /* SUS_ACK# */ + PCH_PAD_CFG(GPP_A16, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A17, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A18, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A19, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A20, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A21, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A22, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A23, 0x84000102, 0x00000000), /* GPIO */ + /* ------- GPIO Group GPP_B ------- */ + PCH_PAD_CFG(GPP_B0, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B1, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B2, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B3, 0x44000201, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B4, 0x84000502, 0x00000000), /* CPU_GP3 */ + PCH_PAD_CFG(GPP_B5, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B6, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B7, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B8, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B9, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B10, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B11, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B12, 0x44000600, 0x00000000), /* SLP_S0# */ + PCH_PAD_CFG(GPP_B13, 0x44000600, 0x00000000), /* PLTRST# */ + PCH_PAD_CFG(GPP_B14, 0x84000600, 0x00001000), /* SPKR */ + PCH_PAD_CFG(GPP_B15, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B16, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B17, 0x44000201, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B18, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B19, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B20, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B21, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B22, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_B23, 0x84000a01, 0x00001000), /* PCHHOT# */ + /* ------- GPIO Group GPP_C ------- */ + PCH_PAD_CFG(GPP_C0, 0x44000502, 0x00000000), /* SMBCLK */ + PCH_PAD_CFG(GPP_C1, 0x44000502, 0x00000000), /* SMBDATA */ + PCH_PAD_CFG(GPP_C2, 0x44000201, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C3, 0x44000502, 0x00000000), /* SML0CLK */ + PCH_PAD_CFG(GPP_C4, 0x44000502, 0x00000000), /* SML0DATA */ + PCH_PAD_CFG(GPP_C5, 0x84000100, 0x00000000), /* GPIO */ + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PCH_PAD_CFG(GPP_C8, 0x84000502, 0x00000000), /* UART0_RXD */ + PCH_PAD_CFG(GPP_C9, 0x84000600, 0x00000000), /* UART0_TXD */ + PCH_PAD_CFG(GPP_C10, 0x84000600, 0x00000000), /* UART0_RTS# */ + PCH_PAD_CFG(GPP_C11, 0x84000502, 0x00000000), /* UART0_CTS# */ + PCH_PAD_CFG(GPP_C12, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C13, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C14, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C15, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C16, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C17, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C18, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C19, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_C20, 0x84000502, 0x00000000), /* UART2_RXD */ + PCH_PAD_CFG(GPP_C21, 0x84000600, 0x00000000), /* UART2_TXD */ + PCH_PAD_CFG(GPP_C22, 0x84000600, 0x00000000), /* UART2_RTS# */ + PCH_PAD_CFG(GPP_C23, 0x40880102, 0x00000000), /* GPIO */ + /* ------- GPIO Group GPP_D ------- */ + PCH_PAD_CFG(GPP_D0, 0xc4000200, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D1, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D2, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D3, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D4, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D5, 0x84000402, 0x00000000), /* I2S_SFRM */ + PCH_PAD_CFG(GPP_D6, 0x84000600, 0x00000000), /* I2S_TXD */ + PCH_PAD_CFG(GPP_D7, 0x84000502, 0x00000000), /* I2S_RXD */ + PCH_PAD_CFG(GPP_D8, 0x84000402, 0x00000000), /* I2S_SCLK */ + PCH_PAD_CFG(GPP_D9, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D10, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D11, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D12, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D13, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D14, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D15, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D16, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D17, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D18, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D19, 0x84000500, 0x00003000), /* DMIC_CLK0 */ + PCH_PAD_CFG(GPP_D20, 0x84000500, 0x00003000), /* DMIC_DATA0 */ + PCH_PAD_CFG(GPP_D21, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D22, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_D23, 0x84000102, 0x00000000), /* GPIO */ + /* ------- GPIO Group GPP_E ------- */ + PCH_PAD_CFG(GPP_E0, 0x84000502, 0x00003000), /* SATAXPCIE0 */ + PCH_PAD_CFG(GPP_E1, 0x84000502, 0x00003000), /* SATAXPCIE1 */ + PCH_PAD_CFG(GPP_E2, 0x84000502, 0x00003000), /* SATAXPCIE2 */ + PCH_PAD_CFG(GPP_E3, 0x84000502, 0x00000000), /* CPU_GP0 */ + PCH_PAD_CFG(GPP_E4, 0x84000500, 0x00000000), /* SATA_DEVSLP0 */ + PCH_PAD_CFG(GPP_E5, 0x84000500, 0x00000000), /* SATA_DEVSLP1 */ + PCH_PAD_CFG(GPP_E6, 0x84000500, 0x00000000), /* SATA_DEVSLP2 */ + PCH_PAD_CFG(GPP_E7, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_E8, 0x84000600, 0x00000000), /* SATA_LED# */ + PCH_PAD_CFG(GPP_E9, 0x44000502, 0x00000000), /* USB_OC0# */ + PCH_PAD_CFG(GPP_E10, 0x44000502, 0x00000000), /* USB_OC1# */ + PCH_PAD_CFG(GPP_E11, 0x44000502, 0x00000000), /* USB_OC2# */ + PCH_PAD_CFG(GPP_E12, 0x44000502, 0x00000000), /* USB_OC3# */ + /* ------- GPIO Group GPP_F ------- */ + PCH_PAD_CFG(GPP_F0, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F1, 0x84000502, 0x00003000), /* SATAXPCIE4 */ + PCH_PAD_CFG(GPP_F2, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F3, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F4, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F5, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F6, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F7, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F8, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F9, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F10, 0x80100102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F11, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F12, 0x80900102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F13, 0x80100102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F14, 0x40900102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F15, 0x44000502, 0x00000000), /* USB_OC4# */ + PCH_PAD_CFG(GPP_F16, 0x44000502, 0x00000000), /* USB_OC5# */ + PCH_PAD_CFG(GPP_F17, 0x44000502, 0x00000000), /* USB_OC6# */ + PCH_PAD_CFG(GPP_F18, 0x84000201, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F19, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F20, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F21, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F22, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_F23, 0x84000100, 0x00000000), /* GPIO */ + /* ------- GPIO Group GPP_G ------- */ + PCH_PAD_CFG(GPP_G0, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G1, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G2, 0x80800102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G3, 0x80800102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G4, 0x44000200, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G5, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G6, 0x80800102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G7, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G8, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G9, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G10, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G11, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G12, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G13, 0x84000201, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G14, 0x80800100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G15, 0x84000200, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G16, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G17, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G18, 0x80100102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G19, 0x84000500, 0x00000000), /* SMI# */ + PCH_PAD_CFG(GPP_G20, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G21, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G22, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_G23, 0x84000102, 0x00000000), /* GPIO */ + /* ------- GPIO Group GPP_H ------- */ + PCH_PAD_CFG(GPP_H0, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H1, 0x44000300, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H2, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H3, 0x44000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H4, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H5, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H6, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H7, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H8, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H9, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H10, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H11, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H12, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H13, 0x80100102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H14, 0x80100102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H15, 0x80100102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H16, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H17, 0x84000201, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H18, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H19, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H20, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H21, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H22, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_H23, 0x04000102, 0x00000000), /* GPIO */ + /* -------- GPIO Group GPD -------- */ + PCH_PAD_CFG(GPD0, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPD1, 0x04000200, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPD2, 0x00080602, 0x00003c00), /* LAN_WAKE# */ + PCH_PAD_CFG(GPD3, 0x04000502, 0x00003000), /* PWRBTN# */ + PCH_PAD_CFG(GPD4, 0x04000600, 0x00000000), /* SLP_S3# */ + PCH_PAD_CFG(GPD5, 0x04000600, 0x00000000), /* SLP_S4# */ + PCH_PAD_CFG(GPD6, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPD7, 0x84000103, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPD8, 0x04000600, 0x00000000), /* SUSCLK */ + PCH_PAD_CFG(GPD9, 0x04000600, 0x00000000), /* SLP_WLAN# */ + PCH_PAD_CFG(GPD10, 0x04000600, 0x00000000), /* SLP_S5# */ + PCH_PAD_CFG(GPD11, 0x04000600, 0x00000000), /* LANPHYPC */ + /* ------- GPIO Group GPP_I ------- */ + PCH_PAD_CFG(GPP_I0, 0x84000500, 0x00000000), /* DDPB_HPD0 */ + PCH_PAD_CFG(GPP_I1, 0x84000502, 0x00000000), /* DDPC_HPD1 */ + PCH_PAD_CFG(GPP_I2, 0x84000502, 0x00000000), /* DDPD_HPD2 */ + PCH_PAD_CFG(GPP_I3, 0x84000500, 0x00000000), /* DDPE_HPD3 */ + PCH_PAD_CFG(GPP_I4, 0x84000100, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_I5, 0x84000502, 0x00000000), /* DDPB_CTRLCLK */ + PCH_PAD_CFG(GPP_I6, 0x84000502, 0x00001000), /* DDPB_CTRLDATA */ + PCH_PAD_CFG(GPP_I7, 0x84000500, 0x00000000), /* DDPC_CTRLCLK */ + PCH_PAD_CFG(GPP_I8, 0x84000500, 0x00001000), /* DDPC_CTRLDATA */ + PCH_PAD_CFG(GPP_I9, 0x84000500, 0x00000000), /* DDPD_CTRLCLK */ + PCH_PAD_CFG(GPP_I10, 0x84000500, 0x00001000), /* DDPD_CTRLDATA */ +}; + +/* Early pad configuration in romstage */ +static const struct pad_config early_gpio_table[] = { + PCH_PAD_CFG(GPP_A0, 0x84000502, 0x00000000), /* RCIN# */ + PCH_PAD_CFG(GPP_A1, 0x84000402, 0x00003000), /* LAD0 */ + PCH_PAD_CFG(GPP_A2, 0x84000402, 0x00003000), /* LAD1 */ + PCH_PAD_CFG(GPP_A3, 0x84000402, 0x00003000), /* LAD2 */ + PCH_PAD_CFG(GPP_A4, 0x84000402, 0x00003000), /* LAD3 */ + PCH_PAD_CFG(GPP_A5, 0x84000600, 0x00000000), /* LFRAME# */ + PCH_PAD_CFG(GPP_A6, 0x84000400, 0x00000000), /* SERIRQ */ + PCH_PAD_CFG(GPP_A7, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A8, 0x84000500, 0x00000000), /* CLKRUN# */ + PCH_PAD_CFG(GPP_A9, 0x84000600, 0x00001000), /* CLKOUT_LPC0 */ + PCH_PAD_CFG(GPP_A10, 0x84000600, 0x00001000), /* CLKOUT_LPC1 */ + PCH_PAD_CFG(GPP_A11, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A12, 0x84000102, 0x00000000), /* GPIO */ + PCH_PAD_CFG(GPP_A13, 0x44000600, 0x00000000), /* SUSWARN#/SUSPWRDNACK */ + PCH_PAD_CFG(GPP_A14, 0x44000600, 0x00000000), /* SUS_STAT# */ + PCH_PAD_CFG(GPP_A15, 0x44000502, 0x00003000), /* SUS_ACK# */ +}; + +const struct pad_config *get_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *get_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/asrock/h110m/variants/stx/hda_verb.c b/src/mainboard/asrock/h110m/variants/stx/hda_verb.c new file mode 100644 index 0000000..52e3039 --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/stx/hda_verb.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki <naresh.solanki(a)intel.com> for Intel Corp.) + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* ALC283 coreboot specific header */ + 0x10ec0283, /* Codec Vendor / Device ID: Realtek */ + 0x18491283, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x18491283), + AZALIA_PIN_CFG(0x0, 0x12, 0x40000000), + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1a, 0x02a19020), + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1d, 0x40559c05), + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x21, 0x0221101f), + + /* Intel Kaby Lake HDA coreboot specific header */ + 0x8086280b, /* Codec Vendor / Device ID */ + 0x80860101, + 0x00000004, + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + AZALIA_SUBVENDOR(0x2, 0x80860101), + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x05, 0x18560010), + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x06, 0x18560020), + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x07, 0x18560030) +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/h110m/variants/stx/overridetree.cb b/src/mainboard/asrock/h110m/variants/stx/overridetree.cb new file mode 100644 index 0000000..45403c8 --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/stx/overridetree.cb @@ -0,0 +1,133 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Intel Corporation. +## Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +chip soc/intel/skylake + + # FSP Configuration + register "EnableLan" = "1" + + # USB 2.0 + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port Front Panel + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port Front Panel + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" # USB3/2 Type A Front Panel + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" # USB3/2 Type A Back panel + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # USB3/2 Type A Back panel + register "usb2_ports[5]" = "USB2_PORT_EMPTY" + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + register "usb2_ports[10]" = "USB2_PORT_EMPTY" + register "usb2_ports[11]" = "USB2_PORT_EMPTY" + register "usb2_ports[12]" = "USB2_PORT_EMPTY" + register "usb2_ports[13]" = "USB2_PORT_EMPTY" + + # USB 3.0 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A Front Panel + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A Back panel + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A Back panel + register "usb3_ports[5]" = "USB3_PORT_EMPTY" + register "usb3_ports[6]" = "USB3_PORT_EMPTY" + register "usb3_ports[7]" = "USB3_PORT_EMPTY" + register "usb3_ports[8]" = "USB3_PORT_EMPTY" + register "usb3_ports[9]" = "USB3_PORT_EMPTY" + + # SATA + # SATA0 - Unused + # SATA1 - Bottom left connector + # SATA2 - Bottom right connector + # SATA3 - Top side connector + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 0, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 0, \ + [5] = 0, \ + [6] = 0, \ + [7] = 0, \ + }" + + # PCH UART, SPI, I2C + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + # PEG 0:1:0 is used for NVMe x4 2280 M.2 + register "Peg0MaxLinkWidth" = "Peg0_x4" + # Configure PCH PCIe clockgen for PEG0: SRCCLKREQ7 and CLKSRC7 + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "7" + register "PcieRpClkSrcNumber[0]" = "7" + + # Root port 4 (x1) is used for I219V LAN device + register "PcieRpEnable[3]" = "1" + # Use SRCCLKREQ13 and CLKSRC10 + register "PcieRpClkReqSupport[3]" = "1" + register "PcieRpClkReqNumber[3]" = "13" + register "PcieRpClkSrcNumber[3]" = "10" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[3]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[3]" = "1" + + # Root port 7(x1) is used for 2242 M.2 PCIE slot + register "PcieRpEnable[6]" = "1" + # Use SRCCLKREQ1 and CLKSRC1 + register "PcieRpClkReqSupport[6]" = "1" + register "PcieRpClkReqNumber[6]" = "1" + register "PcieRpClkSrcNumber[6]" = "1" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[6]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[6]" = "1" + # Use Hot Plug subsystem + register "PcieRpHotPlug[6]" = "1" + + # PL2 override 65W + register "tdp_pl2_override" = "65" + + device domain 0 on + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 on end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on # Chipset LPC/eSPI Controller + subsystemid 0x1849 0x1a43 + end # LPC Interface + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/34904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If95c7ec78b8bee10ed7ae761754ba7f7d548aa55 Gerrit-Change-Number: 34904 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

1 1

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2019