coreboot-gerrit September 2019

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Change in coreboot[master]: drivers/elog: Add elog_boot_notify()
by Kyösti Mälkki (Code Review) 13 Sep '19

13 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35373 ) Change subject: drivers/elog: Add elog_boot_notify() ...................................................................... drivers/elog: Add elog_boot_notify() Change-Id: I898188d31fcfd153eb95d0a7324fa9fd85316e3c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/memory_init.c M src/include/elog.h M src/northbridge/intel/nehalem/early_init.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/southbridge/intel/lynxpoint/early_pch.c 10 files changed, 16 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/35373/1 diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index d86d3ab..67bea32 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -48,8 +48,7 @@ s3wake = params->power_state->prev_sleep_state == ACPI_S3; - if (CONFIG(ELOG_BOOT_COUNT) && !s3wake) - boot_count_increment(); + elog_boot_notify(s3wake); /* Perform remaining SOC initialization */ soc_pre_ram_init(params); diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 5765fb7..a075f01 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -392,8 +392,7 @@ struct memranges memmap; struct range_entry freeranges[2]; - if (CONFIG(ELOG_BOOT_COUNT) && !s3wake) - boot_count_increment(); + elog_boot_notify(s3wake); if (cbfs_boot_locate(&file_desc, name, NULL)) { printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name); diff --git a/src/include/elog.h b/src/include/elog.h index 9bb05ad..0574819 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -274,6 +274,12 @@ #endif u32 boot_count_increment(void); +static inline void elog_boot_notify(int s3_resume) +{ + if (CONFIG(ELOG_BOOT_COUNT) && !s3_resume) + boot_count_increment(); +} + /* * Callback from GSMI handler to allow platform to log any wake source * information. diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index 1f413e3..5bdb5d5 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -139,8 +139,7 @@ s3_resume = (inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3); - if (CONFIG(ELOG_BOOT_COUNT) && !s3_resume) - boot_count_increment(); + elog_boot_notify(s3_resume); /* Device Enable */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 1b402dc..55f2928 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -74,8 +74,7 @@ s3resume = southbridge_detect_s3_resume(); - if (CONFIG(ELOG_BOOT_COUNT) && !s3resume) - boot_count_increment(); + elog_boot_notify(s3resume); post_code(0x38); diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 9882d91..257ae67 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -49,12 +49,10 @@ console_init(); mainboard_romstage_entry_s3(s3_resume); + elog_boot_notify(s3_resume); if (!s3_resume) { post_code(0x40); - - if (CONFIG(ELOG_BOOT_COUNT)) - boot_count_increment(); } else { printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 4032d3f..2228c1a 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -97,6 +97,7 @@ load_smu_fw1(); mainboard_romstage_entry_s3(s3_resume); + elog_boot_notify(s3_resume); bsp_agesa_call(); @@ -132,8 +133,6 @@ msr_t sys_cfg = rdmsr(SYSCFG_MSR); sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB; wrmsr(SYSCFG_MSR, sys_cfg); - if (CONFIG(ELOG_BOOT_COUNT)) - boot_count_increment(); } else { printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 7348d2b..7c129e2 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -185,10 +185,7 @@ printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state); -#if CONFIG(ELOG_BOOT_COUNT) - if (prev_sleep_state != ACPI_S3) - boot_count_increment(); -#endif + elog_boot_notify(prev_sleep_state == ACPI_S3); /* Initialize RAM */ raminit(&mp, prev_sleep_state); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index ebb72cb..96218f4 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -62,6 +62,8 @@ /* Get power state */ rp.power_state = fill_power_state(); + elog_boot_notify(rp.power_state->prev_sleep_state == ACPI_S3); + /* Print useful platform information */ report_platform_info(); @@ -80,10 +82,6 @@ rp.pei_data.boot_mode = rp.power_state->prev_sleep_state; - if (CONFIG(ELOG_BOOT_COUNT) - && rp.power_state->prev_sleep_state != ACPI_S3) - boot_count_increment(); - /* Print ME state before MRC */ intel_me_status(); diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index c362577..25ffdc4 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -124,10 +124,7 @@ wake_from_s3 = southbridge_detect_s3_resume(); -#if CONFIG(ELOG_BOOT_COUNT) - if (!wake_from_s3) - boot_count_increment(); -#endif + elog_boot_notify(wake_from_s3); /* Report if we are waking from s3. */ return wake_from_s3; -- To view, visit https://review.coreboot.org/c/coreboot/+/35373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I898188d31fcfd153eb95d0a7324fa9fd85316e3c Gerrit-Change-Number: 35373 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: intel/nehalem: Refactor ACPI S3 detection
by Kyösti Mälkki (Code Review) 13 Sep '19

13 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35372 ) Change subject: intel/nehalem: Refactor ACPI S3 detection ...................................................................... intel/nehalem: Refactor ACPI S3 detection Change-Id: Ib405f3c3a6143e972963307eef7371dd43b9b5fc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/northbridge/intel/nehalem/early_init.c 1 file changed, 8 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35372/1 diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index a5cac7b..1f413e3 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -73,22 +73,7 @@ pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33); pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33); -#if CONFIG(ELOG_BOOT_COUNT) - /* Increment Boot Counter for non-S3 resume */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) - boot_count_increment(); -#endif - printk(BIOS_DEBUG, " done.\n"); - -#if CONFIG(ELOG_BOOT_COUNT) - /* Increment Boot Counter except when resuming from S3 */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) - return; - boot_count_increment(); -#endif } static void early_cpu_init (void) @@ -134,6 +119,7 @@ { u32 capid0_a; u8 reg8; + int s3_resume; /* Device ID Override Enable should be done very early */ capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); @@ -150,6 +136,12 @@ /* Setup all BARs required for early PCIe and raminit */ nehalem_setup_bars(); + s3_resume = (inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && + (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3); + + if (CONFIG(ELOG_BOOT_COUNT) && !s3_resume) + boot_count_increment(); + /* Device Enable */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_DEVEN, DEVEN_IGD | DEVEN_PEG10 | DEVEN_HOST); @@ -161,7 +153,7 @@ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Magic for S3 resume. Must be done early. */ - if (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) { + if (s3_resume) { MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~1) | 6; MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~3) | 4; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib405f3c3a6143e972963307eef7371dd43b9b5fc Gerrit-Change-Number: 35372 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: intel/fsp2_0: Move TS_BEFORE_INITRAM
by Kyösti Mälkki (Code Review) 13 Sep '19

13 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35371 ) Change subject: intel/fsp2_0: Move TS_BEFORE_INITRAM ...................................................................... intel/fsp2_0: Move TS_BEFORE_INITRAM Exclude FSP-M loading from the timestamps used for RAM detection and training process. Change-Id: I859b292f2347c6f0e3e41555ad4fb8d95a139007 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/intel/fsp2_0/memory_init.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/35371/1 diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 1386d2c..5765fb7 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -392,8 +392,6 @@ struct memranges memmap; struct range_entry freeranges[2]; - timestamp_add_now(TS_BEFORE_INITRAM); - if (CONFIG(ELOG_BOOT_COUNT) && !s3wake) boot_count_increment(); @@ -421,6 +419,8 @@ /* Signal that FSP component has been loaded. */ prog_segment_loaded(hdr.image_base, hdr.image_size, SEG_FINAL); + timestamp_add_now(TS_BEFORE_INITRAM); + do_fsp_memory_init(&hdr, s3wake, &memmap); timestamp_add_now(TS_AFTER_INITRAM); -- To view, visit https://review.coreboot.org/c/coreboot/+/35371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I859b292f2347c6f0e3e41555ad4fb8d95a139007 Gerrit-Change-Number: 35371 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: mb/google/drallion: Use arcada_ish.bin for arcada_cml
by Selma Bensaid (Code Review) 13 Sep '19

13 Sep '19

Selma Bensaid has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35347 ) Change subject: mb/google/drallion: Use arcada_ish.bin for arcada_cml ...................................................................... mb/google/drallion: Use arcada_ish.bin for arcada_cml drallion_ish.bin is updated for drallion GPIO changes and not compatible with arcada_cml. Signed-off-by: Selma BENSAID <selma.bensaid(a)intel.com> Change-Id: Idb35c33425bfd50533df74349dd645db18a65bc5 --- M src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/35347/1 diff --git a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb index 3628264..9e5be93 100644 --- a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb @@ -231,7 +231,7 @@ device pci 12.6 off end # GSPI #2 device pci 13.0 on # Integrated Sensor Hub chip drivers/intel/ish - register "firmware_name" = ""drallion_ish.bin"" + register "firmware_name" = ""arcada_ish.bin"" device generic 0 on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/35347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb35c33425bfd50533df74349dd645db18a65bc5 Gerrit-Change-Number: 35347 Gerrit-PatchSet: 1 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: vendorcode/cavium: Replace use of __PRE_RAM__
by Kyösti Mälkki (Code Review) 13 Sep '19

13 Sep '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34998 ) Change subject: vendorcode/cavium: Replace use of __PRE_RAM__ ...................................................................... Patch Set 13: (1 comment) https://review.coreboot.org/c/coreboot/+/34998/11/src/vendorcode/cavium/bdk… File src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c: https://review.coreboot.org/c/coreboot/+/34998/11/src/vendorcode/cavium/bdk… PS11, Line 208: > Now that __PRE_RAM__ tests inside set_value() were removed, it would need malloc(). […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/34998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c93031c8c0e3a86261988edc956e8cd5a8dd961 Gerrit-Change-Number: 34998 Gerrit-PatchSet: 13 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 13 Sep 2019 08:37:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/intel/fsp2_0: Allow platform to increase mem overhead
by Marshall Dawson (Code Review) 13 Sep '19

13 Sep '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35383 ) Change subject: drivers/intel/fsp2_0: Allow platform to increase mem overhead ...................................................................... drivers/intel/fsp2_0: Allow platform to increase mem overhead Add a call and a weak function for an additional amount of DRAM to be considered overhead by the SOC. This change provides a convenient solution for reserving additional memory, e.g. for AMD TSEG, without requiring explicit passing of additional values to FSP via UPD. TEST=Implement in Picasso and verify FSP recognizes additional TOLUM requirements. Change-Id: Ia291273b9b7fda0e34be7879473eabd7b53b47b4 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/memory_init.c 2 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/35383/1 diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index b905b69..2c3a566 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -58,6 +58,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version); void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd); +/* Allow the platform to increase BootLoaderTolumSize */ +size_t platform_mem_overhead_size(void); + /* * The following functions are used when FSP_PLATFORM_MEMORY_SETTINGS_VERSION * is employed allowing the mainboard and SoC to supply their own version diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 1386d2c..349a188 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -41,6 +41,8 @@ CONFIG(VBOOT_STARTS_IN_BOOTBLOCK), "for TPM MRC hash functionality, vboot must start in bootblock"); +__weak size_t platform_mem_overhead_size(void) { return 0; } + static void save_memory_training_data(bool s3wake, uint32_t fsp_version) { size_t mrc_data_size; @@ -289,8 +291,11 @@ arch_upd = &fspm_upd.FspmArchUpd; - /* Reserve enough memory under TOLUD to save CBMEM header */ + /* Reserve enough memory under TOLUD to save CBMEM header and any + * additional requirements of the platform implementation. + */ arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); + arch_upd->BootLoaderTolumSize += platform_mem_overhead_size(); /* Fill common settings on behalf of chipset. */ if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version, -- To view, visit https://review.coreboot.org/c/coreboot/+/35383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia291273b9b7fda0e34be7879473eabd7b53b47b4 Gerrit-Change-Number: 35383 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: mb/google/hatch/var: Increase Goodix touchscreen reset delay to 500ms
by Philip Chen (Code Review) 13 Sep '19

13 Sep '19

Philip Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35350 ) Change subject: mb/google/hatch/var: Increase Goodix touchscreen reset delay to 500ms ...................................................................... mb/google/hatch/var: Increase Goodix touchscreen reset delay to 500ms Even though GT7375P programming guide rev0.4 only requires a reset delay of 120ms, in practice, we have to increase the reset delay to 500ms, or Goodix FW update would fail. BUG=b:138795891, b:138796844 TEST=boot helios board and verify Goodix FW update succeeded Signed-off-by: Philip Chen <philipchen(a)google.com> Change-Id: Ic0049bf240de0a1c7f1b1f39bf155d48bb76fb86 --- M src/mainboard/google/hatch/variants/hatch/overridetree.cb M src/mainboard/google/hatch/variants/helios/overridetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/35350/1 diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 6ed25c8..df2cc38 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -98,7 +98,7 @@ register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "120" + register "generic.reset_delay_ms" = "500" register "generic.reset_off_delay_ms" = "3" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" register "generic.enable_delay_ms" = "12" diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index b3da8c9..8ca878d 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -103,7 +103,7 @@ register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "120" + register "generic.reset_delay_ms" = "500" register "generic.reset_off_delay_ms" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" -- To view, visit https://review.coreboot.org/c/coreboot/+/35350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0049bf240de0a1c7f1b1f39bf155d48bb76fb86 Gerrit-Change-Number: 35350 Gerrit-PatchSet: 1 Gerrit-Owner: Philip Chen <philipchen(a)google.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: soc/amd/picasso: Refactor AOAC enabling
by Marshall Dawson (Code Review) 13 Sep '19

13 Sep '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35296 ) Change subject: soc/amd/picasso: Refactor AOAC enabling ...................................................................... soc/amd/picasso: Refactor AOAC enabling Replace the raw register definitions with device numbers and macros for determining the register offsets. Rewrite the source to refer to AOAC device numbers instead of a structure. Remove the calculated offset for the console UART. Picasso's UARTs are not contiguous so handle them separately. Change-Id: Iffc87f39ebe38394a56d41bb0940e9701fd05db9 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/southbridge.c 2 files changed, 57 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/35296/1 diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 803c638..dad4358 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -206,14 +206,18 @@ #define I2C_PAD_CTRL_SPARE1 BIT(18) /* FCH AOAC Registers 0xfed81e00 */ -#define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40 -#define FCH_AOAC_D3_CONTROL_I2C2 0x4e -#define FCH_AOAC_D3_CONTROL_I2C3 0x50 -#define FCH_AOAC_D3_CONTROL_I2C4 0x52 -#define FCH_AOAC_D3_CONTROL_UART0 0x56 -#define FCH_AOAC_D3_CONTROL_UART1 0x58 -#define FCH_AOAC_D3_CONTROL_AMBA 0x62 -/* Bit definitions for all FCH_AOAC_D3_CONTROL_* Registers */ +#define AOAC_DEV_D3_CTL(device) (0x40 + device * 2) +#define AOAC_DEV_D3_STATE(device) (AOAC_DEV_D3_CTL(device) + 1) + +#define FCH_AOAC_DEV_CLK_GEN 0 +#define FCH_AOAC_DEV_I2C2 7 +#define FCH_AOAC_DEV_I2C3 8 +#define FCH_AOAC_DEV_I2C4 9 +#define FCH_AOAC_DEV_UART0 11 +#define FCH_AOAC_DEV_UART1 12 +#define FCH_AOAC_DEV_AMBA 17 + +/* Bit definitions for Device D3 Control AOACx0000[40...7E] step 2 */ #define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1)) #define FCH_AOAC_DEVICE_STATE BIT(2) #define FCH_AOAC_PWR_ON_DEV BIT(3) @@ -222,14 +226,7 @@ #define FCH_AOAC_SW_RST_B BIT(6) #define FCH_AOAC_IS_SW_CONTROL BIT(7) -#define FCH_AOAC_D3_STATE_CLK_GEN 0x41 -#define FCH_AOAC_D3_STATE_I2C2 0x4f -#define FCH_AOAC_D3_STATE_I2C3 0x51 -#define FCH_AOAC_D3_STATE_I2C4 0x53 -#define FCH_AOAC_D3_STATE_UART0 0x57 -#define FCH_AOAC_D3_STATE_UART1 0x59 -#define FCH_AOAC_D3_STATE_AMBA 0x63 -/* Bit definitions for all FCH_AOAC_D3_STATE_* Registers */ +/* Bit definitions for Device D3 State AOACx0000[41...7f] step 2 */ #define FCH_AOAC_PWR_RST_STATE BIT(0) #define FCH_AOAC_RST_CLK_OK_STATE BIT(1) #define FCH_AOAC_RST_B_STATE BIT(2) @@ -307,11 +304,6 @@ /* IO 0xf0 NCP Error */ #define NCP_WARM_BOOT BIT(7) /* Write-once */ -struct picasso_aoac { - int enable; - int status; -}; - typedef struct aoac_devs { unsigned int :7; unsigned int ic2e:1; /* 7: I2C2 */ diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 582034a..e6fc0de 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -36,19 +36,25 @@ #include <soc/nvs.h> #include <types.h> +#define FCH_AOAC_UART_FOR_CONSOLE \ + (CONFIG_UART_FOR_CONSOLE == 0 ? FCH_AOAC_DEV_UART0 \ + : CONFIG_UART_FOR_CONSOLE == 1 ? FCH_AOAC_DEV_UART1 \ + : -1) +#if FCH_AOAC_UART_FOR_CONSOLE == -1 +# error Unsupported UART_FOR_CONSOLE chosen +#endif + /* * Table of devices that need their AOAC registers enabled and waited * upon (usually about .55 milliseconds). Instead of individual delays * waiting for each device to become available, a single delay will be - * executed. + * executed. The console UART is handled separately from this table. */ -const static struct picasso_aoac aoac_devs[] = { - { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), - (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) }, - { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA }, - { FCH_AOAC_D3_CONTROL_I2C2, FCH_AOAC_D3_STATE_I2C2 }, - { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 }, - { FCH_AOAC_D3_CONTROL_I2C4, FCH_AOAC_D3_STATE_I2C4 } +const static int aoac_devs[] = { + FCH_AOAC_DEV_AMBA, + FCH_AOAC_DEV_I2C2, + FCH_AOAC_DEV_I2C3, + FCH_AOAC_DEV_I2C4, }; /* @@ -101,21 +107,21 @@ return irq_association; } -static void power_on_aoac_device(int aoac_device_control_register) +static void power_on_aoac_device(int dev) { uint8_t byte; /* Power on the UART and AMBA devices */ - byte = aoac_read8(aoac_device_control_register); + byte = aoac_read8(AOAC_DEV_D3_CTL(dev)); byte |= FCH_AOAC_PWR_ON_DEV; - aoac_write8(aoac_device_control_register, byte); + aoac_write8(AOAC_DEV_D3_CTL(dev), byte); } -static bool is_aoac_device_enabled(int aoac_device_status_register) +static bool is_aoac_device_enabled(int dev) { uint8_t byte; - byte = aoac_read8(aoac_device_status_register); + byte = aoac_read8(AOAC_DEV_D3_STATE(dev)); byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE); if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE)) return true; @@ -123,20 +129,38 @@ return false; } +static void enable_aoac_console_uart(void) +{ + if (!CONFIG(PICASSO_UART)) + return; + + power_on_aoac_device(FCH_AOAC_UART_FOR_CONSOLE); +} + +static bool is_aoac_console_uart_enabled(void) +{ + if (!CONFIG(PICASSO_UART)) + return true; + + return is_aoac_device_enabled(FCH_AOAC_UART_FOR_CONSOLE); +} + void enable_aoac_devices(void) { bool status; int i; for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) - power_on_aoac_device(aoac_devs[i].enable); + power_on_aoac_device(aoac_devs[i]); + enable_aoac_console_uart(); /* Wait for AOAC devices to indicate power and clock OK */ do { udelay(100); status = true; for (i = 0; i < ARRAY_SIZE(aoac_devs); i++) - status &= is_aoac_device_enabled(aoac_devs[i].status); + status &= is_aoac_device_enabled(aoac_devs[i]); + status &= is_aoac_console_uart_enabled(); } while (!status); } @@ -513,11 +537,11 @@ if (gnvs == NULL) return; - gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2); - gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3); - gnvs->aoac.ic4e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C4); - gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0); - gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1); + gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C2); + gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C3); + gnvs->aoac.ic4e = is_aoac_device_enabled(FCH_AOAC_DEV_I2C4); + gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_DEV_UART0); + gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_DEV_UART1); /* Rely on these being in sync with devicetree */ sata = pcidev_path_on_root(SATA_DEVFN); gnvs->aoac.st_e = sata && sata->enabled ? 1 : 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/35296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffc87f39ebe38394a56d41bb0940e9701fd05db9 Gerrit-Change-Number: 35296 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Add NULL pointer debug messages to UPD
by Marshall Dawson (Code Review) 12 Sep '19

12 Sep '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35364 ) Change subject: drivers/intel/fsp2_0: Add NULL pointer debug messages to UPD ...................................................................... drivers/intel/fsp2_0: Add NULL pointer debug messages to UPD Check for a NULL pointer before displaying UPD information in case the new area wasn't allocated. Change-Id: I28febfb04c2e5e68c43a0db499686bbbcd80afef Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/drivers/intel/fsp2_0/upd_display.c 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/35364/1 diff --git a/src/drivers/intel/fsp2_0/upd_display.c b/src/drivers/intel/fsp2_0/upd_display.c index 363ee36..8f6f937 100644 --- a/src/drivers/intel/fsp2_0/upd_display.c +++ b/src/drivers/intel/fsp2_0/upd_display.c @@ -28,6 +28,11 @@ static void fspm_display_arch_params(const FSPM_ARCH_UPD *old, const FSPM_ARCH_UPD *new) { + if (!new) { + printk(BIOS_SPEW, "Skipping architectural UPD display for MemoryInit - no new value region\n"); + return; + } + /* Display the architectural parameters for MemoryInit */ printk(BIOS_SPEW, "Architectural UPD values for MemoryInit at: 0x%p\n", new); @@ -53,6 +58,11 @@ const FSPM_UPD *fspm_old_upd, const FSPM_UPD *fspm_new_upd) { + if (!fspm_new_upd) { + printk(BIOS_SPEW, "Skipping MemoryInit UPD values - no new value region\n"); + return; + } + printk(BIOS_SPEW, "UPD values for MemoryInit:\n"); hexdump(fspm_new_upd, sizeof(*fspm_new_upd)); } @@ -70,6 +80,11 @@ const FSPS_UPD *fsps_old_upd, const FSPS_UPD *fsps_new_upd) { + if (!fsps_new_upd) { + printk(BIOS_SPEW, "Skipping SiliconInit UPD values - no new value region\n"); + return; + } + printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); hexdump(fsps_new_upd, sizeof(*fsps_new_upd)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28febfb04c2e5e68c43a0db499686bbbcd80afef Gerrit-Change-Number: 35364 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/drallion: Update memory map
by Ivy Jian (Code Review) 12 Sep '19

12 Sep '19

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35304 ) Change subject: mb/google/drallion: Update memory map ...................................................................... mb/google/drallion: Update memory map This will increase ME region size and reduce the BIOS regsion size. BUG:b:140665483 TEST='compile successfully' Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Change-Id: I5be2580d280569421d0870a06f9b93124b564b6f --- M src/mainboard/google/drallion/chromeos.fmd 1 file changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/35304/1 diff --git a/src/mainboard/google/drallion/chromeos.fmd b/src/mainboard/google/drallion/chromeos.fmd index 78b12bd..8bab919 100644 --- a/src/mainboard/google/drallion/chromeos.fmd +++ b/src/mainboard/google/drallion/chromeos.fmd @@ -1,26 +1,26 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x402000 { + SI_ALL@0x0 0x438000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x100000 - SI_ME@0x101000 0x2fd000 - SI_PDR(PRESERVE)@0x3fe000 0x4000 + SI_ME@0x101000 0x333000 + SI_PDR(PRESERVE)@0x434000 0x4000 } - SI_BIOS@0x402000 0x1bfe000 { - RW_DIAG@0x0 0x12ce000 { - RW_LEGACY(CBFS)@0x0 0x12be000 - DIAG_NVRAM@0x12be000 0x10000 + SI_BIOS@0x438000 0x1bc8000 { + RW_DIAG@0x0 0x1298000 { + RW_LEGACY(CBFS)@0x0 0x1288000 + DIAG_NVRAM@0x1288000 0x10000 } - RW_SECTION_A@0x12ce000 0x280000 { + RW_SECTION_A@0x1298000 0x280000 { VBLOCK_A@0x0 0x10000 FW_MAIN_A(CBFS)@0x10000 0x26ffc0 RW_FWID_A@0x27ffc0 0x40 } - RW_SECTION_B@0x154e000 0x280000 { + RW_SECTION_B@0x1518000 0x280000 { VBLOCK_B@0x0 0x10000 FW_MAIN_B(CBFS)@0x10000 0x26ffc0 RW_FWID_B@0x27ffc0 0x40 } - RW_MISC@0x17ce000 0x30000 { + RW_MISC@0x1798000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 @@ -33,7 +33,7 @@ RW_VPD(PRESERVE)@0x28000 0x2000 RW_NVRAM(PRESERVE)@0x2a000 0x6000 } - WP_RO@0x17fe000 0x400000 { + WP_RO@0x17c8000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 { -- To view, visit https://review.coreboot.org/c/coreboot/+/35304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5be2580d280569421d0870a06f9b93124b564b6f Gerrit-Change-Number: 35304 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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