coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: intel/broadwell: Replace some __PRE_RAM__ use
by Kyösti Mälkki (Code Review) 13 Sep '19

13 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35381 ) Change subject: intel/broadwell: Replace some __PRE_RAM__ use ...................................................................... intel/broadwell: Replace some __PRE_RAM__ use Guards are required due to different PCI accessor signatures. Change-Id: I60e87f16a48565917f6ee9d05cc59d2b9373270c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/broadwell/pch.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/35381/1 diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index e555588..e6c2319 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -73,7 +73,7 @@ return SPIBAR32(SPIBAR_FDOD); } -#ifndef __PRE_RAM__ +#ifndef __SIMPLE_DEVICE__ /* Put device in D3Hot Power State */ static void pch_enable_d3hot(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/35381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60e87f16a48565917f6ee9d05cc59d2b9373270c Gerrit-Change-Number: 35381 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/haswell: Remove some __PRE_RAM__ use
by Kyösti Mälkki (Code Review) 13 Sep '19

13 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35380 ) Change subject: intel/haswell: Remove some __PRE_RAM__ use ...................................................................... intel/haswell: Remove some __PRE_RAM__ use Change-Id: I167e9a171af4fe7997ebb76cdfa22a4578817a55 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h 1 file changed, 1 insertion(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/35380/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index f786caf..4c67ba8 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -130,9 +130,6 @@ # error "CONFIG_IED_REGION_SIZE is not a power of 2" #endif -#if !defined(__ROMCC__) // FIXME romcc should handle below constructs - -#if defined(__PRE_RAM__) struct pei_data; struct rcba_config_instruction; struct romstage_params { @@ -142,18 +139,13 @@ void (*copy_spd)(struct pei_data *); }; void romstage_common(const struct romstage_params *params); -#endif -#ifdef __SMM__ /* Lock MSRs */ void intel_cpu_haswell_finalize_smm(void); -#else + /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -/* Determine if HyperThreading is disabled. The variable is not valid until - * setup_ap_init() has been called. */ -#endif /* CPU identification */ int haswell_family_model(void); @@ -161,5 +153,3 @@ int haswell_is_ult(void); #endif - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I167e9a171af4fe7997ebb76cdfa22a4578817a55 Gerrit-Change-Number: 35380 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel: Remove some __PRE_RAM__ use
by Kyösti Mälkki (Code Review) 13 Sep '19

13 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35379 ) Change subject: soc/intel: Remove some __PRE_RAM__ use ...................................................................... soc/intel: Remove some __PRE_RAM__ use Change-Id: I35b44967de4e8d9907dc887fe35407bcaf334adc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/fsp_broadwell_de/include/soc/romstage.h M src/soc/intel/quark/include/soc/romstage.h 3 files changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/35379/1 diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 93669f2..e86861c 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -16,10 +16,6 @@ #ifndef _BAYTRAIL_ROMSTAGE_H_ #define _BAYTRAIL_ROMSTAGE_H_ -#if !defined(__PRE_RAM__) -#error "Don't include romstage.h from a ramstage compilation unit!" -#endif - #include <stdint.h> #include <arch/cpu.h> #include <soc/mrc_wrapper.h> diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h b/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h index 63b7fba..6ee160d 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h @@ -17,10 +17,6 @@ #ifndef _SOC_ROMSTAGE_H_ #define _SOC_ROMSTAGE_H_ -#if !defined(__PRE_RAM__) -#error "Don't include romstage.h from a ramstage compilation unit!" -#endif - #include <stdint.h> #include <fsp.h> diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index 29f934e..453b4bb 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -18,10 +18,6 @@ #ifndef _QUARK_ROMSTAGE_H_ #define _QUARK_ROMSTAGE_H_ -#if !defined(__PRE_RAM__) -#error "Don't include romstage.h from a ramstage compilation unit!" -#endif - #include <soc/car.h> #include <soc/reg_access.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/35379 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35b44967de4e8d9907dc887fe35407bcaf334adc Gerrit-Change-Number: 35379 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch: Merge emmc_sku_gpio_table and gpio_table to one table
by Peichao Li (Code Review) 13 Sep '19

13 Sep '19

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35344 ) Change subject: mb/google/hatch: Merge emmc_sku_gpio_table and gpio_table to one table ...................................................................... mb/google/hatch: Merge emmc_sku_gpio_table and gpio_table to one table BUG=b:140008849, b:140573677 TEST=verify eMMC SKU and SSD SKU will bring up normally. Signed-off-by: Peichao Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I0c0adf569cc92e8b44ab72379420f2b190fa31f5 --- M src/mainboard/google/hatch/variants/akemi/gpio.c 1 file changed, 2 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/35344/1 diff --git a/src/mainboard/google/hatch/variants/akemi/gpio.c b/src/mainboard/google/hatch/variants/akemi/gpio.c index 27b49e5..b873754 100644 --- a/src/mainboard/google/hatch/variants/akemi/gpio.c +++ b/src/mainboard/google/hatch/variants/akemi/gpio.c @@ -90,77 +90,6 @@ PAD_CFG_GPI(GPP_H22, NONE, PLTRST), }; -static const struct pad_config emmc_sku_gpio_table[] = { - /* A0 : NC */ - PAD_NC(GPP_A0, NONE), - /* A6 : NC */ - PAD_NC(GPP_A6, NONE), - /* A8 : NC */ - PAD_NC(GPP_A8, NONE), - /* A10 : NC */ - PAD_NC(GPP_A10, NONE), - /* A11 : NC */ - PAD_NC(GPP_A11, NONE), - /* A12 : NC */ - PAD_NC(GPP_A12, NONE), - /* A18 : NC */ - PAD_NC(GPP_A18, NONE), - /* A19 : NC */ - PAD_NC(GPP_A19, NONE), - /* A22 : NC */ - PAD_NC(GPP_A22, NONE), - /* A23 : NC */ - PAD_NC(GPP_A23, NONE), - /* B20 : NC */ - PAD_NC(GPP_B20, NONE), - /* B21 : NC */ - PAD_NC(GPP_B21, NONE), - /* B22 : NC */ - PAD_NC(GPP_B22, NONE), - /* C11 : NC */ - PAD_NC(GPP_C11, NONE), - /* C15 : NC */ - PAD_NC(GPP_C15, NONE), - /* F1 : NC */ - PAD_NC(GPP_F1, NONE), - /* F3 : MEM_STRAP_3 */ - PAD_CFG_GPI(GPP_F3, NONE, PLTRST), - /* F10 : MEM_STRAP_2 */ - PAD_CFG_GPI(GPP_F10, NONE, PLTRST), - /* F11 : EMMC_CMD ==> EMMC_CMD */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), - /* F12 : EMMC_DATA0 ==> EMMC_DAT0 */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - /* F13 : EMMC_DATA1 ==> EMMC_DAT1 */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - /* F14 : EMMC_DATA2 ==> EMMC_DAT2 */ - PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), - /* F15 : EMMC_DATA3 ==> EMMC_DAT3 */ - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - /* F16 : EMMC_DATA4 ==> EMMC_DAT4 */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), - /* F17 : EMMC_DATA5 ==> EMMC_DAT5 */ - PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), - /* F18 : EMMC_DATA6 ==> EMMC_DAT6 */ - PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), - /* F19 : EMMC_DATA7 ==> EMMC_DAT7 */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* F20 : EMMC_RCLK ==> EMMC_RCLK */ - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - /* F21 : EMMC_CLK ==> EMMC_CLK */ - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - /* F22 : EMMC_RESET# ==> EMMC_RST_L */ - PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), - /* H6 : NC */ - PAD_NC(GPP_H6, NONE), - /* H7 : NC */ - PAD_NC(GPP_H7, NONE), - /* H19 : MEM_STRAP_0 */ - PAD_CFG_GPI(GPP_H19, NONE, PLTRST), - /* H22 : MEM_STRAP_1 */ - PAD_CFG_GPI(GPP_H22, NONE, PLTRST), -}; - static const struct pad_config gpio_table[] = { /* A0 : NC */ PAD_NC(GPP_A0, NONE), @@ -242,8 +171,8 @@ } /* For eMMC SKU */ if (sku_id == 1) { - *num = ARRAY_SIZE(emmc_sku_gpio_table); - return emmc_sku_gpio_table; + *num = ARRAY_SIZE(gpio_table); + return gpio_table; } *num = ARRAY_SIZE(gpio_table); return gpio_table; -- To view, visit https://review.coreboot.org/c/coreboot/+/35344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c0adf569cc92e8b44ab72379420f2b190fa31f5 Gerrit-Change-Number: 35344 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: emulation/qemu-i440fx/northbridge.c: replace macro with enum
by Name of user not set (Code Review) 13 Sep '19

13 Sep '19

Name of user not set #1002476 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35310 ) Change subject: emulation/qemu-i440fx/northbridge.c: replace macro with enum ...................................................................... emulation/qemu-i440fx/northbridge.c: replace macro with enum replace multiple existing FW_CFG_* defines with enum fw_cfg_enum. Change-Id: I9699df4aeb2d8b18f933bb9aaed16008d10158ad Signed-off-by: Himanshu Sahdev <himanshusah(a)hcl.com> --- M src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h 1 file changed, 28 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/35310/1 diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h index 46aee9b3d..5aac1cf 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h @@ -21,32 +21,34 @@ #include <stdint.h> -#define FW_CFG_SIGNATURE 0x00 -#define FW_CFG_ID 0x01 -#define FW_CFG_UUID 0x02 -#define FW_CFG_RAM_SIZE 0x03 -#define FW_CFG_NOGRAPHIC 0x04 -#define FW_CFG_NB_CPUS 0x05 -#define FW_CFG_MACHINE_ID 0x06 -#define FW_CFG_KERNEL_ADDR 0x07 -#define FW_CFG_KERNEL_SIZE 0x08 -#define FW_CFG_KERNEL_CMDLINE 0x09 -#define FW_CFG_INITRD_ADDR 0x0a -#define FW_CFG_INITRD_SIZE 0x0b -#define FW_CFG_BOOT_DEVICE 0x0c -#define FW_CFG_NUMA 0x0d -#define FW_CFG_BOOT_MENU 0x0e -#define FW_CFG_MAX_CPUS 0x0f -#define FW_CFG_KERNEL_ENTRY 0x10 -#define FW_CFG_KERNEL_DATA 0x11 -#define FW_CFG_INITRD_DATA 0x12 -#define FW_CFG_CMDLINE_ADDR 0x13 -#define FW_CFG_CMDLINE_SIZE 0x14 -#define FW_CFG_CMDLINE_DATA 0x15 -#define FW_CFG_SETUP_ADDR 0x16 -#define FW_CFG_SETUP_SIZE 0x17 -#define FW_CFG_SETUP_DATA 0x18 -#define FW_CFG_FILE_DIR 0x19 +enum fw_cfg_enum { + FW_CFG_SIGNATURE, + FW_CFG_ID, + FW_CFG_UUID, + FW_CFG_RAM_SIZE, + FW_CFG_NOGRAPHIC, + FW_CFG_NB_CPUS, + FW_CFG_MACHINE_ID, + FW_CFG_KERNEL_ADDR, + FW_CFG_KERNEL_SIZE, + FW_CFG_KERNEL_CMDLINE, + FW_CFG_INITRD_ADDR, + FW_CFG_INITRD_SIZE, + FW_CFG_BOOT_DEVICE, + FW_CFG_NUMA, + FW_CFG_BOOT_MENU, + FW_CFG_MAX_CPUS, + FW_CFG_KERNEL_ENTRY, + FW_CFG_KERNEL_DATA, + FW_CFG_INITRD_DATA, + FW_CFG_CMDLINE_ADDR, + FW_CFG_CMDLINE_SIZE, + FW_CFG_CMDLINE_DATA, + FW_CFG_SETUP_ADDR, + FW_CFG_SETUP_SIZE, + FW_CFG_SETUP_DATA, + FW_CFG_FILE_DIR +}; #define FW_CFG_FILE_FIRST 0x20 #define FW_CFG_FILE_SLOTS 0x10 -- To view, visit https://review.coreboot.org/c/coreboot/+/35310 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9699df4aeb2d8b18f933bb9aaed16008d10158ad Gerrit-Change-Number: 35310 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002476 Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Update southbridge
by Richard Spiegel (Code Review) 13 Sep '19

13 Sep '19

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33770 ) Change subject: soc/amd/picasso: Update southbridge ...................................................................... Patch Set 14: Code-Review+2 Sorry, only now noticed that you updated first than answered... I was waiting your update. -- To view, visit https://review.coreboot.org/c/coreboot/+/33770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69dfc4a875006639aa330385680d150331840e40 Gerrit-Change-Number: 33770 Gerrit-PatchSet: 14 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 13 Sep 2019 15:12:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/lenovo/t410: Add new port
by build bot (Jenkins) (Code Review) 13 Sep '19

13 Sep '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: mainboard/lenovo/t410: Add new port ...................................................................... Patch Set 15: (5 comments) https://review.coreboot.org/c/coreboot/+/11791/15/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/romstage.c: https://review.coreboot.org/c/coreboot/+/11791/15/src/mainboard/lenovo/t410… PS15, Line 140: unsigned i; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/c/coreboot/+/11791/15/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/smihandler.c: https://review.coreboot.org/c/coreboot/+/11791/15/src/mainboard/lenovo/t410… PS15, Line 35: switch (smif) { switch and case should be at the same indent https://review.coreboot.org/c/coreboot/+/11791/15/src/mainboard/lenovo/t410… PS15, Line 38: udelay(250000); long udelay - prefer mdelay; see arch/arm/include/asm/delay.h https://review.coreboot.org/c/coreboot/+/11791/15/src/mainboard/lenovo/t410… PS15, Line 71: switch (event) { switch and case should be at the same indent https://review.coreboot.org/c/coreboot/+/11791/15/src/mainboard/lenovo/t410… PS15, Line 98: switch (data) { switch and case should be at the same indent -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 15 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Degen Gerrit-CC: Matt Parnell <mparnell(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Fri, 13 Sep 2019 13:16:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/lenovo/t410: Add new port
by Patrick Rudolph (Code Review) 13 Sep '19

13 Sep '19

Patrick Rudolph has uploaded a new patch set (#15) to the change originally created by Nicolas Reinecke. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: mainboard/lenovo/t410: Add new port ...................................................................... mainboard/lenovo/t410: Add new port The port is based on the x201 / t410s. 2537-vg5 / i5, no discrete gpu Tested and working: * Native raminit * Native gfxinit * Booting Seabios 1.12.1 * Booting from EHCI * Running GNU/Linux 5.0.0 * No errors in dmesg * EHCI debug on the devices left side, bottom-right * Keyboard * Fn keys (Mute, Volume, Mic) * Touchpad * TPM * Wifi * Sound * USB * Ethernet Testing in progress. Untested: * VGA * Displayport Bugs: * Linux hangs in 2 out of 3 attempts when booting from USB * S3 resume is broken. * AC adapter can't be read from ACPI TODOs: * Hide internal PCI devices Details for flashing externally: 1. Disconnect all power 2. Connect the external flasher 3. Connect the power cord (This fixes internal power control) 4. Remove the power cord Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A src/mainboard/lenovo/t410/Kconfig A src/mainboard/lenovo/t410/Kconfig.name A src/mainboard/lenovo/t410/Makefile.inc A src/mainboard/lenovo/t410/acpi/dock.asl A src/mainboard/lenovo/t410/acpi/ec.asl A src/mainboard/lenovo/t410/acpi/gpe.asl A src/mainboard/lenovo/t410/acpi/platform.asl A src/mainboard/lenovo/t410/acpi/superio.asl A src/mainboard/lenovo/t410/acpi_tables.c A src/mainboard/lenovo/t410/board_info.txt A src/mainboard/lenovo/t410/cmos.default A src/mainboard/lenovo/t410/cmos.layout A src/mainboard/lenovo/t410/data.vbt A src/mainboard/lenovo/t410/devicetree.cb A src/mainboard/lenovo/t410/dock.c A src/mainboard/lenovo/t410/dock.h A src/mainboard/lenovo/t410/dsdt.asl A src/mainboard/lenovo/t410/gma-mainboard.ads A src/mainboard/lenovo/t410/gpio.c A src/mainboard/lenovo/t410/hda_verb.c A src/mainboard/lenovo/t410/mainboard.c A src/mainboard/lenovo/t410/romstage.c A src/mainboard/lenovo/t410/smi.h A src/mainboard/lenovo/t410/smihandler.c A src/mainboard/lenovo/t410/thermal.h 25 files changed, 1,918 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/11791/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 15 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Degen Gerrit-CC: Matt Parnell <mparnell(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp2_0: Allocate cfg_region_size for UPD
by Marshall Dawson (Code Review) 13 Sep '19

13 Sep '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35349 ) Change subject: drivers/intel/fsp2_0: Allocate cfg_region_size for UPD ...................................................................... drivers/intel/fsp2_0: Allocate cfg_region_size for UPD In FSP-S, the driver constructs its pointer to UPD using the offset in the header. The cfg_region_size should likewise be used for allocating memory and copying the default configuration. Make the change and add an error message in case there are more UPD definitions than cfg_region_size. TEST=Verify OK on Mandolin, verify a mock error condition BUG=b:140648081 Change-Id: I20fad0e27a2ad537898b6d01e5241e1508da690c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/drivers/intel/fsp2_0/silicon_init.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/35349/1 diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index e72e4ac..6a899bf 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -39,9 +39,11 @@ die_with_post_code(POST_INVALID_VENDOR_BINARY, "Invalid FSPS signature\n"); - upd = xmalloc(sizeof(FSPS_UPD)); + upd = xmalloc(hdr->cfg_region_size); - memcpy(upd, supd, sizeof(FSPS_UPD)); + memcpy(upd, supd, hdr->cfg_region_size); + if (hdr->image_size < sizeof(FSPS_UPD)) + printk(BIOS_ERR, "FSP error: more UPD specified than allowed by header cfg_region_size\n"); /* Give SoC/mainboard a chance to populate entries */ platform_fsp_silicon_init_params_cb(upd); -- To view, visit https://review.coreboot.org/c/coreboot/+/35349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20fad0e27a2ad537898b6d01e5241e1508da690c Gerrit-Change-Number: 35349 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/bootblock_crt0.S: Leverage eax in protected mode entry
by Name of user not set (Code Review) 13 Sep '19

13 Sep '19

Hello HIMANSHU SAHDEV, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35292 to review the following change. Change subject: arch/x86/bootblock_crt0.S: Leverage eax in protected mode entry ...................................................................... arch/x86/bootblock_crt0.S: Leverage eax in protected mode entry Leverage already used eax register in bootblock_protected_mode_entry. Avoid another register ebx just for preserving eax value as it is not used at all after the assignment. Allow EBX to be preserved for other usage. Change-Id: Ia668b78f2f97cf026692f1fe63ff8a382a162474 Signed-off-by: Himanshu Sahdev <himanshusah(a)hcl.com> --- M src/arch/x86/bootblock_crt0.S 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/35292/1 diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index ea55096..272a4eb 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -48,11 +48,10 @@ /* MMX registers required here */ /* BIST result in eax */ - movl %eax, %ebx + movd %eax, %mm0 /* Get an early timestamp */ rdtsc - movd %ebx, %mm0 movd %eax, %mm1 movd %edx, %mm2 #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia668b78f2f97cf026692f1fe63ff8a382a162474 Gerrit-Change-Number: 35292 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002476 Gerrit-Reviewer: HIMANSHU SAHDEV <sahdev.himan(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2019