coreboot-gerrit September 2019

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Change in coreboot[master]: Add Razer Blade Stealth (2016) H2U
by Mimoja (Code Review) 14 Sep '19

14 Sep '19

Hello Alexander Couzens, Christoph Pomaska, Angel Pons, Jonathan Neuschäfer, Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34475 to look at the new patch set (#39). Change subject: Add Razer Blade Stealth (2016) H2U ...................................................................... Add Razer Blade Stealth (2016) H2U The Razer Blade Stealth H2U is a KabyLake System using: - Intel KBL 7500U - ITE8528E SuperIO - Intel 600P Series NVMe SSD - Either four MT52L1G32D4PG (16GB) or MT52L512MB32D4PG (8GB) of soldered memory in dualchannel mode - (Optional) Touchscreen - HDMI 2.0a via DP-1: Paradetech PS175 Even though it has a 16MB chip equipped (W25Q128.V) only the first 8MB are used and mapped via IFD. The rest is left empty (0xFF). The flash is not secured in any way and can be read via flashrom. It should be the source for this port's IFD and ME blobs. Working: - USB-A Ports left and right - Speakers - Touchscreen (USB) - Onboard Keyboard in Linux - NVMe SSD - SeaBIOS, Tianocore and Grub Payloads - Webcam - Powersaving Modes - Battery state and LID switch, sometimes slow to update. - Touchpad (I2C-HID) - Headphones Not part of this commit: - Thunderbolt / USB-C (Requires advanced EC signaling) - Full HDMI support (Currently requires plugged connection at boot) Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> --- A src/mainboard/razer/Kconfig A src/mainboard/razer/Kconfig.name A src/mainboard/razer/blade_stealth_kbl/Kconfig A src/mainboard/razer/blade_stealth_kbl/Kconfig.name A src/mainboard/razer/blade_stealth_kbl/Makefile.inc A src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl A src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl A src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl A src/mainboard/razer/blade_stealth_kbl/acpi/mainboard.asl A src/mainboard/razer/blade_stealth_kbl/acpi/superio.asl A src/mainboard/razer/blade_stealth_kbl/acpi_tables.c A src/mainboard/razer/blade_stealth_kbl/board_info.txt A src/mainboard/razer/blade_stealth_kbl/devicetree.cb A src/mainboard/razer/blade_stealth_kbl/dsdt.asl A src/mainboard/razer/blade_stealth_kbl/gma-mainboard.ads A src/mainboard/razer/blade_stealth_kbl/gpio.h A src/mainboard/razer/blade_stealth_kbl/hda_verb.c A src/mainboard/razer/blade_stealth_kbl/mainboard.c A src/mainboard/razer/blade_stealth_kbl/ramstage.c A src/mainboard/razer/blade_stealth_kbl/romstage.c A src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc A src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex A src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex A src/mainboard/razer/blade_stealth_kbl/spd/spd.h A src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c 25 files changed, 1,268 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/34475/39 -- To view, visit https://review.coreboot.org/c/coreboot/+/34475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Gerrit-Change-Number: 34475 Gerrit-PatchSet: 39 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/asrock/h110m: configure SuperIO global registers
by Maxim Polyakov (Code Review) 14 Sep '19

14 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35386 ) Change subject: mb/asrock/h110m: configure SuperIO global registers ...................................................................... mb/asrock/h110m: configure SuperIO global registers Information based on superiotool dump. Change-Id: I24ae9b1a7eab3095518341354544efe613912a6a Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 15 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/35386/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 88a4edc..572cd6a 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -327,12 +327,22 @@ subsystemid 0x1849 0x1a43 chip superio/nuvoton/nct6791d device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # Parallel - # global - irq 0x1c = 0x10 + device pnp 2e.1 on + # Global Control Registers + # Device IRQ Polarity + irq 0x13 = 0x00 + irq 0x14 = 0x00 + # Global Option + irq 0x24 = 0xfb irq 0x27 = 0x10 - irq 0x2a = 0x64 - # parallel port + # Multi Function + irq 0x1a = 0xb0 + irq 0x1b = 0xe6 + irq 0x2a = 0x04 + irq 0x2c = 0x40 + irq 0x2d = 0x03 + + # Parallel Port io 0x60 = 0x0378 irq 0x70 = 7 drq 0x74 = 4 # No DMA -- To view, visit https://review.coreboot.org/c/coreboot/+/35386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24ae9b1a7eab3095518341354544efe613912a6a Gerrit-Change-Number: 35386 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asrock/h110m: configure GPIO in SuperIO chip
by Maxim Polyakov (Code Review) 14 Sep '19

14 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35378 ) Change subject: mb/asrock/h110m: configure GPIO in SuperIO chip ...................................................................... mb/asrock/h110m: configure GPIO in SuperIO chip Enables and configures GPIOs in the NCT6791D chip. This value is got from a superiotool dump. Change-Id: I5968a6c20cc013697d64bfbe4fc2e7b2390b72b0 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 30 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/35378/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 0b40dea..d5b5f68 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -353,18 +353,39 @@ irq 0x72 = 12 # Mouse end device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GPIO6 - device pnp 2e.107 off end # GPIO7 - device pnp 2e.207 off end # GPIO8 + device pnp 2e.7 off # GPIO6 + drq 0xf6 = 0xff + drq 0xf7 = 0xff + drq 0xf8 = 0xff + end + device pnp 2e.107 on # GPIO7 + drq 0xe0 = 0x7f + drq 0xe1 = 0x0d + end + device pnp 2e.207 off # GPIO8 + drq 0xe6 = 0xff + drq 0xe7 = 0xff + drq 0xed = 0xff + end device pnp 2e.8 off end # WDT - device pnp 2e.108 off end # GPIO0 + device pnp 2e.108 on end # GPIO0 device pnp 2e.308 off end # GPIO base device pnp 2e.408 off end # WDTMEM - device pnp 2e.708 off end # GPIO1 - device pnp 2e.9 off end # GPIO2 - device pnp 2e.109 off end # GPIO3 - device pnp 2e.209 off end # GPIO4 - device pnp 2e.309 off end # GPIO5 + device pnp 2e.708 on end # GPIO1 + device pnp 2e.9 on end # GPIO2 + device pnp 2e.109 on # GPIO3 + drq 0xe4 = 0x7b + drq 0xe5 = 0x02 + drq 0xea = 0x04 + end + device pnp 2e.209 on # GPIO4 + drq 0xf0 = 0x7f + drq 0xf1 = 0x80 + end + device pnp 2e.309 on # GPIO5 + drq 0xf4 = 0xdf + drq 0xf5 = 0xd5 + end device pnp 2e.a on # Power RAM in S3 and let the PCH # handle power failure actions -- To view, visit https://review.coreboot.org/c/coreboot/+/35378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5968a6c20cc013697d64bfbe4fc2e7b2390b72b0 Gerrit-Change-Number: 35378 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asrock/h110m: enable ACPI LDN in SuperIO
by Maxim Polyakov (Code Review) 14 Sep '19

14 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35370 ) Change subject: mb/asrock/h110m: enable ACPI LDN in SuperIO ...................................................................... mb/asrock/h110m: enable ACPI LDN in SuperIO Change-Id: Icbfec4dc82a1fbbfeb49c3dbd047509f5873d235 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/bootblock.c M src/mainboard/asrock/h110m/devicetree.cb 2 files changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/35370/1 diff --git a/src/mainboard/asrock/h110m/bootblock.c b/src/mainboard/asrock/h110m/bootblock.c index 96ce205..2fa70e1 100644 --- a/src/mainboard/asrock/h110m/bootblock.c +++ b/src/mainboard/asrock/h110m/bootblock.c @@ -18,12 +18,25 @@ #include <soc/gpio.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6791d/nct6791d.h> +#include <device/pnp_ops.h> #include "include/gpio.h" static void early_config_superio(void) { const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT6791D_SP1); + const pnp_devfn_t acpi_dev = PNP_DEV(0x2e, NCT6791D_ACPI); + nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + + nuvoton_pnp_enter_conf_state(acpi_dev); + + pnp_set_logical_device(acpi_dev); + /* Power RAM in S3 and let the PCH handle power failure actions */ + pnp_write_config(acpi_dev, 0xe4, 0x70); + /* Set Hardware Monitor reset source to LRESET# */ + pnp_write_config(acpi_dev, 0xe7, 0x01); + + nuvoton_pnp_exit_conf_state(acpi_dev); } static void early_config_gpio(void) diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 8ed3476..038f144 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -365,7 +365,7 @@ device pnp 2e.109 off end # GPIO3 device pnp 2e.209 off end # GPIO4 device pnp 2e.309 off end # GPIO5 - device pnp 2e.a off end # ACPI + device pnp 2e.a on end # ACPI device pnp 2e.b on # HWM, LED # HM base address io 0x60 = 0x0290 -- To view, visit https://review.coreboot.org/c/coreboot/+/35370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbfec4dc82a1fbbfeb49c3dbd047509f5873d235 Gerrit-Change-Number: 35370 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asrock/h110m: set I/O Range for SuperIO HWM
by Maxim Polyakov (Code Review) 14 Sep '19

14 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35369 ) Change subject: mb/asrock/h110m: set I/O Range for SuperIO HWM ...................................................................... mb/asrock/h110m: set I/O Range for SuperIO HWM Change-Id: I30de4f40f8ca87c54faee84053c4bb0f874b2884 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/35369/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 5af5cfc..8ed3476 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -33,6 +33,9 @@ register "gpe0_dw1" = "GPP_D" register "gpe0_dw2" = "GPP_E" + # Set @0x200-0x2ff I/O Range for SuperIO HWM + register "gen1_dec" = "0x00fc0201" + # Enable "Intel Speed Shift Technology" register "speed_shift_enable" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/35369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30de4f40f8ca87c54faee84053c4bb0f874b2884 Gerrit-Change-Number: 35369 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mediatek/mt8183: Add soc ARM Trusted Firmware support
by Hung-Te Lin (Code Review) 14 Sep '19

14 Sep '19

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29186 ) Change subject: mediatek/mt8183: Add soc ARM Trusted Firmware support ...................................................................... Patch Set 15: Try to rebase - in theory that should pass buildbot -- To view, visit https://review.coreboot.org/c/coreboot/+/29186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia988d2b4ed646027c04c7c6ff0e50ed7a0b14da3 Gerrit-Change-Number: 29186 Gerrit-PatchSet: 15 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Erin Lo <erin.lo(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: jitao shi <jitao.shi(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 14 Sep 2019 05:18:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arm64: Uprev Arm TF and adjust to BL31 parameter changes
by Julius Werner (Code Review) 14 Sep '19

14 Sep '19

Hello Patrick Rudolph, Hung-Te Lin, Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34676 to review the following change. Change subject: arm64: Uprev Arm TF and adjust to BL31 parameter changes ...................................................................... arm64: Uprev Arm TF and adjust to BL31 parameter changes This patch uprevs the Arm Trusted Firmware submodule to the new upstream master (commit 3ee48f40f5). Arm Trusted Firmware unfinied a bunch of stuff related to BL31 handoff parameters across platforms which involved changing a few names around. This patch syncs coreboot back up with that. They also made header changes that now allow us to directly include all the headers we need (in a safer and cleaner way than before), so we can get rid of some structure definitions that were duplicated. Since the version of entry point info parameters we have been using has been deprecated in Trusted Firmware, this patch switches to the new version 2 parameter format. (Also rename arm_tf.c to bl31.c because I'm getting annoyed with the auto-completion clashes it keeps causing.) Change-Id: I0ed32bce5585ce191736f0ff2e5a94a9d2b2cc28 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M 3rdparty/arm-trusted-firmware M src/arch/arm64/Makefile.inc D src/arch/arm64/arm_tf.c A src/arch/arm64/bl31.c M src/arch/arm64/boot.c D src/arch/arm64/include/arm_tf.h D src/arch/arm64/include/arm_tf_temp.h A src/arch/arm64/include/bl31.h M src/mainboard/google/gru/mainboard.c M src/soc/cavium/cn81xx/bl31_plat_params.c M src/soc/cavium/cn81xx/include/soc/bl31_plat_params.h M src/soc/cavium/cn81xx/soc.c D src/soc/mediatek/mt8173/bl31_plat_params.c M src/soc/nvidia/tegra210/arm_tf.c M src/soc/rockchip/rk3399/Makefile.inc D src/soc/rockchip/rk3399/bl31_plat_params.c D src/soc/rockchip/rk3399/include/soc/bl31_plat_params.h 17 files changed, 197 insertions(+), 348 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/34676/1 diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware index 693e278..3ee48f4 160000 --- a/3rdparty/arm-trusted-firmware +++ b/3rdparty/arm-trusted-firmware @@ -1 +1 @@ -Subproject commit 693e278e308441d716f7f5116c43aa150955da31 +Subproject commit 3ee48f40f50bd3cea6fbb824bbc5ce0a43802d78 diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 6bb7196..2f862da 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -135,7 +135,7 @@ ramstage-y += memset.S ramstage-y += memcpy.S ramstage-y += memmove.S -ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += arm_tf.c +ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31.c ramstage-y += transition.c transition_asm.S ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c deleted file mode 100644 index 291e4ee..0000000 --- a/src/arch/arm64/arm_tf.c +++ /dev/null @@ -1,92 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cache.h> -#include <arch/lib_helpers.h> -#include <arch/mmu.h> -#include <arch/transition.h> -#include <arm_tf.h> -#include <bootmem.h> -#include <cbfs.h> -#include <console/console.h> -#include <program_loading.h> - -/* - * TODO: Many of these structures are currently unused. Better not fill them out - * to make future changes fail fast, rather than try to come up with content - * that might turn out to not make sense. Implement later as required. - * -static image_info_t bl31_image_info; -static image_info_t bl32_image_info; -static image_info_t bl33_image_info; - */ -static entry_point_info_t bl32_ep_info; -static entry_point_info_t bl33_ep_info; -static bl31_params_t bl31_params; - -void __weak *soc_get_bl31_plat_params(bl31_params_t *params) -{ - /* Default weak implementation. */ - return NULL; -} - -void arm_tf_run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr) -{ - struct prog bl31 = PROG_INIT(PROG_BL31, CONFIG_CBFS_PREFIX"/bl31"); - void (*bl31_entry)(bl31_params_t *params, void *plat_params) = NULL; - - if (prog_locate(&bl31)) - die("BL31 not found"); - - if (!selfload_check(&bl31, BM_MEM_BL31)) - die("BL31 load failed"); - bl31_entry = prog_entry(&bl31); - - SET_PARAM_HEAD(&bl31_params, PARAM_BL31, VERSION_1, 0); - - if (CONFIG(ARM64_USE_SECURE_OS)) { - struct prog bl32 = PROG_INIT(PROG_BL32, - CONFIG_CBFS_PREFIX"/secure_os"); - - if (prog_locate(&bl32)) - die("BL32 not found"); - - if (cbfs_prog_stage_load(&bl32)) - die("BL32 load failed"); - - SET_PARAM_HEAD(&bl32_ep_info, PARAM_EP, VERSION_1, - PARAM_EP_SECURE); - bl32_ep_info.pc = (uintptr_t)prog_entry(&bl32); - bl32_ep_info.spsr = SPSR_EXCEPTION_MASK | - get_eret_el(EL1, SPSR_USE_L); - bl31_params.bl32_ep_info = &bl32_ep_info; - } - - bl31_params.bl33_ep_info = &bl33_ep_info; - - SET_PARAM_HEAD(&bl33_ep_info, PARAM_EP, VERSION_1, PARAM_EP_NON_SECURE); - bl33_ep_info.pc = payload_entry; - bl33_ep_info.spsr = payload_spsr; - bl33_ep_info.args.arg0 = payload_arg0; - - /* May update bl31_params if necessary. */ - void *bl31_plat_params = soc_get_bl31_plat_params(&bl31_params); - - /* MMU disable will flush cache, so passed params land in memory. */ - raw_write_daif(SPSR_EXCEPTION_MASK); - mmu_disable(); - bl31_entry(&bl31_params, bl31_plat_params); - die("BL31 returned!"); -} diff --git a/src/arch/arm64/bl31.c b/src/arch/arm64/bl31.c new file mode 100644 index 0000000..33d79f6 --- /dev/null +++ b/src/arch/arm64/bl31.c @@ -0,0 +1,127 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cache.h> +#include <arch/lib_helpers.h> +#include <arch/mmu.h> +#include <arch/transition.h> +#include <bl31.h> +#include <bootmem.h> +#include <cbfs.h> +#include <cbmem.h> +#include <console/console.h> +#include <program_loading.h> + +#include <arm-trusted-firmware/include/export/common/bl_common_exp.h> + +static entry_point_info_t bl32_ep_info = { + .h = { + .type = PARAM_EP, + .version = PARAM_VERSION_1, + .size = sizeof(bl32_ep_info), + .attr = EP_SECURE, + }, +}; +static entry_point_info_t bl33_ep_info = { + .h = { + .type = PARAM_EP, + .version = PARAM_VERSION_1, + .size = sizeof(bl33_ep_info), + .attr = EP_NON_SECURE, + }, +}; + +static bl_params_node_t bl32_params_node = { + .image_id = BL32_IMAGE_ID, + .ep_info = &bl32_ep_info, +}; +static bl_params_node_t bl33_params_node = { + .image_id = BL33_IMAGE_ID, + .ep_info = &bl33_ep_info, +}; + +static bl_params_t bl_params = { + .h = { + .type = PARAM_BL_PARAMS, + .version = PARAM_VERSION_2, + .size = sizeof(bl_params), + .attr = 0, + }, + .head = &bl33_params_node, +}; + +static struct bl_aux_param_header *bl_aux_params; + +/* Only works when using the default soc_get_bl31_plat_params() below. */ +void register_bl31_aux_param(struct bl_aux_param_header *param) +{ + param->next = (uintptr_t)bl_aux_params; + bl_aux_params = param; +} + +/* Default implementation. All newly added SoCs should use this if possible! */ +__weak void *soc_get_bl31_plat_params(void) +{ + static struct bl_aux_param_uint64 cbtable_param = { + .h = { .type = BL_AUX_PARAM_COREBOOT_TABLE, }, + }; + if (!cbtable_param.value) { + cbtable_param.value = (uint64_t)cbmem_find(CBMEM_ID_CBTABLE); + if (cbtable_param.value) + register_bl31_aux_param(&cbtable_param.h); + } + return bl_aux_params; +} + +void run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr) +{ + struct prog bl31 = PROG_INIT(PROG_BL31, CONFIG_CBFS_PREFIX"/bl31"); + void (*bl31_entry)(bl_params_t *params, void *plat_params) = NULL; + + if (prog_locate(&bl31)) + die("BL31 not found"); + + if (!selfload_check(&bl31, BM_MEM_BL31)) + die("BL31 load failed"); + bl31_entry = prog_entry(&bl31); + + if (CONFIG(ARM64_USE_SECURE_OS)) { + struct prog bl32 = PROG_INIT(PROG_BL32, + CONFIG_CBFS_PREFIX"/secure_os"); + + if (prog_locate(&bl32)) + die("BL32 not found"); + + if (cbfs_prog_stage_load(&bl32)) + die("BL32 load failed"); + + bl32_ep_info.pc = (uintptr_t)prog_entry(&bl32); + bl32_ep_info.spsr = SPSR_EXCEPTION_MASK | + get_eret_el(EL1, SPSR_USE_L); + bl33_params_node.next_params_info = &bl32_params_node; + } + + bl33_ep_info.pc = payload_entry; + bl33_ep_info.spsr = payload_spsr; + bl33_ep_info.args.arg0 = payload_arg0; + + void *bl31_plat_params = soc_get_bl31_plat_params(); + + /* MMU disable will flush cache, so passed params land in memory. */ + raw_write_daif(SPSR_EXCEPTION_MASK); + mmu_disable(); + bl31_entry(&bl_params, bl31_plat_params); + die("BL31 returned!"); +} diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index 7fbc525..2c3d243 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -17,7 +17,7 @@ #include <arch/lib_helpers.h> #include <arch/stages.h> #include <arch/transition.h> -#include <arm_tf.h> +#include <bl31.h> #include <program_loading.h> static void run_payload(struct prog *prog) @@ -30,7 +30,7 @@ u64 payload_spsr = get_eret_el(EL2, SPSR_USE_L); if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE)) - arm_tf_run_bl31((u64)doit, (u64)arg, payload_spsr); + run_bl31((u64)doit, (u64)arg, payload_spsr); else transition_to_el2(doit, arg, payload_spsr); } diff --git a/src/arch/arm64/include/arm_tf.h b/src/arch/arm64/include/arm_tf.h deleted file mode 100644 index ea5a0f4..0000000 --- a/src/arch/arm64/include/arm_tf.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ARM_TF_H__ -#define __ARM_TF_H__ - -#include <types.h> - -/* TODO: Pull in directly from ARM TF once its headers have been reorganized. */ -#include <arm_tf_temp.h> - -/* Load and enter BL31, set it up to exit to payload according to arguments. */ -void arm_tf_run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr); - -/* Return platform-specific bl31_plat_params. May update bl31_params. */ -void *soc_get_bl31_plat_params(bl31_params_t *bl31_params); - -#endif /* __ARM_TF_H__ */ diff --git a/src/arch/arm64/include/arm_tf_temp.h b/src/arch/arm64/include/arm_tf_temp.h deleted file mode 100644 index 8db5dcb..0000000 --- a/src/arch/arm64/include/arm_tf_temp.h +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __ARM_TF_TEMP_H__ -#define __ARM_TF_TEMP_H__ - -#include <types.h> - -/* - * Code temporarily copied from arm-trusted-firmware/include/common/bl_common.h, - * since it tries to pull in a few too many standard C headers and needs to be - * cleaned up a bit before we can include it directly. - */ - -#define PARAM_EP_SECURE 0x0 -#define PARAM_EP_NON_SECURE 0x1 -#define PARAM_EP_SECURITY_MASK 0x1 - -#define PARAM_EP_EE_MASK 0x2 -#define PARAM_EP_EE_LITTLE 0x0 -#define PARAM_EP_EE_BIG 0x2 - -#define PARAM_EP_ST_MASK 0x4 -#define PARAM_EP_ST_DISABLE 0x0 -#define PARAM_EP_ST_ENABLE 0x4 - -#define PARAM_EP 0x01 -#define PARAM_IMAGE_BINARY 0x02 -#define PARAM_BL31 0x03 - -#define VERSION_1 0x01 - -#define SET_PARAM_HEAD(_p, _type, _ver, _attr) do { \ - (_p)->h.type = (uint8_t)(_type); \ - (_p)->h.version = (uint8_t)(_ver); \ - (_p)->h.size = (uint16_t)sizeof(*_p); \ - (_p)->h.attr = (uint32_t)(_attr) ; \ - } while (0) - -typedef struct aapcs64_params { - unsigned long arg0; - unsigned long arg1; - unsigned long arg2; - unsigned long arg3; - unsigned long arg4; - unsigned long arg5; - unsigned long arg6; - unsigned long arg7; -} aapcs64_params_t; - -typedef struct param_header { - uint8_t type; /* type of the structure */ - uint8_t version; /* version of this structure */ - uint16_t size; /* size of this structure in bytes */ - uint32_t attr; /* attributes: unused bits SBZ */ -} param_header_t; - -typedef struct entry_point_info { - param_header_t h; - uintptr_t pc; - uint32_t spsr; - aapcs64_params_t args; -} entry_point_info_t; - -typedef struct image_info { - param_header_t h; - uintptr_t image_base; /* physical address of base of image */ - uint32_t image_size; /* bytes read from image file */ -} image_info_t; - -typedef struct bl31_params { - param_header_t h; - image_info_t *bl31_image_info; - entry_point_info_t *bl32_ep_info; - image_info_t *bl32_image_info; - entry_point_info_t *bl33_ep_info; - image_info_t *bl33_image_info; -} bl31_params_t; - -#endif /* __ARM_TF_TEMP_H__ */ diff --git a/src/arch/arm64/include/bl31.h b/src/arch/arm64/include/bl31.h new file mode 100644 index 0000000..97b6da3 --- /dev/null +++ b/src/arch/arm64/include/bl31.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __BL31_H__ +#define __BL31_H__ + +#include <types.h> + +#include <arm-trusted-firmware/include/export/lib/bl_aux_params/bl_aux_params_exp.h> + +/* Load and enter BL31, set it up to exit to payload according to arguments. */ +void run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr); + +/* Return platform-specific bl31_plat_params. SoCs should avoid overriding this + and stick with the default BL aux parameter framework if possible. */ +void *soc_get_bl31_plat_params(void); + +/* Add a BL aux parameter to the list to be passed to BL31. Only works for SoCs + that use the default soc_get_bl31_plat_params() implementation. */ +void register_bl31_aux_param(struct bl_aux_param_header *param); + +#endif /* __BL31_H__ */ diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 19f4ecc..4ebe143 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -15,6 +15,7 @@ */ #include <assert.h> +#include <bl31.h> #include <boardid.h> #include <console/console.h> #include <device/mmio.h> @@ -23,7 +24,6 @@ #include <device/i2c_simple.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> -#include <soc/bl31_plat_params.h> #include <soc/clock.h> #include <soc/display.h> #include <soc/grf.h> @@ -35,6 +35,8 @@ #include "board.h" +#include <arm-trusted-firmware/include/export/plat/rockchip/common/plat_params_exp.h> + /* * We have to drive the stronger pull-up within 1 second of powering up the * touchpad to prevent its firmware from falling into recovery. Not on @@ -71,9 +73,9 @@ static void register_apio_suspend(void) { - static struct bl31_apio_param param_apio = { + static struct bl_aux_param_rk_apio param_apio = { .h = { - .type = PARAM_SUSPEND_APIO, + .type = BL_AUX_PARAM_RK_SUSPEND_APIO, }, .apio = { .apio1 = 1, @@ -83,7 +85,7 @@ .apio5 = 1, }, }; - register_bl31_param(&param_apio.h); + register_bl31_aux_param(&param_apio.h); } static void register_gpio_suspend(void) @@ -98,34 +100,34 @@ * so we skip them. */ if (!CONFIG(GRU_BASEBOARD_SCARLET)) { - static struct bl31_gpio_param param_p15_en = { - .h = { .type = PARAM_SUSPEND_GPIO }, - .gpio = { .polarity = BL31_GPIO_LEVEL_LOW }, + static struct bl_aux_param_gpio param_p15_en = { + .h = { .type = BL_AUX_PARAM_RK_SUSPEND_GPIO }, + .gpio = { .polarity = ARM_TF_GPIO_LEVEL_LOW }, }; param_p15_en.gpio.index = GPIO_P15V_EN.raw; - register_bl31_param(&param_p15_en.h); + register_bl31_aux_param(&param_p15_en.h); - static struct bl31_gpio_param param_p18_audio_en = { - .h = { .type = PARAM_SUSPEND_GPIO }, - .gpio = { .polarity = BL31_GPIO_LEVEL_LOW }, + static struct bl_aux_param_gpio param_p18_audio_en = { + .h = { .type = BL_AUX_PARAM_RK_SUSPEND_GPIO }, + .gpio = { .polarity = ARM_TF_GPIO_LEVEL_LOW }, }; param_p18_audio_en.gpio.index = GPIO_P18V_AUDIO_PWREN.raw; - register_bl31_param(&param_p18_audio_en.h); + register_bl31_aux_param(&param_p18_audio_en.h); } - static struct bl31_gpio_param param_p30_en = { - .h = { .type = PARAM_SUSPEND_GPIO }, - .gpio = { .polarity = BL31_GPIO_LEVEL_LOW }, + static struct bl_aux_param_gpio param_p30_en = { + .h = { .type = BL_AUX_PARAM_RK_SUSPEND_GPIO }, + .gpio = { .polarity = ARM_TF_GPIO_LEVEL_LOW }, }; param_p30_en.gpio.index = GPIO_P30V_EN.raw; - register_bl31_param(&param_p30_en.h); + register_bl31_aux_param(&param_p30_en.h); } static void register_reset_to_bl31(void) { - static struct bl31_gpio_param param_reset = { + static struct bl_aux_param_gpio param_reset = { .h = { - .type = PARAM_RESET, + .type = BL_AUX_PARAM_RK_RESET_GPIO, }, .gpio = { .polarity = 1, @@ -135,14 +137,14 @@ /* gru/kevin reset pin: gpio0b3 */ param_reset.gpio.index = GPIO_RESET.raw, - register_bl31_param(&param_reset.h); + register_bl31_aux_param(&param_reset.h); } static void register_poweroff_to_bl31(void) { - static struct bl31_gpio_param param_poweroff = { + static struct bl_aux_param_gpio param_poweroff = { .h = { - .type = PARAM_POWEROFF, + .type = BL_AUX_PARAM_RK_POWEROFF_GPIO, }, .gpio = { .polarity = 1, @@ -156,7 +158,7 @@ */ param_poweroff.gpio.index = GPIO_POWEROFF.raw, - register_bl31_param(&param_poweroff.h); + register_bl31_aux_param(&param_poweroff.h); } static void configure_sdmmc(void) diff --git a/src/soc/cavium/cn81xx/bl31_plat_params.c b/src/soc/cavium/cn81xx/bl31_plat_params.c index 5d4dead..661f3ef 100644 --- a/src/soc/cavium/cn81xx/bl31_plat_params.c +++ b/src/soc/cavium/cn81xx/bl31_plat_params.c @@ -14,13 +14,13 @@ * */ -#include <arm_tf.h> #include <assert.h> +#include <bl31.h> #include <soc/bl31_plat_params.h> static struct bl31_plat_param *plat_params; -void register_bl31_param(struct bl31_plat_param *param) +void cn81xx_register_bl31_param(struct bl31_plat_param *param) { ASSERT(param); @@ -28,7 +28,7 @@ plat_params = param; } -void *soc_get_bl31_plat_params(bl31_params_t *bl31_params) +void *soc_get_bl31_plat_params(void) { return plat_params; } diff --git a/src/soc/cavium/cn81xx/include/soc/bl31_plat_params.h b/src/soc/cavium/cn81xx/include/soc/bl31_plat_params.h index f365aad..e47de89 100644 --- a/src/soc/cavium/cn81xx/include/soc/bl31_plat_params.h +++ b/src/soc/cavium/cn81xx/include/soc/bl31_plat_params.h @@ -19,6 +19,6 @@ #include <atf/plat_params.h> -void register_bl31_param(struct bl31_plat_param *param); +void cn81xx_register_bl31_param(struct bl31_plat_param *param); #endif/* __BL31_PLAT_PARAMS_H__ */ diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index f1e11d3..8abb328 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -354,7 +354,7 @@ /* Point to devicetree in secure memory */ fdt_param.fdt_ptr = (uintptr_t)_sff8104; - register_bl31_param(&fdt_param.h); + cn81xx_register_bl31_param(&fdt_param.h); static struct bl31_u64_param cbtable_param = { .h = { .type = PARAM_COREBOOT_TABLE, }, @@ -362,7 +362,7 @@ /* Point to coreboot tables */ cbtable_param.value = (uint64_t)cbmem_find(CBMEM_ID_CBTABLE); if (cbtable_param.value) - register_bl31_param(&cbtable_param.h); + cn81xx_register_bl31_param(&cbtable_param.h); } static void soc_init(struct device *dev) diff --git a/src/soc/mediatek/mt8173/bl31_plat_params.c b/src/soc/mediatek/mt8173/bl31_plat_params.c deleted file mode 100644 index 245866a..0000000 --- a/src/soc/mediatek/mt8173/bl31_plat_params.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 MediaTek Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <arm_tf.h> - -void *soc_get_bl31_plat_params(bl31_params_t *bl31_params) -{ - return NULL; -} diff --git a/src/soc/nvidia/tegra210/arm_tf.c b/src/soc/nvidia/tegra210/arm_tf.c index 38bb8bf..e0863d2 100644 --- a/src/soc/nvidia/tegra210/arm_tf.c +++ b/src/soc/nvidia/tegra210/arm_tf.c @@ -14,8 +14,8 @@ */ #include <arch/cache.h> -#include <arm_tf.h> #include <assert.h> +#include <bl31.h> #include <soc/addressmap.h> #include <soc/console_uart.h> #include <symbols.h> @@ -32,7 +32,7 @@ static bl31_plat_params_t t210_plat_params; -void *soc_get_bl31_plat_params(bl31_params_t *params) +void *soc_get_bl31_plat_params(void) { uintptr_t tz_base_mib; size_t tz_size_mib; diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 854eb84..3b66247 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -76,7 +76,6 @@ ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ../common/vop.c ramstage-y += usb.c -ramstage-y += bl31_plat_params.c BL31_MAKEARGS += PLAT=rk3399 M0_CROSS_COMPILE="$(CROSS_COMPILE_arm)" ################################################################################ diff --git a/src/soc/rockchip/rk3399/bl31_plat_params.c b/src/soc/rockchip/rk3399/bl31_plat_params.c deleted file mode 100644 index 9c11552..0000000 --- a/src/soc/rockchip/rk3399/bl31_plat_params.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <arm_tf.h> -#include <cbmem.h> -#include <soc/bl31_plat_params.h> - -static struct bl31_plat_param *plat_params; - -void register_bl31_param(struct bl31_plat_param *param) -{ - param->next = plat_params; - plat_params = param; -} - -void *soc_get_bl31_plat_params(bl31_params_t *bl31_params) -{ - static struct bl31_u64_param cbtable_param = { - .h = { .type = PARAM_COREBOOT_TABLE, }, - }; - if (!cbtable_param.value) { - cbtable_param.value = (uint64_t)cbmem_find(CBMEM_ID_CBTABLE); - if (cbtable_param.value) - register_bl31_param(&cbtable_param.h); - } - return plat_params; -} diff --git a/src/soc/rockchip/rk3399/include/soc/bl31_plat_params.h b/src/soc/rockchip/rk3399/include/soc/bl31_plat_params.h deleted file mode 100644 index c73d687..0000000 --- a/src/soc/rockchip/rk3399/include/soc/bl31_plat_params.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Rockchip Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef __BL31_PLAT_PARAMS_H__ -#define __BL31_PLAT_PARAMS_H__ - -#include <arm-trusted-firmware/plat/rockchip/common/include/plat_params.h> - -void register_bl31_param(struct bl31_plat_param *param); - -#endif/* __BL31_PLAT_PARAMS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34676 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ed32bce5585ce191736f0ff2e5a94a9d2b2cc28 Gerrit-Change-Number: 34676 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 16

Change in coreboot[master]: timestamps: Remove TIMESTAMP_CACHE_IN_BSS
by Kyösti Mälkki (Code Review) 13 Sep '19

13 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35375 ) Change subject: timestamps: Remove TIMESTAMP_CACHE_IN_BSS ...................................................................... timestamps: Remove TIMESTAMP_CACHE_IN_BSS This was implemented for LATE_CBMEM_INIT support which has already been deprecated. Change-Id: I39225ba675bc3389e051e15b400a905431969715 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/lib/timestamp.c 1 file changed, 10 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/35375/1 diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index ecfa274..03a46c6 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -27,34 +27,9 @@ #define MAX_TIMESTAMPS 192 -/* When changing this number, adjust TIMESTAMP() size ASSERT() in memlayout.h */ -#define MAX_BSS_TIMESTAMP_CACHE 16 - -struct __packed timestamp_cache { - struct timestamp_table table; - /* The struct timestamp_table has a 0 length array as its last field. - * The following 'entries' array serves as the storage space for the - * cache when allocated in the BSS. */ - struct timestamp_entry entries[MAX_BSS_TIMESTAMP_CACHE]; -}; - DECLARE_OPTIONAL_REGION(timestamp); -#if ENV_ROMSTAGE_OR_BEFORE -#define USE_TIMESTAMP_REGION (REGION_SIZE(timestamp) > 0) -#else -#define USE_TIMESTAMP_REGION 0 -#endif - -/* Currently we never store timestamp cache in .bss. */ -#define TIMESTAMP_CACHE_IN_BSS 0 - -/* - * Storage of cache entries prior to cbmem coming online. - */ -static struct timestamp_cache timestamp_cache; - -/* This points to the active timestamp_table and can change within a stage. +/* This points to the active timestamp_table and can change within a stage as CBMEM comes available. */ static struct timestamp_table *glob_ts_table CAR_GLOBAL; @@ -62,24 +37,22 @@ uint64_t base) { ts_cache->num_entries = 0; - ts_cache->max_entries = MAX_BSS_TIMESTAMP_CACHE; ts_cache->base_time = base; - - if (USE_TIMESTAMP_REGION) - ts_cache->max_entries = (REGION_SIZE(timestamp) - - offsetof(struct timestamp_table, entries)) - / sizeof(struct timestamp_entry); + ts_cache->max_entries = (REGION_SIZE(timestamp) - + offsetof(struct timestamp_table, entries)) + / sizeof(struct timestamp_entry); } static struct timestamp_table *timestamp_cache_get(void) { struct timestamp_table *ts_cache = NULL; - if (TIMESTAMP_CACHE_IN_BSS) { - ts_cache = &timestamp_cache.table; - } else if (USE_TIMESTAMP_REGION) { - if (REGION_SIZE(timestamp) < sizeof(*ts_cache)) - BUG(); + if (!ENV_ROMSTAGE_OR_BEFORE) + return NULL; + + if (REGION_SIZE(timestamp) < sizeof(*ts_cache)) { + BUG(); + } else { ts_cache = (void *)_timestamp; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39225ba675bc3389e051e15b400a905431969715 Gerrit-Change-Number: 35375 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 13

Change in coreboot[master]: timestamps: Further simplify timestamp_reinit()
by Kyösti Mälkki (Code Review) 13 Sep '19

13 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35374 ) Change subject: timestamps: Further simplify timestamp_reinit() ...................................................................... timestamps: Further simplify timestamp_reinit() Change-Id: I089a84b372893fb3018a796fb1e16cd58753bdf4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/lib/timestamp.c 1 file changed, 9 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/35374/1 diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index db73f15..ecfa274 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -265,21 +265,16 @@ if (!timestamp_should_run()) return; - /* cbmem is being recovered. */ - if (is_recovery) { - /* x86 resume path expects timestamps to be reset. */ - if (CONFIG(ARCH_ROMSTAGE_X86_32) && ENV_ROMSTAGE) - ts_cbmem_table = timestamp_alloc_cbmem_table(); - else { - /* Find existing table in cbmem. */ - ts_cbmem_table = cbmem_find(CBMEM_ID_TIMESTAMP); - /* No existing timestamp table. */ - if (ts_cbmem_table == NULL) - ts_cbmem_table = timestamp_alloc_cbmem_table(); - } - } else - /* First time sync. Add new table. */ + /* First time sync or ARCH_X86 S3 resume. Add new table. */ + if (ENV_ROMSTAGE || !is_recovery) { ts_cbmem_table = timestamp_alloc_cbmem_table(); + } else { + /* Find existing table in cbmem. */ + ts_cbmem_table = cbmem_find(CBMEM_ID_TIMESTAMP); + /* No existing timestamp table. */ + if (ts_cbmem_table == NULL) + ts_cbmem_table = timestamp_alloc_cbmem_table(); + } if (ts_cbmem_table == NULL) { printk(BIOS_ERR, "ERROR: No timestamp table allocated\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/35374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I089a84b372893fb3018a796fb1e16cd58753bdf4 Gerrit-Change-Number: 35374 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: drivers/pc80: Remove some __PRE_RAM__ and __SMM__
by Kyösti Mälkki (Code Review) 13 Sep '19

13 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35388 ) Change subject: drivers/pc80: Remove some __PRE_RAM__ and __SMM__ ...................................................................... drivers/pc80: Remove some __PRE_RAM__ and __SMM__ Change-Id: Ic90df69c27d524086405238b9683a69771c1b9d5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/pc80/rtc/mc146818rtc.c 1 file changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35388/1 diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index e0869a9..9ea5414 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -100,7 +100,6 @@ #define RTC_CONTROL_DEFAULT (RTC_24H) #define RTC_FREQ_SELECT_DEFAULT (RTC_REF_CLCK_32KHZ | RTC_RATE_1024HZ) -#ifndef __SMM__ static bool __cmos_init(bool invalid) { bool cmos_invalid; @@ -109,16 +108,14 @@ size_t i; uint8_t x; -#ifndef __PRE_RAM__ /* * Avoid clearing pending interrupts and resetting the RTC control * register in the resume path because the Linux kernel relies on * this to know if it should restart the RTC timer queue if the wake * was due to the RTC alarm. */ - if (acpi_is_wakeup_s3()) + if (ENV_RAMSTAGE && acpi_is_wakeup_s3()) return false; -#endif /* __PRE_RAM__ */ printk(BIOS_DEBUG, "RTC Init\n"); @@ -200,13 +197,14 @@ void cmos_init(bool invalid) { + if (ENV_SMM) + return; + if (CONFIG(VBOOT_VBNV_CMOS)) cmos_init_vbnv(invalid); else __cmos_init(invalid); } -#endif /* __SMM__ */ - /* * This routine returns the value of the requested bits. -- To view, visit https://review.coreboot.org/c/coreboot/+/35388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic90df69c27d524086405238b9683a69771c1b9d5 Gerrit-Change-Number: 35388 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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