coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

1 participants
1442 discussions

Change in ...coreboot[master]: mb/packardbell/ms2290: Use common SB code to set up GPIO's
by Arthur Heymans (Code Review) 15 Sep '19

15 Sep '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33809 Change subject: mb/packardbell/ms2290: Use common SB code to set up GPIO's ...................................................................... mb/packardbell/ms2290: Use common SB code to set up GPIO's Change-Id: I6658c53213127db5a46f2ea330d85a3a537c3276 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/packardbell/ms2290/Makefile.inc A src/mainboard/packardbell/ms2290/gpio.c M src/mainboard/packardbell/ms2290/romstage.c 3 files changed, 130 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/33809/1 diff --git a/src/mainboard/packardbell/ms2290/Makefile.inc b/src/mainboard/packardbell/ms2290/Makefile.inc index da1f50d..b8841cc 100644 --- a/src/mainboard/packardbell/ms2290/Makefile.inc +++ b/src/mainboard/packardbell/ms2290/Makefile.inc @@ -13,6 +13,8 @@ ## GNU General Public License for more details. ## +romstage-y += gpio.c + smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/packardbell/ms2290/gpio.c b/src/mainboard/packardbell/ms2290/gpio.c new file mode 100644 index 0000000..3aed746 --- /dev/null +++ b/src/mainboard/packardbell/ms2290/gpio.c @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_OUTPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio12 = GPIO_LEVEL_LOW, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio7 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_LOW, + .gpio35 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, +}; diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 0ab5544..d36f587e 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -31,6 +31,7 @@ #include <timestamp.h> #include <arch/acpi.h> +#include <southbridge/intel/common/gpio.h> #include <southbridge/intel/ibexpeak/pch.h> #include <northbridge/intel/nehalem/nehalem.h> @@ -181,15 +182,8 @@ /* Enable GPIOs */ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); - outl (0x796bd9c3, DEFAULT_GPIOBASE); - outl (0x86fec7c2, DEFAULT_GPIOBASE + 4); - outl (0xe4e8d7fe, DEFAULT_GPIOBASE + 0xc); - outl (0, DEFAULT_GPIOBASE + 0x18); - outl (0x00004182, DEFAULT_GPIOBASE + 0x2c); - outl (0x123360f8, DEFAULT_GPIOBASE + 0x30); - outl (0x1f47bfa8, DEFAULT_GPIOBASE + 0x34); - outl (0xfffe7fb6, DEFAULT_GPIOBASE + 0x38); + setup_pch_gpios(&mainboard_gpio_map); /* This should probably go away. Until now it is required * and mainboard specific -- To view, visit https://review.coreboot.org/c/coreboot/+/33809 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6658c53213127db5a46f2ea330d85a3a537c3276 Gerrit-Change-Number: 33809 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: soc/intel/skylake: add FSP params for SATA SpinUp, HotPlug and TestMode
by Michael Niewöhner (Code Review) 15 Sep '19

15 Sep '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35186 ) Change subject: soc/intel/skylake: add FSP params for SATA SpinUp, HotPlug and TestMode ...................................................................... soc/intel/skylake: add FSP params for SATA SpinUp, HotPlug and TestMode Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: I7ba67879b78c2cb0fd0b0ce832140b213edd5884 --- M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/35186/1 diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 1313dc1..fee14d8 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -200,6 +200,8 @@ u8 SataSalpSupport; u8 SataPortsEnable[8]; u8 SataPortsDevSlp[8]; + u8 SataPortsSpinUp[8]; + u8 SataPortsHotPlug[8]; u8 SataSpeedLimit; /* Audio related */ @@ -587,6 +589,9 @@ /* Enable/Disable Sata power optimization */ u8 SataPwrOptEnable; + + /* Enable/Disable Sata test mode */ + u8 SataTestMode; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 064f71e..820b9d3 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -283,6 +283,10 @@ sizeof(params->SataPortsEnable)); memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp, sizeof(params->SataPortsDevSlp)); + memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug, + sizeof(params->SataPortsHotPlug)); + memcpy(params->SataPortsSpinUp, config->SataPortsSpinUp, + sizeof(params->SataPortsSpinUp)); memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, sizeof(params->PcieRpClkReqSupport)); memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber, @@ -372,6 +376,7 @@ tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; tconfig->PowerLimit4 = config->PowerLimit4; + tconfig->SataTestMode = config->SataTestMode; /* * To disable HECI, the Psf needs to be left unlocked * by FSP till end of post sequence. Based on the devicetree -- To view, visit https://review.coreboot.org/c/coreboot/+/35186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ba67879b78c2cb0fd0b0ce832140b213edd5884 Gerrit-Change-Number: 35186 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: mb/*/{x201,ms2290}/mainboard.c: Remove superfluous ramstage code
by Arthur Heymans (Code Review) 15 Sep '19

15 Sep '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33141 Change subject: mb/*/{x201,ms2290}/mainboard.c: Remove superfluous ramstage code ...................................................................... mb/*/{x201,ms2290}/mainboard.c: Remove superfluous ramstage code Change-Id: I0270c50dea2a2ce6c8e6114ed708f06be9d33c0e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/packardbell/ms2290/mainboard.c 2 files changed, 0 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/33141/1 diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 54acca3..ad878db 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -70,19 +70,6 @@ dev->ops->init = mainboard_init; dev->ops->acpi_fill_ssdt_generator = fill_ssdt; - pmbase = pci_read_config32(pcidev_on_root(0x1f, 0), - PMBASE) & 0xff80; - - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); - - outl(0, pmbase + SMI_EN); - - enable_lapic(); - pci_write_config32(pcidev_on_root(0x1f, 0), GPIO_BASE, - DEFAULT_GPIOBASE | 1); - pci_write_config8(pcidev_on_root(0x1f, 0), GPIO_CNTL, - 0x10); - /* If we're resuming from suspend, blink suspend LED */ if (acpi_is_wakeup_s3()) ec_write(0x0c, 0xc7); diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 28d3bb0..d532a48 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -83,19 +83,6 @@ for (i = 0; i < 256; i++) ec_write (i, dmp[i]); - pmbase = pci_read_config32(pcidev_on_root(0x1f, 0), - PMBASE) & 0xff80; - - printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); - - outl(0, pmbase + SMI_EN); - - enable_lapic(); - pci_write_config32(pcidev_on_root(0x1f, 0), GPIO_BASE, - DEFAULT_GPIOBASE | 1); - pci_write_config8(pcidev_on_root(0x1f, 0), GPIO_CNTL, - 0x10); - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2); /* This sneaked in here, because EasyNote has no SuperIO chip. -- To view, visit https://review.coreboot.org/c/coreboot/+/33141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0270c50dea2a2ce6c8e6114ed708f06be9d33c0e Gerrit-Change-Number: 33141 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: cpu/intel/microcode: Make microcode lib available in bootblock
by Rizwan Qureshi (Code Review) 15 Sep '19

15 Sep '19

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35278 ) Change subject: cpu/intel/microcode: Make microcode lib available in bootblock ...................................................................... cpu/intel/microcode: Make microcode lib available in bootblock Make microcode lib available in bootblock. Change-Id: I419da6af70222902e3ca39fc2133d5dc8558e053 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/cpu/intel/microcode/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/35278/1 diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index 2df1d5e..b13172e 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -1,5 +1,6 @@ bootblock-$(CONFIG_MICROCODE_UPDATE_PRE_RAM) += microcode_asm.S romstage-$(CONFIG_MICROCODE_UPDATE_PRE_RAM) += microcode_asm.S +bootblock-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c romstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c -- To view, visit https://review.coreboot.org/c/coreboot/+/35278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I419da6af70222902e3ca39fc2133d5dc8558e053 Gerrit-Change-Number: 35278 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: payloads/LinuxBoot: move kernel make flags into own variable
by Alexander Couzens (Code Review) 15 Sep '19

15 Sep '19

Alexander Couzens has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35392 ) Change subject: payloads/LinuxBoot: move kernel make flags into own variable ...................................................................... payloads/LinuxBoot: move kernel make flags into own variable Change-Id: I9240043d2c15b68aabe154b289a961d8d48d3e5f --- M payloads/external/LinuxBoot/targets/linux.mk 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/35392/1 diff --git a/payloads/external/LinuxBoot/targets/linux.mk b/payloads/external/LinuxBoot/targets/linux.mk index b7b3a0d..8be0926 100644 --- a/payloads/external/LinuxBoot/targets/linux.mk +++ b/payloads/external/LinuxBoot/targets/linux.mk @@ -29,6 +29,8 @@ decompress_flag=.done OBJCOPY:=$(LINUXBOOT_CROSS_COMPILE)objcopy +KERNEL_MAKE_FLAGS = \ + ARCH=$(ARCH-y) ifeq ($(CONFIG_LINUXBOOT_KERNEL_CUSTOM),y) kernel_version:=$(CONFIG_LINUXBOOT_KERNEL_CUSTOM_VERSION) @@ -90,15 +92,15 @@ else cp $(ARCH-y)/defconfig $(kernel_dir)/.config endif - $(MAKE) -C $(kernel_dir) olddefconfig ARCH=$(ARCH-y) + $(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) olddefconfig build: $(kernel_dir)/.config @echo " MAKE Linux $(kernel_version)" ifeq ($(CONFIG_LINUXBOOT_KERNEL_BZIMAGE),y) - $(MAKE) -C $(kernel_dir) CROSS_COMPILE=$(LINUXBOOT_CROSS_COMPILE) ARCH=$(ARCH-y) bzImage + $(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) CROSS_COMPILE=$(LINUXBOOT_CROSS_COMPILE) bzImage else ifeq ($(CONFIG_LINUXBOOT_KERNEL_UIMAGE),y) - $(MAKE) -C $(kernel_dir) CROSS_COMPILE=$(LINUXBOOT_CROSS_COMPILE) ARCH=$(ARCH-y) vmlinux + $(MAKE) -C $(kernel_dir) $(KERNEL_MAKE_FLAGS) CROSS_COMPILE=$(LINUXBOOT_CROSS_COMPILE) vmlinux endif endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9240043d2c15b68aabe154b289a961d8d48d3e5f Gerrit-Change-Number: 35392 Gerrit-PatchSet: 1 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: {i945,i82801gx}: Remove unneeded include <cpu/x86/cache.h>
by HAOUAS Elyes (Code Review) 15 Sep '19

15 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34934 ) Change subject: {i945,i82801gx}: Remove unneeded include <cpu/x86/cache.h> ...................................................................... {i945,i82801gx}: Remove unneeded include <cpu/x86/cache.h> Change-Id: I4f38be28d81c0c01c0389210552232e63ea55545 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c M src/southbridge/intel/i82801gx/smihandler.c 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/34934/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index dd98433..7096774 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -15,7 +15,6 @@ */ #include <console/console.h> -#include <cpu/x86/cache.h> #include <delay.h> #include <device/pci_def.h> #include <device/pci_ops.h> diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 31306fb..16ceb13 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -16,7 +16,6 @@ #include <types.h> #include <console/console.h> -#include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> #include <pc80/mc146818rtc.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/34934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f38be28d81c0c01c0389210552232e63ea55545 Gerrit-Change-Number: 34934 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: src/security: Remove not used #include <fmap.h>
by HAOUAS Elyes (Code Review) 15 Sep '19

15 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33734 Change subject: src/security: Remove not used #include <fmap.h> ...................................................................... src/security: Remove not used #include <fmap.h> Change-Id: I9db59d5db2ed3e792251a94b67fb277d9160e4e8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/security/tpm/tspi/log.c M src/security/vboot/vboot_handoff.c 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/33734/1 diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 6ab9067..a33116a 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -16,7 +16,6 @@ #include <console/console.h> #include <security/tpm/tspi.h> #include <arch/early_variables.h> -#include <fmap.h> #include <region_file.h> #include <string.h> #include <security/vboot/symbols.h> diff --git a/src/security/vboot/vboot_handoff.c b/src/security/vboot/vboot_handoff.c index 19773c54..d8af702 100644 --- a/src/security/vboot/vboot_handoff.c +++ b/src/security/vboot/vboot_handoff.c @@ -26,7 +26,6 @@ #include <cbmem.h> #include <console/console.h> #include <console/vtxprintf.h> -#include <fmap.h> #include <stdlib.h> #include <vboot_struct.h> #include <security/vboot/vbnv.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9db59d5db2ed3e792251a94b67fb277d9160e4e8 Gerrit-Change-Number: 33734 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 6

Change in ...coreboot[master]: southbridge: Remove unused include <device/pci_ops.h>
by HAOUAS Elyes (Code Review) 15 Sep '19

15 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33531 Change subject: southbridge: Remove unused include <device/pci_ops.h> ...................................................................... southbridge: Remove unused include <device/pci_ops.h> Change-Id: I8578cf365addc47550e27c9ebed08de340d70ede Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/agesa/hudson/hda.c M src/southbridge/amd/agesa/hudson/ide.c M src/southbridge/amd/agesa/hudson/pci.c M src/southbridge/amd/agesa/hudson/pcie.c M src/southbridge/amd/agesa/hudson/reset.c M src/southbridge/amd/agesa/hudson/sm.c M src/southbridge/amd/agesa/hudson/usb.c M src/southbridge/amd/amd8111/ac97.c M src/southbridge/amd/amd8111/usb2.c M src/southbridge/amd/pi/hudson/hda.c M src/southbridge/amd/pi/hudson/ide.c M src/southbridge/amd/pi/hudson/pci.c M src/southbridge/amd/pi/hudson/pcie.c M src/southbridge/amd/pi/hudson/reset.c M src/southbridge/amd/pi/hudson/sm.c M src/southbridge/amd/pi/hudson/usb.c M src/southbridge/broadcom/bcm5785/ide.c M src/southbridge/broadcom/bcm5785/sb_pci_main.c M src/southbridge/intel/fsp_rangeley/smbus.c M src/southbridge/intel/i82801gx/smbus.c M src/southbridge/intel/ibexpeak/thermal.c M src/southbridge/nvidia/ck804/ac97.c M src/southbridge/nvidia/ck804/smbus.c M src/southbridge/nvidia/mcp55/ht.c M src/southbridge/nvidia/mcp55/smbus.c M src/southbridge/nvidia/mcp55/usb.c M src/southbridge/ti/pcixx12/pcixx12.c 27 files changed, 0 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/33531/1 diff --git a/src/southbridge/amd/agesa/hudson/hda.c b/src/southbridge/amd/agesa/hudson/hda.c index 2368bb2..725bb0b 100644 --- a/src/southbridge/amd/agesa/hudson/hda.c +++ b/src/southbridge/amd/agesa/hudson/hda.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include "hudson.h" diff --git a/src/southbridge/amd/agesa/hudson/ide.c b/src/southbridge/amd/agesa/hudson/ide.c index 66bb89b..aa2b66f 100644 --- a/src/southbridge/amd/agesa/hudson/ide.c +++ b/src/southbridge/amd/agesa/hudson/ide.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include "hudson.h" static void ide_init(struct device *dev) diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c index 31371ce..5564533 100644 --- a/src/southbridge/amd/agesa/hudson/pci.c +++ b/src/southbridge/amd/agesa/hudson/pci.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include "hudson.h" #include <southbridge/amd/common/amd_pci_util.h> #include <bootstate.h> diff --git a/src/southbridge/amd/agesa/hudson/pcie.c b/src/southbridge/amd/agesa/hudson/pcie.c index c765fb6..9f7e84b 100644 --- a/src/southbridge/amd/agesa/hudson/pcie.c +++ b/src/southbridge/amd/agesa/hudson/pcie.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include "hudson.h" static void pcie_init(struct device *dev) diff --git a/src/southbridge/amd/agesa/hudson/reset.c b/src/southbridge/amd/agesa/hudson/reset.c index e329038..b7a2287 100644 --- a/src/southbridge/amd/agesa/hudson/reset.c +++ b/src/southbridge/amd/agesa/hudson/reset.c @@ -16,7 +16,6 @@ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ -#include <device/pci_ops.h> #include <cf9_reset.h> #include <reset.h> diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index 46eca33..b5739f9 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include <device/smbus.h> #include <cpu/x86/lapic.h> #include <arch/ioapic.h> diff --git a/src/southbridge/amd/agesa/hudson/usb.c b/src/southbridge/amd/agesa/hudson/usb.c index ec305af..d6f3879 100644 --- a/src/southbridge/amd/agesa/hudson/usb.c +++ b/src/southbridge/amd/agesa/hudson/usb.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include <device/pci_ehci.h> #include "hudson.h" diff --git a/src/southbridge/amd/amd8111/ac97.c b/src/southbridge/amd/amd8111/ac97.c index 267c436..d05f0be 100644 --- a/src/southbridge/amd/amd8111/ac97.c +++ b/src/southbridge/amd/amd8111/ac97.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include "amd8111.h" static struct pci_operations lops_pci = { diff --git a/src/southbridge/amd/amd8111/usb2.c b/src/southbridge/amd/amd8111/usb2.c index adb7db1..b41c0be 100644 --- a/src/southbridge/amd/amd8111/usb2.c +++ b/src/southbridge/amd/amd8111/usb2.c @@ -18,7 +18,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include "amd8111.h" static void amd8111_usb2_enable(struct device *dev) diff --git a/src/southbridge/amd/pi/hudson/hda.c b/src/southbridge/amd/pi/hudson/hda.c index 9cdc1b4..8bd54a8 100644 --- a/src/southbridge/amd/pi/hudson/hda.c +++ b/src/southbridge/amd/pi/hudson/hda.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include "hudson.h" diff --git a/src/southbridge/amd/pi/hudson/ide.c b/src/southbridge/amd/pi/hudson/ide.c index 66bb89b..aa2b66f 100644 --- a/src/southbridge/amd/pi/hudson/ide.c +++ b/src/southbridge/amd/pi/hudson/ide.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include "hudson.h" static void ide_init(struct device *dev) diff --git a/src/southbridge/amd/pi/hudson/pci.c b/src/southbridge/amd/pi/hudson/pci.c index 35cd2a9..c8e51b1 100644 --- a/src/southbridge/amd/pi/hudson/pci.c +++ b/src/southbridge/amd/pi/hudson/pci.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include "hudson.h" #include <southbridge/amd/common/amd_pci_util.h> #include <bootstate.h> diff --git a/src/southbridge/amd/pi/hudson/pcie.c b/src/southbridge/amd/pi/hudson/pcie.c index c765fb6..9f7e84b 100644 --- a/src/southbridge/amd/pi/hudson/pcie.c +++ b/src/southbridge/amd/pi/hudson/pcie.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include "hudson.h" static void pcie_init(struct device *dev) diff --git a/src/southbridge/amd/pi/hudson/reset.c b/src/southbridge/amd/pi/hudson/reset.c index e329038..b7a2287 100644 --- a/src/southbridge/amd/pi/hudson/reset.c +++ b/src/southbridge/amd/pi/hudson/reset.c @@ -16,7 +16,6 @@ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ -#include <device/pci_ops.h> #include <cf9_reset.h> #include <reset.h> diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index 0387567..58f5113 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include <device/smbus.h> #include <cpu/x86/lapic.h> #include <arch/ioapic.h> diff --git a/src/southbridge/amd/pi/hudson/usb.c b/src/southbridge/amd/pi/hudson/usb.c index f6d0106..2f50c3f 100644 --- a/src/southbridge/amd/pi/hudson/usb.c +++ b/src/southbridge/amd/pi/hudson/usb.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include <device/pci_ehci.h> #include "hudson.h" diff --git a/src/southbridge/broadcom/bcm5785/ide.c b/src/southbridge/broadcom/bcm5785/ide.c index 2932a23..c143c22 100644 --- a/src/southbridge/broadcom/bcm5785/ide.c +++ b/src/southbridge/broadcom/bcm5785/ide.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include "bcm5785.h" static void bcm5785_ide_read_resources(struct device *dev) diff --git a/src/southbridge/broadcom/bcm5785/sb_pci_main.c b/src/southbridge/broadcom/bcm5785/sb_pci_main.c index 759cb5d..318086e 100644 --- a/src/southbridge/broadcom/bcm5785/sb_pci_main.c +++ b/src/southbridge/broadcom/bcm5785/sb_pci_main.c @@ -18,7 +18,6 @@ #include <device/pci.h> #include <device/pnp.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> diff --git a/src/southbridge/intel/fsp_rangeley/smbus.c b/src/southbridge/intel/fsp_rangeley/smbus.c index 83533f1..610ce0c 100644 --- a/src/southbridge/intel/fsp_rangeley/smbus.c +++ b/src/southbridge/intel/fsp_rangeley/smbus.c @@ -19,7 +19,6 @@ #include <device/smbus.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include <southbridge/intel/common/smbus.h> #include "soc.h" diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index 693c2dc..b2341a1 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -19,7 +19,6 @@ #include <device/smbus.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include <southbridge/intel/common/smbus.h> #include "i82801gx.h" diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index 31b2cb6..597d388 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -20,7 +20,6 @@ #include <device/pci_ids.h> #include "pch.h" #include <device/mmio.h> -#include <device/pci_ops.h> static void thermal_init(struct device *dev) { diff --git a/src/southbridge/nvidia/ck804/ac97.c b/src/southbridge/nvidia/ck804/ac97.c index f7c6f42..28c5e74 100644 --- a/src/southbridge/nvidia/ck804/ac97.c +++ b/src/southbridge/nvidia/ck804/ac97.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include "chip.h" static struct device_operations ac97audio_ops = { diff --git a/src/southbridge/nvidia/ck804/smbus.c b/src/southbridge/nvidia/ck804/smbus.c index 2d223fd..b96dc6e 100644 --- a/src/southbridge/nvidia/ck804/smbus.c +++ b/src/southbridge/nvidia/ck804/smbus.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include <device/smbus.h> #include "chip.h" #include "smbus.h" diff --git a/src/southbridge/nvidia/mcp55/ht.c b/src/southbridge/nvidia/mcp55/ht.c index 4c831ad..070f8b7 100644 --- a/src/southbridge/nvidia/mcp55/ht.c +++ b/src/southbridge/nvidia/mcp55/ht.c @@ -20,7 +20,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include <arch/acpi.h> #include "mcp55.h" diff --git a/src/southbridge/nvidia/mcp55/smbus.c b/src/southbridge/nvidia/mcp55/smbus.c index 1228d57..37f4a1e 100644 --- a/src/southbridge/nvidia/mcp55/smbus.c +++ b/src/southbridge/nvidia/mcp55/smbus.c @@ -20,7 +20,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include <device/smbus.h> #include "mcp55.h" #include "smbus.h" diff --git a/src/southbridge/nvidia/mcp55/usb.c b/src/southbridge/nvidia/mcp55/usb.c index 18e6a65..46e2775 100644 --- a/src/southbridge/nvidia/mcp55/usb.c +++ b/src/southbridge/nvidia/mcp55/usb.c @@ -20,7 +20,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include "mcp55.h" static struct device_operations usb_ops = { diff --git a/src/southbridge/ti/pcixx12/pcixx12.c b/src/southbridge/ti/pcixx12/pcixx12.c index fa1c67d..984b60f 100644 --- a/src/southbridge/ti/pcixx12/pcixx12.c +++ b/src/southbridge/ti/pcixx12/pcixx12.c @@ -15,7 +15,6 @@ #include <device/device.h> #include <device/pci.h> -#include <device/pci_ops.h> #include <console/console.h> #include <device/cardbus.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33531 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8578cf365addc47550e27c9ebed08de340d70ede Gerrit-Change-Number: 33531 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: src/soc: Remove unused include <device/pci_ops.h>
by HAOUAS Elyes (Code Review) 15 Sep '19

15 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33530 Change subject: src/soc: Remove unused include <device/pci_ops.h> ...................................................................... src/soc: Remove unused include <device/pci_ops.h> Change-Id: I80c92f744fb9a6c3788b8b9ba779deef76e58943 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/common/block/hda/hda.c M src/soc/amd/common/block/iommu/iommu.c M src/soc/amd/common/block/pi/amd_late_init.c M src/soc/amd/common/block/sata/sata.c M src/soc/amd/stoneyridge/sm.c M src/soc/amd/stoneyridge/spi.c M src/soc/intel/baytrail/bootblock/bootblock.c M src/soc/intel/baytrail/chip.c M src/soc/intel/baytrail/elog.c M src/soc/intel/baytrail/iosf.c M src/soc/intel/braswell/elog.c M src/soc/intel/braswell/iosf.c M src/soc/intel/broadwell/bootblock/systemagent.c M src/soc/intel/broadwell/chip.c M src/soc/intel/cannonlake/pmc.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/denverton_ns/chip.c M src/soc/intel/denverton_ns/uart_debug.c M src/soc/intel/fsp_baytrail/chip.c M src/soc/intel/fsp_baytrail/iosf.c M src/soc/intel/fsp_broadwell_de/chip.c M src/soc/intel/icelake/pmc.c M src/soc/intel/quark/include/soc/ramstage.h 24 files changed, 0 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/33530/1 diff --git a/src/soc/amd/common/block/hda/hda.c b/src/soc/amd/common/block/hda/hda.c index f4ea732..2f81780 100644 --- a/src/soc/amd/common/block/hda/hda.c +++ b/src/soc/amd/common/block/hda/hda.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_AMD_SB900_HDA, diff --git a/src/soc/amd/common/block/iommu/iommu.c b/src/soc/amd/common/block/iommu/iommu.c index 1c982ca..ac7beed 100644 --- a/src/soc/amd/common/block/iommu/iommu.c +++ b/src/soc/amd/common/block/iommu/iommu.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include <lib.h> static void iommu_read_resources(struct device *dev) diff --git a/src/soc/amd/common/block/pi/amd_late_init.c b/src/soc/amd/common/block/pi/amd_late_init.c index 80c7add..f2b4ed1 100644 --- a/src/soc/amd/common/block/pi/amd_late_init.c +++ b/src/soc/amd/common/block/pi/amd_late_init.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <dimm_info_util.h> #include <memory_info.h> #include <lib.h> diff --git a/src/soc/amd/common/block/sata/sata.c b/src/soc/amd/common/block/sata/sata.c index cbbc7cf..5aa2088 100644 --- a/src/soc/amd/common/block/sata/sata.c +++ b/src/soc/amd/common/block/sata/sata.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include <amdblocks/sata.h> void __weak soc_enable_sata_features(struct device *dev) { } diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c index 803e628..fbcddfa 100644 --- a/src/soc/amd/stoneyridge/sm.c +++ b/src/soc/amd/stoneyridge/sm.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include <device/smbus.h> #include <cpu/x86/lapic.h> #include <arch/ioapic.h> diff --git a/src/soc/amd/stoneyridge/spi.c b/src/soc/amd/stoneyridge/spi.c index 8abfa16..60b6a20 100644 --- a/src/soc/amd/stoneyridge/spi.c +++ b/src/soc/amd/stoneyridge/spi.c @@ -24,7 +24,6 @@ #include <spi-generic.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ops.h> #include <soc/southbridge.h> #include <amdblocks/lpc.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index b2cdf9d..9a189e3 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <device/pci_ops.h> #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> diff --git a/src/soc/intel/baytrail/chip.c b/src/soc/intel/baytrail/chip.c index acac679..6f0d98a 100644 --- a/src/soc/intel/baytrail/chip.c +++ b/src/soc/intel/baytrail/chip.c @@ -15,7 +15,6 @@ #include <device/device.h> #include <device/pci.h> -#include <device/pci_ops.h> #include <arch/pci_ops.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c index 45dcec8..d7a0460 100644 --- a/src/soc/intel/baytrail/elog.c +++ b/src/soc/intel/baytrail/elog.c @@ -20,7 +20,6 @@ #include <cbmem.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ops.h> #include <elog.h> #include <soc/iomap.h> #include <soc/pmc.h> diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index bb5e80c..9974a22 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -14,7 +14,6 @@ */ #include <stdint.h> -#include <device/pci_ops.h> #include <soc/iosf.h> static inline void write_iosf_reg(int reg, uint32_t value) diff --git a/src/soc/intel/braswell/elog.c b/src/soc/intel/braswell/elog.c index f1fc7d4..6efcef1 100644 --- a/src/soc/intel/braswell/elog.c +++ b/src/soc/intel/braswell/elog.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ops.h> #include <elog.h> #include <soc/iomap.h> #include <soc/pm.h> diff --git a/src/soc/intel/braswell/iosf.c b/src/soc/intel/braswell/iosf.c index 5aa6181..71bf3a6 100644 --- a/src/soc/intel/braswell/iosf.c +++ b/src/soc/intel/braswell/iosf.c @@ -15,7 +15,6 @@ */ #include <stdint.h> -#include <device/pci_ops.h> #include <console/console.h> #include <soc/iosf.h> diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c index 7aaed78..62a5330 100644 --- a/src/soc/intel/broadwell/bootblock/systemagent.c +++ b/src/soc/intel/broadwell/bootblock/systemagent.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> #include <cpu/intel/car/bootblock.h> diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c index caff026..2b9f6a1 100644 --- a/src/soc/intel/broadwell/chip.c +++ b/src/soc/intel/broadwell/chip.c @@ -15,7 +15,6 @@ #include <device/device.h> #include <device/pci.h> -#include <device/pci_ops.h> #include <soc/acpi.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index 6834aa2..19478c2 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <device/mmio.h> #include <device/device.h> -#include <device/pci_ops.h> #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 8ab835e..f4b8789 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -19,7 +19,6 @@ #include <device/azalia_device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include <soc/intel/common/hda_verb.h> #include <soc/ramstage.h> diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index fc22577..2a0ab4b 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -19,7 +19,6 @@ #include <device/smbus.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include <soc/smbus.h> #include "smbuslib.h" diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index b72bf28..c21a2a7 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -21,7 +21,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ops.h> #include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/fast_spi.h> diff --git a/src/soc/intel/denverton_ns/uart_debug.c b/src/soc/intel/denverton_ns/uart_debug.c index f7d523e..8fb1fab 100644 --- a/src/soc/intel/denverton_ns/uart_debug.c +++ b/src/soc/intel/denverton_ns/uart_debug.c @@ -16,7 +16,6 @@ #include <stdint.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <soc/uart.h> #define MY_PCI_DEV(SEGBUS, DEV, FN) \ diff --git a/src/soc/intel/fsp_baytrail/chip.c b/src/soc/intel/fsp_baytrail/chip.c index 9e86279..3ca26ad 100644 --- a/src/soc/intel/fsp_baytrail/chip.c +++ b/src/soc/intel/fsp_baytrail/chip.c @@ -16,7 +16,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <drivers/intel/fsp1_0/fsp_util.h> diff --git a/src/soc/intel/fsp_baytrail/iosf.c b/src/soc/intel/fsp_baytrail/iosf.c index 25f82ab..ea5d9d5 100644 --- a/src/soc/intel/fsp_baytrail/iosf.c +++ b/src/soc/intel/fsp_baytrail/iosf.c @@ -16,7 +16,6 @@ */ #include <stdint.h> -#include <device/pci_ops.h> #include <soc/iosf.h> static inline void write_iosf_reg(int reg, uint32_t value) diff --git a/src/soc/intel/fsp_broadwell_de/chip.c b/src/soc/intel/fsp_broadwell_de/chip.c index a0b3f7c..a1978fa4 100644 --- a/src/soc/intel/fsp_broadwell_de/chip.c +++ b/src/soc/intel/fsp_broadwell_de/chip.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ops.h> #include <drivers/intel/fsp1_0/fsp_util.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> diff --git a/src/soc/intel/icelake/pmc.c b/src/soc/intel/icelake/pmc.c index 8f61d70..ad71359 100644 --- a/src/soc/intel/icelake/pmc.c +++ b/src/soc/intel/icelake/pmc.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <device/mmio.h> #include <device/device.h> -#include <device/pci_ops.h> #include <intelblocks/pmc.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h index 56be795..ada8899 100644 --- a/src/soc/intel/quark/include/soc/ramstage.h +++ b/src/soc/intel/quark/include/soc/ramstage.h @@ -19,7 +19,6 @@ #include <arch/cpu.h> #include <device/device.h> -#include <device/pci_ops.h> #include <soc/QuarkNcSocId.h> #include "../../chip.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/33530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80c92f744fb9a6c3788b8b9ba779deef76e58943 Gerrit-Change-Number: 33530 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 4

Change in ...coreboot[master]: northbridge: Remove unused include <device/pci_ops.h>
by HAOUAS Elyes (Code Review) 15 Sep '19

15 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33529 Change subject: northbridge: Remove unused include <device/pci_ops.h> ...................................................................... northbridge: Remove unused include <device/pci_ops.h> Change-Id: Ib60305948ac1d3464586fe69501bd28eecb761ee Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/pi/00730F01/iommu.c M src/northbridge/intel/gm45/bootblock.c M src/northbridge/intel/haswell/bootblock.c M src/northbridge/intel/i945/bootblock.c M src/northbridge/intel/nehalem/bootblock.c M src/northbridge/intel/nehalem/finalize.c M src/northbridge/intel/pineview/bootblock.c M src/northbridge/intel/sandybridge/bootblock.c M src/northbridge/intel/sandybridge/pcie.c M src/northbridge/intel/x4x/bootblock.c M src/northbridge/via/vx900/bootblock.c 11 files changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/33529/1 diff --git a/src/northbridge/amd/pi/00730F01/iommu.c b/src/northbridge/amd/pi/00730F01/iommu.c index 1ff4cfb..5ff631c 100644 --- a/src/northbridge/amd/pi/00730F01/iommu.c +++ b/src/northbridge/amd/pi/00730F01/iommu.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_ops.h> #include <lib.h> static void iommu_read_resources(struct device *dev) diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c index c076c55..0040d8f 100644 --- a/src/northbridge/intel/gm45/bootblock.c +++ b/src/northbridge/intel/gm45/bootblock.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <device/pci_ops.h> /* Just re-define these instead of including gm45.h. It blows up romcc. */ #define D0F0_PCIEXBAR_LO 0x60 diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index 2c1bd58..7cd0eb4 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <device/pci_ops.h> #include <cpu/intel/car/bootblock.h> #include "haswell.h" diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index 604088b..8e74d80 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <device/pci_ops.h> /* Just re-define this instead of including i945.h. It blows up romcc. */ #define PCIEXBAR 0x48 diff --git a/src/northbridge/intel/nehalem/bootblock.c b/src/northbridge/intel/nehalem/bootblock.c index f96ff56..fa3f15b 100644 --- a/src/northbridge/intel/nehalem/bootblock.c +++ b/src/northbridge/intel/nehalem/bootblock.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <device/pci_ops.h> static void bootblock_northbridge_init(void) { diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c index 97f6011..3389249 100644 --- a/src/northbridge/intel/nehalem/finalize.c +++ b/src/northbridge/intel/nehalem/finalize.c @@ -15,7 +15,6 @@ */ #include <stdlib.h> -#include <device/pci_ops.h> #include "nehalem.h" #define PCI_DEV_SNB PCI_DEV(0, 0, 0) diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c index bd510b0..66fe40e 100644 --- a/src/northbridge/intel/pineview/bootblock.c +++ b/src/northbridge/intel/pineview/bootblock.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <device/pci_ops.h> #include <cpu/intel/car/bootblock.h> #include "pineview.h" diff --git a/src/northbridge/intel/sandybridge/bootblock.c b/src/northbridge/intel/sandybridge/bootblock.c index 15e2de1..cdbe007 100644 --- a/src/northbridge/intel/sandybridge/bootblock.c +++ b/src/northbridge/intel/sandybridge/bootblock.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <device/pci_ops.h> /* Just re-define this instead of including sandybridge.h. It blows up romcc. */ #define PCIEXBAR 0x60 diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c index 344cd80..618ee52 100644 --- a/src/northbridge/intel/sandybridge/pcie.c +++ b/src/northbridge/intel/sandybridge/pcie.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ops.h> #include <device/pciexp.h> #include <device/pci_ids.h> #include <assert.h> diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index 1dfdf19..b1e384b 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <device/pci_ops.h> #include "iomap.h" #include "x4x.h" diff --git a/src/northbridge/via/vx900/bootblock.c b/src/northbridge/via/vx900/bootblock.c index 6679cdb..478893b 100644 --- a/src/northbridge/via/vx900/bootblock.c +++ b/src/northbridge/via/vx900/bootblock.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <device/pci_ops.h> #if CONFIG_ROM_SIZE == 0x80000 # define ROM_DECODE_MAP 0x00 -- To view, visit https://review.coreboot.org/c/coreboot/+/33529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib60305948ac1d3464586fe69501bd28eecb761ee Gerrit-Change-Number: 33529 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2019