coreboot-gerrit September 2019

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Change in coreboot[master]: mainboard/lenovo/t410: Add new port
by Patrick Rudolph (Code Review) 16 Sep '19

16 Sep '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: mainboard/lenovo/t410: Add new port ...................................................................... Patch Set 16: (2 comments) Remove some unused code. Added documentation. https://review.coreboot.org/c/coreboot/+/11791/15/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/mainboard.c: https://review.coreboot.org/c/coreboot/+/11791/15/src/mainboard/lenovo/t410… PS15, Line 33: static void mainboard_init(struct device *dev) > I think this RCBA configuration may be removed. See commit b236cba61558649791224cf35357568bfe3b30db. Done https://review.coreboot.org/c/coreboot/+/11791/15/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/smihandler.c: https://review.coreboot.org/c/coreboot/+/11791/15/src/mainboard/lenovo/t410… PS15, Line 21: #include <southbridge/intel/ibexpeak/pch.h> > I believe this include is no longer necessary since commit 548f33a9f4a7675c42822516c285bdf2c8bb64de Done -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 16 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Degen Gerrit-CC: Matt Parnell <mparnell(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Mon, 16 Sep 2019 07:56:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/lenovo/t410: Add new port
by build bot (Jenkins) (Code Review) 16 Sep '19

16 Sep '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: mainboard/lenovo/t410: Add new port ...................................................................... Patch Set 16: (5 comments) https://review.coreboot.org/c/coreboot/+/11791/16/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/romstage.c: https://review.coreboot.org/c/coreboot/+/11791/16/src/mainboard/lenovo/t410… PS16, Line 140: unsigned i; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/c/coreboot/+/11791/16/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/smihandler.c: https://review.coreboot.org/c/coreboot/+/11791/16/src/mainboard/lenovo/t410… PS16, Line 34: switch (smif) { switch and case should be at the same indent https://review.coreboot.org/c/coreboot/+/11791/16/src/mainboard/lenovo/t410… PS16, Line 37: udelay(250000); long udelay - prefer mdelay; see arch/arm/include/asm/delay.h https://review.coreboot.org/c/coreboot/+/11791/16/src/mainboard/lenovo/t410… PS16, Line 70: switch (event) { switch and case should be at the same indent https://review.coreboot.org/c/coreboot/+/11791/16/src/mainboard/lenovo/t410… PS16, Line 97: switch (data) { switch and case should be at the same indent -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 16 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Degen Gerrit-CC: Matt Parnell <mparnell(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Mon, 16 Sep 2019 07:56:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/lenovo/t410: Add new port
by Patrick Rudolph (Code Review) 16 Sep '19

16 Sep '19

Patrick Rudolph has uploaded a new patch set (#16) to the change originally created by Nicolas Reinecke. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: mainboard/lenovo/t410: Add new port ...................................................................... mainboard/lenovo/t410: Add new port The port is based on the x201 / t410s. 2537-vg5 / i5, no discrete gpu Tested and working: * Native raminit * Native gfxinit * Booting Seabios 1.12.1 * Booting from EHCI * Running GNU/Linux 5.0.0 * No errors in dmesg * EHCI debug on the devices left side, bottom-right * Keyboard * Fn keys (Mute, Volume, Mic) * Touchpad * TPM * Wifi * Sound * USB * Ethernet Testing in progress. Untested: * VGA * Displayport Bugs: * S3 resume is broken. * AC adapter can't be read from ACPI TODOs: * Hide internal PCI devices Details for flashing externally: 1. Disconnect all power 2. Connect the external flasher 3. Connect the power cord (This fixes internal power control) 4. Remove the power cord Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/t410.md A Documentation/mainboard/lenovo/t410_chip_location.jpg A src/mainboard/lenovo/t410/Kconfig A src/mainboard/lenovo/t410/Kconfig.name A src/mainboard/lenovo/t410/Makefile.inc A src/mainboard/lenovo/t410/acpi/dock.asl A src/mainboard/lenovo/t410/acpi/ec.asl A src/mainboard/lenovo/t410/acpi/gpe.asl A src/mainboard/lenovo/t410/acpi/platform.asl A src/mainboard/lenovo/t410/acpi/superio.asl A src/mainboard/lenovo/t410/acpi_tables.c A src/mainboard/lenovo/t410/board_info.txt A src/mainboard/lenovo/t410/cmos.default A src/mainboard/lenovo/t410/cmos.layout A src/mainboard/lenovo/t410/data.vbt A src/mainboard/lenovo/t410/devicetree.cb A src/mainboard/lenovo/t410/dock.c A src/mainboard/lenovo/t410/dock.h A src/mainboard/lenovo/t410/dsdt.asl A src/mainboard/lenovo/t410/gma-mainboard.ads A src/mainboard/lenovo/t410/gpio.c A src/mainboard/lenovo/t410/hda_verb.c A src/mainboard/lenovo/t410/mainboard.c A src/mainboard/lenovo/t410/romstage.c A src/mainboard/lenovo/t410/smi.h A src/mainboard/lenovo/t410/smihandler.c A src/mainboard/lenovo/t410/thermal.h 28 files changed, 1,821 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/11791/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 16 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Degen Gerrit-CC: Matt Parnell <mparnell(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/up/squared: Do RAM config based on SKU ID
by Felix Singer (Code Review) 16 Sep '19

16 Sep '19

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34838 ) Change subject: mb/up/squared: Do RAM config based on SKU ID ...................................................................... mb/up/squared: Do RAM config based on SKU ID Change-Id: Ic121652213d5b1f65cff2f3096e919a3cf88db72 Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/mainboard/up/squared/romstage.c A src/mainboard/up/squared/romstage.h 2 files changed, 109 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/34838/1 diff --git a/src/mainboard/up/squared/romstage.c b/src/mainboard/up/squared/romstage.c index 2cfaa00..c1c52ad 100644 --- a/src/mainboard/up/squared/romstage.c +++ b/src/mainboard/up/squared/romstage.c @@ -15,10 +15,20 @@ #include <string.h> #include <soc/romstage.h> +#include <soc/gpio_apl.h> #include <fsp/api.h> #include <FspmUpd.h> #include <console/console.h> +#include <gpio.h> #include "gpio.h" +#include "romstage.h" + +/* + * Offsets: + * - GPIO_27: 0xd8 + * - GPIO_28: 0xe0 + */ +const uint8_t memory_skuid_pads[] = { GPIO_27, GPIO_28 }; static const uint8_t ch0_bit_swizzling[] = { 0x0D, 0x0A, 0x08, 0x0B, 0x0C, 0x0F, 0x0E, 0x09, @@ -48,49 +58,101 @@ 0x19, 0x1F, 0x1D, 0x1B, 0x1E, 0x18, 0x1C, 0x1A }; - void mainboard_memory_init_params(FSPM_UPD *memupd) { printk(BIOS_DEBUG, "MAINBOARD: %s/%s called\n", __FILE__, __func__); + FSP_M_CONFIG *config = &memupd->FspmConfig; + + uint8_t memory_skuid = get_memory_skuid(); + + switch (memory_skuid) { + case 0: /* 2GB */ + config->DualRankSupportEnable = 0; + config->Ch0_RankEnable = 1; + config->Ch0_DramDensity = 2; + config->Ch1_RankEnable = 1; + config->Ch1_DramDensity = 2; + config->Ch2_RankEnable = 0; + config->Ch3_RankEnable = 0; + break; + case 1: /* 4GB */ + config->DualRankSupportEnable = 1; + config->Ch0_RankEnable = 1; + config->Ch0_DramDensity = 2; + config->Ch1_RankEnable = 1; + config->Ch1_DramDensity = 2; + config->Ch2_RankEnable = 1; + config->Ch2_DramDensity = 2; + config->Ch3_RankEnable = 1; + config->Ch3_DramDensity = 2; + break; + case 2: /* 8GB */ + config->DualRankSupportEnable = 1; + config->Ch0_RankEnable = 3; + config->Ch0_DramDensity = 2; + config->Ch1_RankEnable = 3; + config->Ch1_DramDensity = 2; + config->Ch2_RankEnable = 3; + config->Ch2_DramDensity = 2; + config->Ch3_RankEnable = 3; + config->Ch3_DramDensity = 2; + break; + default: + break; + } + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); - memupd->FspmConfig.Package = 0x1; // 0x0 - memupd->FspmConfig.Profile = 0xB; // 0x19 - memupd->FspmConfig.MemoryDown = 0x1; // 0x0 - memupd->FspmConfig.DDR3LPageSize = 0x0; // 0x1 - memupd->FspmConfig.DIMM0SPDAddress = 0x0; // 0xa0 - memupd->FspmConfig.DIMM1SPDAddress = 0x0; // 0xa4 - memupd->FspmConfig.RmtCheckRun = 0x3; // 0x0 - memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0xC8; // 0x0 - memupd->FspmConfig.EnhancePort8xhDecoding = 0x0; // 0x1 - memupd->FspmConfig.NpkEn = 0x0; // 0x3 - memupd->FspmConfig.PrimaryVideoAdaptor = 0x2; // 0x0 + config->Package = 0x1; // 0x0 + config->Profile = 0xB; // 0x19 + config->MemoryDown = 0x1; // 0x0 + config->DDR3LPageSize = 0x0; // 0x1 + config->DIMM0SPDAddress = 0x0; // 0xa0 + config->DIMM1SPDAddress = 0x0; // 0xa4 + config->RmtCheckRun = 0x3; // 0x0 + config->RmtMarginCheckScaleHighThreshold = 0xC8; // 0x0 + config->EnhancePort8xhDecoding = 0x0; // 0x1 + config->NpkEn = 0x0; // 0x3 + config->PrimaryVideoAdaptor = 0x2; // 0x0 - memupd->FspmConfig.Ch0_RankEnable = 0x1; // 0x0 - memupd->FspmConfig.Ch0_DeviceWidth = 0x1; // 0x0 - memupd->FspmConfig.Ch0_DramDensity = 0x2; // 0x0 - memupd->FspmConfig.Ch0_Option = 0x3; // 0x0 - memupd->FspmConfig.Ch1_RankEnable = 0x1; // 0x0 - memupd->FspmConfig.Ch1_DeviceWidth = 0x1; // 0x0 - memupd->FspmConfig.Ch1_DramDensity = 0x2; // 0x0 - memupd->FspmConfig.Ch1_Option = 0x3; // 0x0 - memupd->FspmConfig.Ch2_RankEnable = 0x1; // 0x0 - memupd->FspmConfig.Ch2_DeviceWidth = 0x1; // 0x0 - memupd->FspmConfig.Ch2_DramDensity = 0x2; // 0x0 - memupd->FspmConfig.Ch2_Option = 0x3; // 0x0 - memupd->FspmConfig.Ch3_RankEnable = 0x1; // 0x0 - memupd->FspmConfig.Ch3_DeviceWidth = 0x1; // 0x0 - memupd->FspmConfig.Ch3_DramDensity = 0x2; // 0x0 - memupd->FspmConfig.Ch3_Option = 0x3; // 0x0 - memupd->FspmConfig.StartTimerTickerOfPfetAssert = 0x4E20; // 0x0 + config->Ch0_RankEnable = 0x1; // 0x0 + config->Ch0_DeviceWidth = 0x1; // 0x0 + config->Ch0_DramDensity = 0x2; // 0x0 + config->Ch0_Option = 0x3; // 0x0 + config->Ch1_RankEnable = 0x1; // 0x0 + config->Ch1_DeviceWidth = 0x1; // 0x0 + config->Ch1_DramDensity = 0x2; // 0x0 + config->Ch1_Option = 0x3; // 0x0 + config->Ch2_RankEnable = 0x1; // 0x0 + config->Ch2_DeviceWidth = 0x1; // 0x0 + config->Ch2_DramDensity = 0x2; // 0x0 + config->Ch2_Option = 0x3; // 0x0 + config->Ch3_RankEnable = 0x1; // 0x0 + config->Ch3_DeviceWidth = 0x1; // 0x0 + config->Ch3_DramDensity = 0x2; // 0x0 + config->Ch3_Option = 0x3; // 0x0 + config->StartTimerTickerOfPfetAssert = 0x4E20; // 0x0 - memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &ch0_bit_swizzling, + memcpy(config->Ch0_Bit_swizzling, &ch0_bit_swizzling, sizeof(ch0_bit_swizzling)); - memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &ch1_bit_swizzling, + memcpy(config->Ch1_Bit_swizzling, &ch1_bit_swizzling, sizeof(ch1_bit_swizzling)); - memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &ch2_bit_swizzling, + memcpy(config->Ch2_Bit_swizzling, &ch2_bit_swizzling, sizeof(ch2_bit_swizzling)); - memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &ch3_bit_swizzling, + memcpy(config->Ch3_Bit_swizzling, &ch3_bit_swizzling, sizeof(ch3_bit_swizzling)); } + +uint8_t get_memory_skuid(void) +{ + uint8_t memory_skuid = 0; + + for (uint8_t i = 0; i < ARRAY_SIZE(memory_skuid_pads); i++) { + uint32_t gpio_value = gpio_get(memory_skuid_pads[i]); + uint8_t rx_state = gpio_value & 0x2; + memory_skuid |= rx_state << i; + } + memory_skuid = memory_skuid & 0x3; + return memory_skuid; +} diff --git a/src/mainboard/up/squared/romstage.h b/src/mainboard/up/squared/romstage.h new file mode 100644 index 0000000..5c0f4ba --- /dev/null +++ b/src/mainboard/up/squared/romstage.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +uint8_t get_memory_skuid(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/34838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic121652213d5b1f65cff2f3096e919a3cf88db72 Gerrit-Change-Number: 34838 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mainboard: Remove unused include <device/pci_ops.h>
by HAOUAS Elyes (Code Review) 16 Sep '19

16 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33528 Change subject: src/mainboard: Remove unused include <device/pci_ops.h> ...................................................................... src/mainboard: Remove unused include <device/pci_ops.h> Change-Id: Icdbccb3af294dd97ba1835f034669198094a3661 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/apple/macbook21/mainboard.c M src/mainboard/asus/kcma-d8/bootblock.c M src/mainboard/asus/kgpe-d16/bootblock.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/google/beltino/mainboard.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/parrot/mainboard.c M src/mainboard/google/rambi/mainboard.c M src/mainboard/google/slippy/mainboard.c M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/baskingridge/mainboard.c M src/mainboard/intel/bayleybay_fsp/mainboard.c M src/mainboard/intel/camelbackmountain_fsp/mainboard.c M src/mainboard/intel/d510mo/mainboard.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/emeraldlake2/mainboard.c M src/mainboard/intel/wtm2/mainboard.c M src/mainboard/kontron/ktqm77/mainboard.c M src/mainboard/samsung/lumpy/mainboard.c M src/mainboard/siemens/mc_tcu3/mainboard.c M src/mainboard/via/epia-m850/mainboard.c 25 files changed, 0 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/33528/1 diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 4a817cf..82bc71c 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -17,7 +17,6 @@ #include <stdint.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <timestamp.h> diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 7b2f051..7f3fb0c 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -18,7 +18,6 @@ #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> -#include <device/pci_ops.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index 798fc12..b2aafe3 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -17,7 +17,6 @@ #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <arch/interrupt.h> #include <northbridge/intel/i945/i945.h> #include <arch/acpigen.h> diff --git a/src/mainboard/asus/kcma-d8/bootblock.c b/src/mainboard/asus/kcma-d8/bootblock.c index 543ffed..b370ae0 100644 --- a/src/mainboard/asus/kcma-d8/bootblock.c +++ b/src/mainboard/asus/kcma-d8/bootblock.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include <device/pci_ops.h> #include <pc80/mc146818rtc.h> void bootblock_mainboard_init(void) diff --git a/src/mainboard/asus/kgpe-d16/bootblock.c b/src/mainboard/asus/kgpe-d16/bootblock.c index 543ffed..b370ae0 100644 --- a/src/mainboard/asus/kgpe-d16/bootblock.c +++ b/src/mainboard/asus/kgpe-d16/bootblock.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include <device/pci_ops.h> #include <pc80/mc146818rtc.h> void bootblock_mainboard_init(void) diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 9216ecb..492c978 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 9347919..33e4388 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -17,7 +17,6 @@ #include <stdint.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> diff --git a/src/mainboard/google/beltino/mainboard.c b/src/mainboard/google/beltino/mainboard.c index 7bda2f6..347017d 100644 --- a/src/mainboard/google/beltino/mainboard.c +++ b/src/mainboard/google/beltino/mainboard.c @@ -21,7 +21,6 @@ #include <boot/coreboot_tables.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <southbridge/intel/lynxpoint/pch.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 7f72ad2..dacf0cf 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -16,7 +16,6 @@ #include <console/console.h> #include <string.h> #include <bootmode.h> -#include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c index 8c3ad63..d37ff23 100644 --- a/src/mainboard/google/parrot/mainboard.c +++ b/src/mainboard/google/parrot/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> #include <arch/io.h> diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index d3f6164..30be5f7 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <console/console.h> #if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> diff --git a/src/mainboard/google/slippy/mainboard.c b/src/mainboard/google/slippy/mainboard.c index b98fc8a..58e708b 100644 --- a/src/mainboard/google/slippy/mainboard.c +++ b/src/mainboard/google/slippy/mainboard.c @@ -18,7 +18,6 @@ #include <smbios.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> #include <arch/io.h> diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index c02b0e6..5291247 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -24,7 +24,6 @@ #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> -#include <device/pci_ops.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> #include "option_table.h" diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 6561927..2668af1 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -15,7 +15,6 @@ #include <string.h> #include <bootmode.h> -#include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c index 49e66bf..96b0aee 100644 --- a/src/mainboard/intel/baskingridge/mainboard.c +++ b/src/mainboard/intel/baskingridge/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> #include <arch/io.h> diff --git a/src/mainboard/intel/bayleybay_fsp/mainboard.c b/src/mainboard/intel/bayleybay_fsp/mainboard.c index 16c1844..590cc46 100644 --- a/src/mainboard/intel/bayleybay_fsp/mainboard.c +++ b/src/mainboard/intel/bayleybay_fsp/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif diff --git a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c index ee9f36e..494d9fa 100644 --- a/src/mainboard/intel/camelbackmountain_fsp/mainboard.c +++ b/src/mainboard/intel/camelbackmountain_fsp/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif diff --git a/src/mainboard/intel/d510mo/mainboard.c b/src/mainboard/intel/d510mo/mainboard.c index d2751bc..cac5064 100644 --- a/src/mainboard/intel/d510mo/mainboard.c +++ b/src/mainboard/intel/d510mo/mainboard.c @@ -15,7 +15,6 @@ #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <device/pci.h> #include <drivers/intel/gma/int15.h> diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 699141f..226411e 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -15,7 +15,6 @@ #include <string.h> #include <bootmode.h> -#include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/bd82x6x/pch.h> diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c index d07da83..3032ff4 100644 --- a/src/mainboard/intel/emeraldlake2/mainboard.c +++ b/src/mainboard/intel/emeraldlake2/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> #include <arch/interrupt.h> diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index 4bfd039..ba17b1d 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -17,7 +17,6 @@ #include <types.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> #include <arch/io.h> diff --git a/src/mainboard/kontron/ktqm77/mainboard.c b/src/mainboard/kontron/ktqm77/mainboard.c index afedbfc..675cb05 100644 --- a/src/mainboard/kontron/ktqm77/mainboard.c +++ b/src/mainboard/kontron/ktqm77/mainboard.c @@ -18,7 +18,6 @@ #include <types.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <console/console.h> #if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c index 8664217..7aad98c 100644 --- a/src/mainboard/samsung/lumpy/mainboard.c +++ b/src/mainboard/samsung/lumpy/mainboard.c @@ -18,7 +18,6 @@ #include <string.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <drivers/intel/gma/int15.h> #include <arch/acpi.h> #include <arch/interrupt.h> diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c index 169b04d..dd0f2ed 100644 --- a/src/mainboard/siemens/mc_tcu3/mainboard.c +++ b/src/mainboard/siemens/mc_tcu3/mainboard.c @@ -18,7 +18,6 @@ #include <string.h> #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif diff --git a/src/mainboard/via/epia-m850/mainboard.c b/src/mainboard/via/epia-m850/mainboard.c index e7d65a0..03699db 100644 --- a/src/mainboard/via/epia-m850/mainboard.c +++ b/src/mainboard/via/epia-m850/mainboard.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci_def.h> -#include <device/pci_ops.h> #include <console/console.h> #if CONFIG(VGA_ROM_RUN) -- To view, visit https://review.coreboot.org/c/coreboot/+/33528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdbccb3af294dd97ba1835f034669198094a3661 Gerrit-Change-Number: 33528 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mediatek/mt8183: Add soc ARM Trusted Firmware support
by Patrick Georgi (Code Review) 16 Sep '19

16 Sep '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/29186 ) Change subject: mediatek/mt8183: Add soc ARM Trusted Firmware support ...................................................................... mediatek/mt8183: Add soc ARM Trusted Firmware support Set BL31 platform to mt8183 to link with ARM Trusted Firmware. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui with more patches in ATF. Change-Id: Ia988d2b4ed646027c04c7c6ff0e50ed7a0b14da3 Signed-off-by: kenny liang <kenny.liang(a)mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29186 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/soc/mediatek/mt8183/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index cac793f..b6c3a33 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -67,6 +67,8 @@ sspm.bin-type := raw sspm.bin-compression := $(CBFS_COMPRESS_FLAG) +BL31_MAKEARGS += PLAT=mt8183 + CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include -- To view, visit https://review.coreboot.org/c/coreboot/+/29186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia988d2b4ed646027c04c7c6ff0e50ed7a0b14da3 Gerrit-Change-Number: 29186 Gerrit-PatchSet: 16 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Erin Lo <erin.lo(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: jitao shi <jitao.shi(a)mediatek.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Rizwan Qureshi (Code Review) 16 Sep '19

16 Sep '19

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 46: (1 comment) https://review.coreboot.org/c/coreboot/+/27369/30/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/ucode_update.c: https://review.coreboot.org/c/coreboot/+/27369/30/src/soc/intel/common/base… PS30, Line 172: if (get_current_microcode_rev() != slot_rev) { > Yes, checking if the new microcode is accepted by the processor, only then proceed with update. removed this check, putting the onus of pushing a processor specific update to a device on the updater. This also gives one advantage where we can move the ucode update early in romstage, since the mock load cannot be done when CAR (NEM) is enabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 46 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Mon, 16 Sep 2019 06:34:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Rizwan Qureshi (Code Review) 16 Sep '19

16 Sep '19

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 46: (4 comments) https://review.coreboot.org/c/coreboot/+/27369/36//COMMIT_MSG Commit Message: PS36: > Just for the future (not saying you should change it here as […] Done https://review.coreboot.org/c/coreboot/+/27369/19/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/ucode_update.c: https://review.coreboot.org/c/coreboot/+/27369/19/src/soc/intel/common/base… PS19, Line 92: boot_device_rw_subregion(&st_region, &write_rdev) < 0) > I thought it is cleaner and avoid fmap_parsing. […] Done https://review.coreboot.org/c/coreboot/+/27369/19/src/soc/intel/common/base… PS19, Line 92: boot_device_rw_subregion(&st_region, &write_rdev) < 0) > I thought it is cleaner and avoid fmap_parsing. […] Done https://review.coreboot.org/c/coreboot/+/27369/30/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/ucode_update.c: https://review.coreboot.org/c/coreboot/+/27369/30/src/soc/intel/common/base… PS30, Line 103: static int protect_staging(void) > Claim an FPR and set the range as soon as you get an opportunity. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 46 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Mon, 16 Sep 2019 06:31:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Aaron Durbin <adurbin(a)chromium.org> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Rizwan Qureshi (Code Review) 16 Sep '19

16 Sep '19

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 46: (5 comments) https://review.coreboot.org/c/coreboot/+/27369/30/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/ucode_update.c: https://review.coreboot.org/c/coreboot/+/27369/30/src/soc/intel/common/base… PS30, Line 33: define locate_staging_rw(rdev) \ : fmap_locate_area_as_rdev_rw(CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG, \ : rdev) : : #define locate_staging_ro(rdev) \ : fmap_locate_area_as_rdev(CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG, \ : rdev) > If it's only about the line length, how about giving these long […] Done https://review.coreboot.org/c/coreboot/+/27369/30/src/soc/intel/common/base… PS30, Line 62: stage_microcode = rdev_mmap_full(&staging_rdev); > That requires us to allocate a buffer here. Wanted to avoid that hence the mmap. Done https://review.coreboot.org/c/coreboot/+/27369/30/src/soc/intel/common/base… PS30, Line 118: check_and_update_ucode > Because the FIT table will be in RO. I don't think we need to check that. Done https://review.coreboot.org/c/coreboot/+/27369/30/src/soc/intel/common/base… PS30, Line 130: if (ucode_update_rec_mode_enabled()) { > AFAIK, there is no clear line where coreboot ends. You could say, […] Done https://review.coreboot.org/c/coreboot/+/27369/30/src/soc/intel/common/base… PS30, Line 179: * write does not finish and we end up not loading > you mean add an additional check for checksum at line 163 for checksum? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 46 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Mon, 16 Sep 2019 06:26:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/kohaku: Update USB port settings
by shkim (Code Review) 16 Sep '19

16 Sep '19

Hello Seunghwan Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35236 to review the following change. Change subject: mb/google/kohaku: Update USB port settings ...................................................................... mb/google/kohaku: Update USB port settings This change overrides USB port settings for kohaku. Some port settings are same with baseboard, but I'd like to describe all settings here to be aware of current setting and usage of USB ports on kohaku. Change-Id: I5ac05485d1cd94416e5a0aecf7fa6769bd7c9e84 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/35236/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 9e33bac..adfca17 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -23,6 +23,24 @@ # Enable DMIC1 register "PchHdaAudioLinkDmic1" = "1" + register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 0 + register "usb2_ports[1]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1 + register "usb2_ports[2]" = "USB2_PORT_EMPTY" + register "usb2_ports[3]" = "USB2_PORT_LONG(OC_SKIP)" # SD CARD + register "usb2_ports[4]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_EMPTY" + register "usb2_ports[6]" = "USB2_PORT_LONG(OC_SKIP)" # Camera + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # CnVi BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # World facing camera + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD CARD + register "usb3_ports[4]" = "USB3_PORT_EMPTY" + register "usb3_ports[5]" = "USB3_PORT_EMPTY" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/35236 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ac05485d1cd94416e5a0aecf7fa6769bd7c9e84 Gerrit-Change-Number: 35236 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2019