coreboot-gerrit September 2019

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Change in coreboot[master]: cpu/allwinner: Prepend the BOOT0 header to the bootblock.bin
by Arthur Heymans (Code Review) 14 Sep '19

14 Sep '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35411 ) Change subject: cpu/allwinner: Prepend the BOOT0 header to the bootblock.bin ...................................................................... cpu/allwinner: Prepend the BOOT0 header to the bootblock.bin Instead of prepending the BOOT0 header to the full coreboot.rom to create a new file called BOOT0, prepend to the bootblock.bin that gets included in BOOTBLOCK FMAP region. This updates mksunxiboot to reflect that it only operates on the raw bootblock.bin and not the final image: - given the necessary alignment on some boot media assume that the remainder bytes after the bootblock will be filled with 1's - don't allow bootblocks larger than 24K as the BROM won't load these fully anyway. Change-Id: I974a6aaa1a340c6b26f78b9d038be0f580331831 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/allwinner/a10/Makefile.inc M util/arm_boot_tools/mksunxiboot/mksunxiboot.c 2 files changed, 15 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/35411/1 diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index a6cd4b4..9f5f6ac 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -25,8 +25,6 @@ romstage-y += uart.c uart_console.c ramstage-y += uart.c uart_console.c -real-target: $(obj)/BOOT0 - get_bootblock_size= \ $(eval bb_s=$(shell $(CBFSTOOL) $(1) print | grep bootblocksize | \ sed 's/[^0-9 ]//g')) \ @@ -46,11 +44,11 @@ # under util/arm_boot_tools/mksunxiboot. The boot ROM will load at most 24KiB of # data to SRAM. The BOOT0 header takes 32 bytes, so bootblock is limited to # 24KiB - 32 bytes. -# TODO: make mksunxiboot take the bootblock size as a parameter # TODO: print an error if bootblock is too large (maybe place ROMSTAGE at the # exact offset needed to collide with the bootblock) # FIXME: A10 loads 24KiB. According to Oliver other chips load a little more # -$(obj)/BOOT0: $(obj)/coreboot.rom $(MKSUNXIBOOT) - @printf " BOOT0 $(subst $(obj)/,,$(^))\n" + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(MKSUNXIBOOT) + @printf " Prepending BOOT0 header $(subst $(obj)/,,$(^))\n" $(MKSUNXIBOOT) $(word 1, $^) $@ diff --git a/util/arm_boot_tools/mksunxiboot/mksunxiboot.c b/util/arm_boot_tools/mksunxiboot/mksunxiboot.c index 58765b1..50771e9 100644 --- a/util/arm_boot_tools/mksunxiboot/mksunxiboot.c +++ b/util/arm_boot_tools/mksunxiboot/mksunxiboot.c @@ -62,7 +62,7 @@ } /* Check sum function from sun4i boot code */ -static int fill_check_sum(struct boot_file_head *hdr, const void *boot_code) +static int fill_check_sum(struct boot_file_head *hdr, const void *boot_code, size_t load_size) { size_t i; uint8_t raw_hdr[HEADER_SIZE]; @@ -83,9 +83,14 @@ chksum += le32_to_h(raw_hdr + i); /* Checksum the boot code */ - for (i = 0; i < hdr->length - HEADER_SIZE; i += 4) + for (i = 0; i < load_size; i += 4) chksum += le32_to_h(boot_code + i); + /* Given that the hdr.length is aligned one can assume that the + remaining bytes covered by the length are all 1's */ + for (i = 0; i < hdr->length - load_size- HEADER_SIZE; i +=4) + chksum += 0xffffffff; + /* write back check sum */ hdr->check_sum = chksum; @@ -165,8 +170,10 @@ load_size = align(file_size, sizeof(uint32_t)); - if (load_size > SRAM_LOAD_MAX_SIZE) - load_size = SRAM_LOAD_MAX_SIZE; + if (load_size > SRAM_LOAD_MAX_SIZE) { + fprintf(stderr, "Bootblock larger than the max 24K!\n"); + return EXIT_FAILURE; + } printf("Load size: 0x%x\n", load_size); @@ -178,7 +185,7 @@ /* Fill the header */ fill_header(&hdr, load_size); - fill_check_sum(&hdr, file_data); + fill_check_sum(&hdr, file_data, load_size); /* Now write the header */ serialize_header(raw_hdr, &hdr); -- To view, visit https://review.coreboot.org/c/coreboot/+/35411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I974a6aaa1a340c6b26f78b9d038be0f580331831 Gerrit-Change-Number: 35411 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/lenovo/t410: Add new port
by Peter Lemenkov (Code Review) 14 Sep '19

14 Sep '19

Peter Lemenkov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: mainboard/lenovo/t410: Add new port ...................................................................... Patch Set 15: (2 comments) https://review.coreboot.org/c/coreboot/+/11791/15/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/mainboard.c: https://review.coreboot.org/c/coreboot/+/11791/15/src/mainboard/lenovo/t410… PS15, Line 33: static void mainboard_init(struct device *dev) I think this RCBA configuration may be removed. See commit b236cba61558649791224cf35357568bfe3b30db. https://review.coreboot.org/c/coreboot/+/11791/15/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/smihandler.c: https://review.coreboot.org/c/coreboot/+/11791/15/src/mainboard/lenovo/t410… PS15, Line 21: #include <southbridge/intel/ibexpeak/pch.h> I believe this include is no longer necessary since commit 548f33a9f4a7675c42822516c285bdf2c8bb64de -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 15 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Degen Gerrit-CC: Matt Parnell <mparnell(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Sat, 14 Sep 2019 15:42:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: security/vboot: Replace use of __PRE_RAM__
by Kyösti Mälkki (Code Review) 14 Sep '19

14 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35387 ) Change subject: security/vboot: Replace use of __PRE_RAM__ ...................................................................... security/vboot: Replace use of __PRE_RAM__ Change-Id: Ibaeda2762c733fdbe48979b635cc0cfd7ee4295d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/security/vboot/misc.h 1 file changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/35387/1 diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 725f5fd..1458354 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -117,11 +117,7 @@ return !ENV_BOOTBLOCK; } else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { /* Post-RAM stages are "after the romstage" */ -#ifdef __PRE_RAM__ - return 0; -#else - return 1; -#endif + return !ENV_ROMSTAGE_OR_BEFORE; } else { dead_code(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibaeda2762c733fdbe48979b635cc0cfd7ee4295d Gerrit-Change-Number: 35387 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/: Replace some __PRE_RAM__ use
by Kyösti Mälkki (Code Review) 14 Sep '19

14 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35398 ) Change subject: src/: Replace some __PRE_RAM__ use ...................................................................... src/: Replace some __PRE_RAM__ use Change-Id: Iaa56e7b98aad33eeb876edd7465c56c80fd1ac18 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/console/init.c M src/include/device/pci_ehci.h M src/include/memlayout.h M src/include/thread.h M src/lib/cbmem_console.c M src/lib/imd_cbmem.c M src/lib/program.ld M src/lib/reg_script.c 8 files changed, 19 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/35398/1 diff --git a/src/console/init.c b/src/console/init.c index 4859980..d481858 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -22,11 +22,7 @@ #include <version.h> /* Mutable console log level only allowed when RAM comes online. */ -#if defined(__PRE_RAM__) -#define CONSOLE_LEVEL_CONST 1 -#else -#define CONSOLE_LEVEL_CONST 0 -#endif +#define CONSOLE_LEVEL_CONST !ENV_STAGE_HAS_DATA_SECTION static int console_inited CAR_GLOBAL; static int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; diff --git a/src/include/device/pci_ehci.h b/src/include/device/pci_ehci.h index 6e59854..e9a7776 100644 --- a/src/include/device/pci_ehci.h +++ b/src/include/device/pci_ehci.h @@ -31,7 +31,6 @@ u8 *pci_ehci_base_regs(pci_devfn_t dev); void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port); -#ifndef __PRE_RAM__ #if !CONFIG(USBDEBUG) #define pci_ehci_read_resources pci_dev_read_resources #else @@ -46,6 +45,5 @@ struct device; void pci_ehci_read_resources(struct device *dev); #endif -#endif #endif /* _PCI_EHCI_H_ */ diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 505ccc1..0100e27 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -73,7 +73,7 @@ ALIAS_REGION(cbfs_cache, preram_cbfs_cache) \ ALIAS_REGION(cbfs_cache, postram_cbfs_cache) -#if defined(__PRE_RAM__) +#if ENV_ROMSTAGE_OR_BEFORE #define PRERAM_CBFS_CACHE(addr, size) \ REGION(preram_cbfs_cache, addr, size, 4) \ ALIAS_REGION(preram_cbfs_cache, cbfs_cache) diff --git a/src/include/thread.h b/src/include/thread.h index e6af2ef..b66803e 100644 --- a/src/include/thread.h +++ b/src/include/thread.h @@ -20,7 +20,7 @@ #include <bootstate.h> #include <arch/cpu.h> -#if CONFIG(COOP_MULTITASKING) && !defined(__SMM__) && !defined(__PRE_RAM__) +#if ENV_RAMSTAGE && CONFIG(COOP_MULTITASKING) struct thread { int id; diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 18c3b71..7876ff5 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -51,16 +51,11 @@ static struct cbmem_console *cbmem_console_p CAR_GLOBAL; -#ifdef __PRE_RAM__ /* * While running from ROM, before DRAM is initialized, some area in cache as * RAM space is used for the console buffer storage. The size and location of * the area are defined by the linker script with _(e)preram_cbmem_console. - */ - -#else - -/* + * * When running from RAM, some console output is generated before CBMEM is * reinitialized. This static buffer is used to store that output temporarily, * to be concatenated with the CBMEM console buffer contents accumulated @@ -69,7 +64,6 @@ #define STATIC_CONSOLE_SIZE 1024 static u8 static_console[STATIC_CONSOLE_SIZE]; -#endif static struct cbmem_console *current_console(void) { @@ -107,14 +101,13 @@ void cbmemc_init(void) { -#ifdef __PRE_RAM__ - /* Pre-RAM environments use special buffer placed by linker script. */ - init_console_ptr(_preram_cbmem_console, - REGION_SIZE(preram_cbmem_console)); -#else - /* Post-RAM uses static (BSS) buffer before CBMEM is reinitialized. */ - init_console_ptr(static_console, sizeof(static_console)); -#endif + if (ENV_ROMSTAGE_OR_BEFORE) { + /* Pre-RAM environments use special buffer placed by linker script. */ + init_console_ptr(_preram_cbmem_console, REGION_SIZE(preram_cbmem_console)); + } else { + /* Post-RAM uses static (BSS) buffer before CBMEM is reinitialized. */ + init_console_ptr(static_console, sizeof(static_console)); + } } void cbmemc_tx_byte(unsigned char data) diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index e5c3e41..f04e086 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -172,14 +172,13 @@ if (imd_recover(imd)) return 1; -#if defined(__PRE_RAM__) /* * Lock the imd in romstage on a recovery. The assumption is that * if the imd area was recovered in romstage then S3 resume path * is being taken. */ - imd_lockdown(imd); -#endif + if (ENV_ROMSTAGE) + imd_lockdown(imd); /* Add the specified range first */ if (size) diff --git a/src/lib/program.ld b/src/lib/program.ld index ad364a4..a9d4e48 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -108,7 +108,7 @@ *(.sdata); *(.sdata.*); -#ifdef __PRE_RAM__ +#if ENV_ROMSTAGE_OR_BEFORE PROVIDE(_preram_cbmem_console = .); PROVIDE(_epreram_cbmem_console = _preram_cbmem_console); #elif ENV_RAMSTAGE diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 50cf7b6..0c033ed 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -36,7 +36,8 @@ #endif #define POLL_DELAY 100 /* 100us */ -#if defined(__PRE_RAM__) + +#ifdef __SIMPLE_DEVICE__ #define EMPTY_DEV 0 #else #define EMPTY_DEV NULL @@ -68,9 +69,9 @@ static struct resource *reg_script_get_resource(struct reg_script_context *ctx) { -#if defined(__PRE_RAM__) - return NULL; -#else + if (!ENV_RAMSTAGE) + return NULL; + struct resource *res; const struct reg_script *step = reg_script_get_step(ctx); @@ -82,7 +83,6 @@ res = find_resource(ctx->dev, step->res_index); ctx->res = res; return res; -#endif } static uint32_t reg_script_read_pci(struct reg_script_context *ctx) -- To view, visit https://review.coreboot.org/c/coreboot/+/35398 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa56e7b98aad33eeb876edd7465c56c80fd1ac18 Gerrit-Change-Number: 35398 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/acpi: Replace __PRE_RAM__ use
by Kyösti Mälkki (Code Review) 14 Sep '19

14 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35397 ) Change subject: ec/acpi: Replace __PRE_RAM__ use ...................................................................... ec/acpi: Replace __PRE_RAM__ use Change-Id: Iae31569f16168ba00ce272e4777f3a69bcd6ee94 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/ec/acpi/ec.c 1 file changed, 6 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/35397/1 diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c index 481622c..939ff78 100644 --- a/src/ec/acpi/ec.c +++ b/src/ec/acpi/ec.c @@ -18,19 +18,11 @@ #include <device/device.h> #include <arch/io.h> #include <delay.h> +#include <stdint.h> #include "ec.h" -#ifdef __PRE_RAM__ - -static const int ec_cmd_reg = EC_SC; -static const int ec_data_reg = EC_DATA; - -#else - -static int ec_cmd_reg = EC_SC; -static int ec_data_reg = EC_DATA; - -#endif +static u16 ec_cmd_reg = EC_SC; +static u16 ec_data_reg = EC_DATA; int send_ec_command(u8 command) { @@ -162,16 +154,15 @@ ec_write(addr, ec_read(addr) & ~(1 << bit)); } -#ifndef __PRE_RAM__ - void ec_set_ports(u16 cmd_reg, u16 data_reg) { + if (!ENV_STAGE_HAS_DATA_SECTION) + return; + ec_cmd_reg = cmd_reg; ec_data_reg = data_reg; } -#endif - struct chip_operations ec_acpi_ops = { CHIP_NAME("ACPI Embedded Controller") }; -- To view, visit https://review.coreboot.org/c/coreboot/+/35397 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae31569f16168ba00ce272e4777f3a69bcd6ee94 Gerrit-Change-Number: 35397 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] arch/x86: Replace some __PRE_RAM__ use
by Kyösti Mälkki (Code Review) 14 Sep '19

14 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35390 ) Change subject: [WIP] arch/x86: Replace some __PRE_RAM__ use ...................................................................... [WIP] arch/x86: Replace some __PRE_RAM__ use Change-Id: I4d8db430f8cd0bf0f161fc5cef052f153e59e2bc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/include/arch/acpi.h M src/include/cpu/amd/mtrr.h M src/include/cpu/x86/cache.h M src/include/cpu/x86/lapic.h 4 files changed, 2 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/35390/1 diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 42e45fb..6cd4e9f 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -974,7 +974,7 @@ #if CONFIG(HAVE_ACPI_RESUME) -#ifdef __PRE_RAM__ +#if ENV_ROMSTAGE_OR_BEFORE static inline int acpi_is_wakeup_s3(void) { return (acpi_get_sleep_type() == ACPI_S3); diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index f6b213e..edbf7bb 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -38,7 +38,7 @@ #define TOP_MEM_MASK 0x007fffff #define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10) -#if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__) +#if !defined(__ROMCC__) && !defined(__ASSEMBLER__) #include <cpu/x86/msr.h> diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 7f135e5..713ca32 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -84,9 +84,7 @@ wbinvd(); } -#if !defined(__PRE_RAM__) void x86_enable_cache(void); -#endif #endif /* !__ASSEMBLER__ */ #endif /* CPU_X86_CACHE */ diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 8108174..2c865eb 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -58,8 +58,6 @@ void stop_this_cpu(void); #endif -#if !defined(__PRE_RAM__) - #define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \ sizeof(*(ptr)))) @@ -156,6 +154,4 @@ struct device; int start_cpu(struct device *cpu); -#endif /* !__PRE_RAM__ */ - #endif /* CPU_X86_LAPIC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d8db430f8cd0bf0f161fc5cef052f153e59e2bc Gerrit-Change-Number: 35390 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/x86: Drop lapic_remote_read()
by Kyösti Mälkki (Code Review) 14 Sep '19

14 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35394 ) Change subject: cpu/x86: Drop lapic_remote_read() ...................................................................... cpu/x86: Drop lapic_remote_read() Unused and declaration conflicts with the one amdfam10-15 uses in romstage. Change-Id: Icd454431285b7c423a4f78d2a0085497d052adc9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/cpu/x86/lapic.h 1 file changed, 0 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/35394/1 diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 8108174..2f40742 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -113,30 +113,6 @@ # define lapic_write_around(x, y) lapic_write_atomic((x), (y)) #endif -static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue) -{ - int timeout; - unsigned long status; - int result; - lapic_wait_icr_idle(); - lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); - lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4)); - timeout = 0; - do { -#if 0 - udelay(100); -#endif - status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK; - } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000); - - result = -1; - if (status == LAPIC_ICR_RR_VALID) { - *pvalue = lapic_read(LAPIC_RRR); - result = 0; - } - return result; -} - void do_lapic_init(void); /* See if I need to initialize the local APIC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd454431285b7c423a4f78d2a0085497d052adc9 Gerrit-Change-Number: 35394 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86: Remove acpi_fail_wakeup() and cbmem_fail_resume()
by Kyösti Mälkki (Code Review) 14 Sep '19

14 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35389 ) Change subject: arch/x86: Remove acpi_fail_wakeup() and cbmem_fail_resume() ...................................................................... arch/x86: Remove acpi_fail_wakeup() and cbmem_fail_resume() Unused since commit d46b8d5. Change-Id: If0f1e0381dd7698f842dc1288ff222a4d5d4783c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/acpi_s3.c M src/arch/x86/cbmem.c M src/arch/x86/include/arch/acpi.h M src/include/cbmem.h M src/lib/cbmem_common.c 5 files changed, 0 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/35389/1 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 5553b2cc..52f8a20 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -60,12 +60,6 @@ acpi_handoff_wakeup(); return (acpi_slp_type == ACPI_S4); } - -void acpi_fail_wakeup(void) -{ - if (acpi_slp_type == ACPI_S3 || acpi_slp_type == ACPI_S2) - acpi_slp_type = ACPI_S0; -} #endif /* ENV_RAMSTAGE */ #define WAKEUP_BASE 0x600 diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c index 648633f..16c35b5 100644 --- a/src/arch/x86/cbmem.c +++ b/src/arch/x86/cbmem.c @@ -13,7 +13,6 @@ #include <stdlib.h> #include <cbmem.h> -#include <arch/acpi.h> #if CONFIG(CBMEM_TOP_BACKUP) @@ -35,13 +34,3 @@ } #endif /* CBMEM_TOP_BACKUP */ - -/* Something went wrong, our high memory area got wiped */ -void cbmem_fail_resume(void) -{ -#if !defined(__PRE_RAM__) && CONFIG(HAVE_ACPI_RESUME) - /* ACPI resume needs to be cleared in the fail-to-recover case, but that - * condition is only handled during ramstage. */ - acpi_fail_wakeup(); -#endif -} diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 14f0cdf..42e45fb 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -932,7 +932,6 @@ acpi_hest_esd_t *esd, u16 type, void *data, u16 len); /* For ACPI S3 support. */ -void acpi_fail_wakeup(void); void acpi_resume(void *wake_vec); void mainboard_suspend_resume(void); void *acpi_find_wakeup_vector(void); diff --git a/src/include/cbmem.h b/src/include/cbmem.h index f3df21d..f972ba6 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -106,7 +106,6 @@ /* Indicate to each hook if cbmem is being recovered or not. */ typedef void (* const cbmem_init_hook_t)(int is_recovery); void cbmem_run_init_hooks(int is_recovery); -void cbmem_fail_resume(void); /* Ramstage only functions. */ /* Add the cbmem memory used to the memory map at boot. */ diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index d86edf0..b018acb 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -32,7 +32,3 @@ init_hook_ptr++; } } - -void __weak cbmem_fail_resume(void) -{ -} -- To view, visit https://review.coreboot.org/c/coreboot/+/35389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0f1e0381dd7698f842dc1288ff222a4d5d4783c Gerrit-Change-Number: 35389 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Add Razer Blade Stealth (2016) H2U
by Christoph Pomaska (Code Review) 14 Sep '19

14 Sep '19

Christoph Pomaska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34475 ) Change subject: Add Razer Blade Stealth (2016) H2U ...................................................................... Patch Set 39: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/34475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Gerrit-Change-Number: 34475 Gerrit-PatchSet: 39 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 14 Sep 2019 10:21:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Add Razer Blade Stealth (2016) H2U
by build bot (Jenkins) (Code Review) 14 Sep '19

14 Sep '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34475 ) Change subject: Add Razer Blade Stealth (2016) H2U ...................................................................... Patch Set 39: (2 comments) https://review.coreboot.org/c/coreboot/+/34475/39/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c: https://review.coreboot.org/c/coreboot/+/34475/39/src/mainboard/razer/blade… PS39, Line 26: {0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00}}; space required after that close brace '}' https://review.coreboot.org/c/coreboot/+/34475/39/src/mainboard/razer/blade… PS39, Line 33: const u8 dqs_map[2][8] = {{0, 1, 3, 2, 4, 5, 6, 7}, {1, 0, 4, 5, 2, 3, 6, 7}}; space required after that close brace '}' -- To view, visit https://review.coreboot.org/c/coreboot/+/34475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Gerrit-Change-Number: 34475 Gerrit-PatchSet: 39 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 14 Sep 2019 09:36:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit September 2019