coreboot-gerrit September 2019

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Change in coreboot[master]: soc/intel/cnl: Remove unnecessary FSP UPD “PchPwrOptEnable” usage
by Subrata Banik (Code Review) 12 Sep '19

12 Sep '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35323 ) Change subject: soc/intel/cnl: Remove unnecessary FSP UPD “PchPwrOptEnable” usage ...................................................................... soc/intel/cnl: Remove unnecessary FSP UPD “PchPwrOptEnable” usage PchPwrOptEnable FSP UPD is for internal testing and not really available in externally released FSP source hence assigning this UPD using devicetree config dmipwroptimize doesn't do anything. TEST=Build and boot sarien/arcada. Change-Id: I6da2a088fb697e57d12008fa18bd1764b3da7765 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 7 files changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/35323/1 diff --git a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb index 3628264..7050b1e 100644 --- a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb @@ -32,7 +32,6 @@ register "psys_pmax" = "140" register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "dmipwroptimize" = "1" register "satapwroptimize" = "1" register "tdp_pl1_override" = "25" register "tdp_pl2_override" = "51" diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index e96f9d7..fac4d18 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -32,7 +32,6 @@ register "psys_pmax" = "140" register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "dmipwroptimize" = "1" register "satapwroptimize" = "1" register "tdp_pl1_override" = "25" register "tdp_pl2_override" = "51" diff --git a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb index 84aacd5..f2367ff 100644 --- a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb @@ -34,7 +34,6 @@ register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "dmipwroptimize" = "1" register "satapwroptimize" = "1" register "AcousticNoiseMitigation" = "1" register "SlowSlewRateForIa" = "2" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index ebcf140..0f3023c 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -32,7 +32,6 @@ register "psys_pmax" = "140" register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "dmipwroptimize" = "1" register "satapwroptimize" = "1" register "tdp_pl1_override" = "25" register "tdp_pl2_override" = "51" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index d3aab62..cd216e5 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -34,7 +34,6 @@ register "speed_shift_enable" = "1" register "s0ix_enable" = "1" register "dptf_enable" = "1" - register "dmipwroptimize" = "1" register "satapwroptimize" = "1" register "AcousticNoiseMitigation" = "1" register "SlowSlewRateForIa" = "2" diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 2ebe017..bfd210d 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -377,9 +377,6 @@ uint8_t SlowSlewRateForSa; uint8_t SlowSlewRateForFivr; - /* DMI Power Optimizer */ - uint8_t dmipwroptimize; - /* SATA Power Optimizer */ uint8_t satapwroptimize; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 4038335..e31e62c 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -372,7 +372,6 @@ params->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr; /* Power Optimizer */ - params->PchPwrOptEnable = config->dmipwroptimize; params->SataPwrOptEnable = config->satapwroptimize; /* Disable PCH ACPI timer */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6da2a088fb697e57d12008fa18bd1764b3da7765 Gerrit-Change-Number: 35323 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: src/{northbridge,soc}: Remove not used #include <elog.h>
by HAOUAS Elyes (Code Review) 12 Sep '19

12 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33732 Change subject: src/{northbridge,soc}: Remove not used #include <elog.h> ...................................................................... src/{northbridge,soc}: Remove not used #include <elog.h> Change-Id: I01e1e356936b85b186d9bd5f1c1e5e3a1157a30b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/haswell/early_init.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/fsp_broadwell_de/smihandler.c M src/soc/intel/skylake/romstage/romstage.c 4 files changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/33732/1 diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 6fef0da..606c9c7 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -20,7 +20,7 @@ #include <device/mmio.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <elog.h> + #include "haswell.h" static bool peg_hidden[3]; diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 4d748b2..6fb4cf6 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -24,7 +24,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> -#include <elog.h> #include <intelblocks/fast_spi.h> #include <spi-generic.h> #include <soc/iomap.h> diff --git a/src/soc/intel/fsp_broadwell_de/smihandler.c b/src/soc/intel/fsp_broadwell_de/smihandler.c index 854bd76..bb1bbf8 100644 --- a/src/soc/intel/fsp_broadwell_de/smihandler.c +++ b/src/soc/intel/fsp_broadwell_de/smihandler.c @@ -21,7 +21,6 @@ #include <device/pci_def.h> #include <cpu/x86/smm.h> #include <spi-generic.h> -#include <elog.h> #include <soc/lpc.h> #include <soc/iomap.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 29c4774..e0467bb 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -21,7 +21,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> -#include <elog.h> #include <intelblocks/fast_spi.h> #include <intelblocks/pmclib.h> #include <soc/pci_devs.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01e1e356936b85b186d9bd5f1c1e5e3a1157a30b Gerrit-Change-Number: 33732 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 4

Change in ...coreboot[master]: src/vendorcode: Remove not used #include <elog.h>
by HAOUAS Elyes (Code Review) 12 Sep '19

12 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33731 Change subject: src/vendorcode: Remove not used #include <elog.h> ...................................................................... src/vendorcode: Remove not used #include <elog.h> Change-Id: Id0b9fd9cd248c83b00bc84e9d21abc6b095ecf76 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/vendorcode/google/chromeos/gnvs.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/33731/1 diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 44162c8..8115455 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -19,7 +19,6 @@ #include <cbfs.h> #include <cbmem.h> #include <console/console.h> -#include <elog.h> #include <fmap.h> #include <security/vboot/vbnv.h> #include <security/vboot/vboot_common.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33731 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0b9fd9cd248c83b00bc84e9d21abc6b095ecf76 Gerrit-Change-Number: 33731 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: southbridge: Remove not used #include <elog.h>
by HAOUAS Elyes (Code Review) 12 Sep '19

12 Sep '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33730 Change subject: southbridge: Remove not used #include <elog.h> ...................................................................... southbridge: Remove not used #include <elog.h> Change-Id: Ifa88e3fd824ec57c21de5967e1634c8823fe0fbb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/ibexpeak/smihandler.c 4 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/33730/1 diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 374a9d9..ccfe52d 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -21,7 +21,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <elog.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/southbridge/intel/common/pmutil.c b/src/southbridge/intel/common/pmutil.c index 16ae3c6..f7f08c8 100644 --- a/src/southbridge/intel/common/pmutil.c +++ b/src/southbridge/intel/common/pmutil.c @@ -19,7 +19,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <elog.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index ba5e04b..b477a53 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -28,7 +28,6 @@ #include <arch/ioapic.h> #include <arch/acpi.h> #include <arch/cpu.h> -#include <elog.h> #include <string.h> #include <cbmem.h> #include <arch/acpigen.h> diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 208075b..ac45c15 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -21,7 +21,6 @@ #include <cpu/x86/cache.h> #include <device/pci_def.h> #include <cpu/x86/smm.h> -#include <elog.h> #include <halt.h> #include <pc80/mc146818rtc.h> #include <cpu/intel/model_2065x/model_2065x.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/33730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa88e3fd824ec57c21de5967e1634c8823fe0fbb Gerrit-Change-Number: 33730 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: nb/intel/nehalem: convert raminit_tables to header
by Angel Pons (Code Review) 12 Sep '19

12 Sep '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34876 ) Change subject: nb/intel/nehalem: convert raminit_tables to header ...................................................................... nb/intel/nehalem: convert raminit_tables to header This is necessary to get rid of a .c include. Also do some cosmetic fixes to a table, now that the line length limit has been raised. Change-Id: I6fd7fa5c9b21368bde8f089060733df6de34b4fd Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/nehalem/raminit.c R src/northbridge/intel/nehalem/raminit_tables.h 2 files changed, 24 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/34876/1 diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index fadf0e0..b9d407a 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -42,6 +42,7 @@ #include "chip.h" #include "nehalem.h" #include "raminit.h" +#include "raminit_tables.h" #define NORTHBRIDGE PCI_DEV(0, 0, 0) #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) @@ -357,8 +358,6 @@ #define RANK_SHIFT 28 #define CHANNEL_SHIFT 10 -#include "raminit_tables.c" - static void seq9(struct raminfo *info, int channel, int slot, int rank) { int i, lane; diff --git a/src/northbridge/intel/nehalem/raminit_tables.c b/src/northbridge/intel/nehalem/raminit_tables.h similarity index 98% rename from src/northbridge/intel/nehalem/raminit_tables.c rename to src/northbridge/intel/nehalem/raminit_tables.h index 5c5d46f..540cc30 100644 --- a/src/northbridge/intel/nehalem/raminit_tables.c +++ b/src/northbridge/intel/nehalem/raminit_tables.h @@ -14,6 +14,11 @@ * GNU General Public License for more details. */ +#ifndef RAMINIT_TABLES_H +#define RAMINIT_TABLES_H + +#include <types.h> + /* [CHANNEL][EXT_REVISON][LANE][2*SLOT+RANK][CLOCK_SPEED] */ const u8 u8_FFFD1240[2][5][9][4][4] = { { @@ -617,46 +622,30 @@ const u8 u8_FFFD1891[2][2][4][12] = { { { - {0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x08, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, - 0x00}, + {0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x08, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00}, }, { - {0x04, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x05, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x07, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x08, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, - 0x00}, + {0x04, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x05, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x07, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x08, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00}, } }, { { - {0x06, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x08, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x0a, 0x00, 0x00, 0x0c, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x0c, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, - 0x00}, + {0x06, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x08, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x0a, 0x00, 0x00, 0x0c, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x0c, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00}, }, { - {0x06, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x08, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x0a, 0x00, 0x00, 0x0c, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, - 0x00}, - {0x0c, 0x00, 0x00, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x74} + {0x06, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x08, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x0a, 0x00, 0x00, 0x0c, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00}, + {0x0c, 0x00, 0x00, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x74} } } }; @@ -1272,3 +1261,5 @@ }; const u8 lut16[4] = { 14, 13, 14, 14 }; + +#endif // RAMINIT_TABLES_H -- To view, visit https://review.coreboot.org/c/coreboot/+/34876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fd7fa5c9b21368bde8f089060733df6de34b4fd Gerrit-Change-Number: 34876 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mediatek/mt8183: tune EDID for BOE panel
by Peichao Li (Code Review) 12 Sep '19

12 Sep '19

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35317 ) Change subject: mediatek/mt8183: tune EDID for BOE panel ...................................................................... mediatek/mt8183: tune EDID for BOE panel BUG=b:140545315 TEST=builds Kodama image and verify display working properly Signed-off-by: Peichao Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I52a56f9bbbbef5937a9601f9371e415c74ac9a7c --- M src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/35317/1 diff --git a/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c index eba5747..dc5a2ac 100644 --- a/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c +++ b/src/mainboard/google/kukui/panel_params/panel-BOE_TV101WUM_N53.c @@ -22,11 +22,11 @@ .panel_bits_per_color = 8, .panel_bits_per_pixel = 24, .mode = { - .pixel_clock = 156297, + .pixel_clock = 159834, .lvds_dual_channel = 0, .refresh = 60, - .ha = 1200, .hbl = 164, .hso = 60, .hspw = 24, - .va = 1920, .vbl = 26, .vso = 14, .vspw = 2, + .ha = 1200, .hbl = 164, .hso = 114, .hspw = 10, + .va = 1920, .vbl = 33, .vso = 19, .vspw = 4, .phsync = '-', .pvsync = '-', .x_mm = 135, .y_mm = 216, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/35317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52a56f9bbbbef5937a9601f9371e415c74ac9a7c Gerrit-Change-Number: 35317 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/cavium: Replace use of __PRE_RAM__
by Kyösti Mälkki (Code Review) 12 Sep '19

12 Sep '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34998 ) Change subject: vendorcode/cavium: Replace use of __PRE_RAM__ ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/c/coreboot/+/34998/11/src/vendorcode/cavium/bdk… File src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c: https://review.coreboot.org/c/coreboot/+/34998/11/src/vendorcode/cavium/bdk… PS11, Line 208: > Maybe it should be spaces instead of tabs? […] Now that __PRE_RAM__ tests inside set_value() were removed, it would need malloc(). Maybe it would link without the conditional here, but this maintains the old behaviour. -- To view, visit https://review.coreboot.org/c/coreboot/+/34998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c93031c8c0e3a86261988edc956e8cd5a8dd961 Gerrit-Change-Number: 34998 Gerrit-PatchSet: 12 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 12 Sep 2019 12:32:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/cavium: Replace use of __PRE_RAM__
by Kyösti Mälkki (Code Review) 12 Sep '19

12 Sep '19

Hello Angel Pons, Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34998 to look at the new patch set (#12). Change subject: vendorcode/cavium: Replace use of __PRE_RAM__ ...................................................................... vendorcode/cavium: Replace use of __PRE_RAM__ Change-Id: I7c93031c8c0e3a86261988edc956e8cd5a8dd961 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/34998/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/34998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c93031c8c0e3a86261988edc956e8cd5a8dd961 Gerrit-Change-Number: 34998 Gerrit-PatchSet: 12 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: src/soc/intel/(apollolake,cnl): Modify code to point common function
by Sridhar Siricilla (Code Review) 12 Sep '19

12 Sep '19

Hello Rizwan Qureshi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35231 to review the following change. Change subject: src/soc/intel/(apollolake,cnl): Modify code to point common function ...................................................................... src/soc/intel/(apollolake,cnl): Modify code to point common function Removed function print_me_version from cnl/skl, and dump_me_version(apollolake), and made changes to call print_me_firmware_version() which is defined in the cse lib. Change-Id: I46431426e88b086b326197ba1f9487da1e12074b Signed-off-by: sridhar <sridhar.siricilla(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/apollolake/cse.c M src/soc/intel/cannonlake/me.c M src/soc/intel/skylake/include/soc/me.h M src/soc/intel/skylake/me.c 4 files changed, 3 insertions(+), 221 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/35231/1 diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index 32e9222..386662e 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -36,8 +36,6 @@ #define READ_FILE_FLAG_EMULATED (1 << 2) #define READ_FILE_FLAG_HW (1 << 3) -#define MKHI_GROUP_ID_GEN 0xff -#define GET_FW_VERSION 0x02 #define MCA_MAX_FILE_PATH_SIZE 64 @@ -182,63 +180,6 @@ printk(BIOS_CRIT, "failed to save FPF state\n"); } -static void dump_cse_version(void *unused) -{ - int res; - size_t reply_size; - - struct fw_version_cmd { - union mkhi_header mkhi_hdr; - } __packed msg; - - struct version { - uint16_t minor; - uint16_t major; - uint16_t build; - uint16_t hotfix; - } __packed; - - struct fw_version_response { - union mkhi_header mkhi_hdr; - struct version code; - struct version nftp; - struct version fitc; - } __packed rsp; - - /* - * Print ME version only if UART debugging is enabled. Else, it takes - * ~0.6 second to talk to ME and get this information. - */ - if (!CONFIG(CONSOLE_SERIAL)) - return; - - msg.mkhi_hdr.fields.group_id = MKHI_GROUP_ID_GEN; - msg.mkhi_hdr.fields.command = GET_FW_VERSION; - - res = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); - - if (!res) { - printk(BIOS_ERR, "Failed to send HECI message.\n"); - return; - } - - reply_size = sizeof(rsp); - res = heci_receive(&rsp, &reply_size); - - if (!res) { - printk(BIOS_ERR, "Failed to receive HECI reply.\n"); - return; - } - - if (rsp.mkhi_hdr.fields.result != 0) { - printk(BIOS_ERR, "Failed to get ME version.\n"); - return; - } - - printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", rsp.code.major, - rsp.code.minor, rsp.code.hotfix, rsp.code.build); -} - static void dump_cse_state(void) { uint32_t fwsts1; @@ -292,4 +233,4 @@ } BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, fpf_blown, NULL); -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, dump_cse_version, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, print_me_firmware_version, NULL); diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index dab909b..931f4cd 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -24,13 +24,6 @@ #include <stdint.h> #include <stdlib.h> -/* Miscellaneous constants */ -enum { - MKHI_GEN_GROUP_ID = 0xFF, - MKHI_GET_FW_VERSION = 0x02, - ME_OPMODE_NORMAL = 0x00, - ME_WSTATE_NORMAL = 0x05, -}; /* Host Firmware Status Register 1 */ union hfsts1 { @@ -145,80 +138,7 @@ } __packed fields; }; -/* - * From reading the documentation, this should work for both WHL and CML - * platforms. Also, calling this function from dump_me_status() does not - * work, as the ME does not respond and the command times out. - */ -static void print_me_version(void *unused) -{ - struct mkhi_hdr { - uint8_t group_id; - uint8_t command :7; - uint8_t is_resp :1; - uint8_t rsvd; - uint8_t result; - } __packed; - - struct version { - uint16_t minor; - uint16_t major; - uint16_t build; - uint16_t hotfix; - } __packed; - - struct fw_ver_resp { - struct mkhi_hdr hdr; - struct version code; - struct version rec; - struct version fitc; - } __packed; - - union hfsts1 hfsts1; - const struct mkhi_hdr fw_ver_msg = { - .group_id = MKHI_GEN_GROUP_ID, - .command = MKHI_GET_FW_VERSION, - }; - struct fw_ver_resp resp; - size_t resp_size = sizeof(resp); - - /* Ignore if UART debugging is disabled */ - if (!CONFIG(CONSOLE_SERIAL)) - return; - - hfsts1.raw = me_read_config32(PCI_ME_HFSTS1); - - /* - * Prerequisites: - * 1) HFSTS1 Current Working State is Normal - * 2) HFSTS1 Current Operation Mode is Normal - * 3) It's after DRAM INIT DONE message (taken care of by calling it - * during ramstage - */ - if ((hfsts1.fields.working_state != ME_WSTATE_NORMAL) || - (hfsts1.fields.operation_mode != ME_OPMODE_NORMAL)) - goto fail; - - heci_reset(); - - if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADDR, - HECI_MKHI_ADDR)) - goto fail; - - if (!heci_receive(&resp, &resp_size)) - goto fail; - - if (resp.hdr.result) - goto fail; - - printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major, - resp.code.minor, resp.code.hotfix, resp.code.build); - return; - -fail: - printk(BIOS_DEBUG, "ME: Version: Unavailable\n"); -} -BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_version, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_firmware_version, NULL); void dump_me_status(void *unused) { diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index bec54d8..3c0da58 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -195,12 +195,6 @@ } __packed fields; }; -#define MKHI_GEN_GROUP_ID 0xff - -#define MKHI_GET_FW_VERSION 0x02 - -#define BIOS_HOST_ADD 0x00 -#define HECI_MKHI_ADD 0x07 void intel_me_status(void); int send_global_reset(void); diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index fde4b13..57ea95f 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -198,84 +198,11 @@ "M0 kernel load", }; -static void print_me_version(void *unused) -{ - struct mkhi_hdr { - uint8_t group_id; - uint8_t command:7; - uint8_t is_resp:1; - uint8_t rsvd; - uint8_t result; - } __packed; - - struct version { - uint16_t minor; - uint16_t major; - uint16_t build; - uint16_t hotfix; - } __packed; - - struct fw_ver_resp { - struct mkhi_hdr hdr; - struct version code; - struct version rec; - struct version fitc; - } __packed; - - const struct mkhi_hdr fw_ver_msg = { - .group_id = MKHI_GEN_GROUP_ID, - .command = MKHI_GET_FW_VERSION, - }; - - struct fw_ver_resp resp; - size_t resp_size = sizeof(resp); - union me_hfs hfs; - - /* - * Print ME version only if UART debugging is enabled. Else, it takes ~1 - * second to talk to ME and get this information. - */ - if (!CONFIG(CONSOLE_SERIAL)) - return; - - hfs.data = me_read_config32(PCI_ME_HFSTS1); - /* - * This command can be run only if: - * - Working state is normal and - * - Operation mode is normal. - */ - if ((hfs.fields.working_state != ME_HFS_CWS_NORMAL) || - (hfs.fields.operation_mode != ME_HFS_MODE_NORMAL)) - goto failed; - - /* - * It is important to do a heci_reset to ensure BIOS and ME are in sync - * before reading firmware version. - */ - heci_reset(); - - if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADD, - HECI_MKHI_ADD)) - goto failed; - - if (!heci_receive(&resp, &resp_size)) - goto failed; - - if (resp.hdr.result) - goto failed; - - printk(BIOS_DEBUG, "ME: Version : %d.%d.%d.%d\n", resp.code.major, - resp.code.minor, resp.code.hotfix, resp.code.build); - return; - -failed: - printk(BIOS_DEBUG, "ME: Version : Unavailable\n"); -} /* * This can't be put in intel_me_status because by the time control * reaches there, ME doesn't respond to GET_FW_VERSION command. */ -BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_version, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_firmware_version, NULL); void intel_me_status(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/35231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46431426e88b086b326197ba1f9487da1e12074b Gerrit-Change-Number: 35231 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: src/soc/intel/common/block/cse: Add print_me_fw_version() to cse lib.
by Sridhar Siricilla (Code Review) 12 Sep '19

12 Sep '19

Hello Rizwan Qureshi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35230 to review the following change. Change subject: src/soc/intel/common/block/cse: Add print_me_fw_version() to cse lib. ...................................................................... src/soc/intel/common/block/cse: Add print_me_fw_version() to cse lib. print_me_fw_version() - queries and logs ME's FW version. Change-Id: I68a0338ed655c13a478e5dbcc58fc6a8844a5270 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: sridhar <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 73 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/35230/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index d85209b..2845759 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -85,6 +85,9 @@ #define ME_HFS_CWS_NORMAL 5 #define ME_HFS_MODE_NORMAL 0 +#define MKHI_GEN_GROUP_ID 0xff +#define MKHI_GET_FW_VERSION 0x02 + static struct cse_device { uintptr_t sec_bar; } g_cse; @@ -122,7 +125,6 @@ uint8_t result; }__packed; - /* * Initialize the device with provided temporary BAR. If BAR is 0 use a * default. This is intended for pre-mem usage only where BARs haven't been @@ -774,6 +776,72 @@ return -1; } +/* + * From reading the documentation, this should work for both WHL and CML + * platforms. Also, calling this function from dump_me_status() does not + * work, as the ME does not respond and the command times out. + */ +void print_me_firmware_version(void *unused) +{ + struct version { + uint16_t minor; + uint16_t major; + uint16_t build; + uint16_t hotfix; + } __packed; + + struct fw_ver_resp { + struct mkhi_hdr hdr; + struct version code; + struct version rec; + struct version fitc; + } __packed; + + union me_hfs hfsts1; + const struct mkhi_hdr fw_ver_msg = { + .group_id = MKHI_GEN_GROUP_ID, + .command = MKHI_GET_FW_VERSION, + }; + struct fw_ver_resp resp; + size_t resp_size = sizeof(resp); + + /* Ignore if UART debugging is disabled */ + if (!CONFIG(CONSOLE_SERIAL)) + return; + + hfsts1.data = me_read_config32(PCI_ME_HFSTS1); + + /* + * Prerequisites: + * 1) HFSTS1 Current Working State is Normal + * 2) HFSTS1 Current Operation Mode is Normal + * 3) It's after DRAM INIT DONE message (taken care of by calling it + * during ramstage + */ + if ((hfsts1.fields.working_state != ME_HFS_CWS_NORMAL) || + (hfsts1.fields.operation_mode != ME_HFS_MODE_NORMAL)) + goto fail; + + heci_reset(); + + if (!heci_send(&fw_ver_msg, sizeof(fw_ver_msg), BIOS_HOST_ADDR, + HECI_MKHI_ADDR)) + goto fail; + + if (!heci_receive(&resp, &resp_size)) + goto fail; + + if (resp.hdr.result) + goto fail; + + printk(BIOS_DEBUG, "ME: Version: %d.%d.%d.%d\n", resp.code.major, + resp.code.minor, resp.code.hotfix, resp.code.build); + return; + +fail: + printk(BIOS_DEBUG, "ME: Version: Unavailable\n"); +} + #if ENV_RAMSTAGE static void update_sec_bar(struct device *dev) diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index c0a5fef..f5c2b9e 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -89,6 +89,10 @@ */ int send_hmrfpo_get_status_msg(void); +/* + * Queries and logs ME firmware version + */ +void print_me_firmware_version(void *unused); #define BIOS_HOST_ADDR 0x00 #define HECI_MKHI_ADDR 0x07 -- To view, visit https://review.coreboot.org/c/coreboot/+/35230 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68a0338ed655c13a478e5dbcc58fc6a8844a5270 Gerrit-Change-Number: 35230 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newchange

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