coreboot-gerrit September 2019

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Change in coreboot[master]: vendorcode/cavium: Replace use of __PRE_RAM__
by Angel Pons (Code Review) 12 Sep '19

12 Sep '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34998 ) Change subject: vendorcode/cavium: Replace use of __PRE_RAM__ ...................................................................... Patch Set 11: Code-Review+2 (1 comment) Other than the comment, LGTM https://review.coreboot.org/c/coreboot/+/34998/11/src/vendorcode/cavium/bdk… File src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c: https://review.coreboot.org/c/coreboot/+/34998/11/src/vendorcode/cavium/bdk… PS11, Line 208: Maybe it should be spaces instead of tabs? Also, what is this check added for? -- To view, visit https://review.coreboot.org/c/coreboot/+/34998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c93031c8c0e3a86261988edc956e8cd5a8dd961 Gerrit-Change-Number: 34998 Gerrit-PatchSet: 11 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 12 Sep 2019 10:42:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: timestamps: Mostly remove struct timestamp_cache
by Kyösti Mälkki (Code Review) 12 Sep '19

12 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35290 ) Change subject: timestamps: Mostly remove struct timestamp_cache ...................................................................... timestamps: Mostly remove struct timestamp_cache Change-Id: Ifcd75630e562af302312f93bdf180aa90f18d21d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/lib/timestamp.c 1 file changed, 13 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/35290/1 diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 4983885..db73f15 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -58,25 +58,25 @@ as CBMEM comes available. */ static struct timestamp_table *glob_ts_table CAR_GLOBAL; -static void timestamp_cache_init(struct timestamp_cache *ts_cache, +static void timestamp_cache_init(struct timestamp_table *ts_cache, uint64_t base) { - ts_cache->table.num_entries = 0; - ts_cache->table.max_entries = MAX_BSS_TIMESTAMP_CACHE; - ts_cache->table.base_time = base; + ts_cache->num_entries = 0; + ts_cache->max_entries = MAX_BSS_TIMESTAMP_CACHE; + ts_cache->base_time = base; if (USE_TIMESTAMP_REGION) - ts_cache->table.max_entries = (REGION_SIZE(timestamp) - - offsetof(struct timestamp_cache, entries)) + ts_cache->max_entries = (REGION_SIZE(timestamp) - + offsetof(struct timestamp_table, entries)) / sizeof(struct timestamp_entry); } -static struct timestamp_cache *timestamp_cache_get(void) +static struct timestamp_table *timestamp_cache_get(void) { - struct timestamp_cache *ts_cache = NULL; + struct timestamp_table *ts_cache = NULL; if (TIMESTAMP_CACHE_IN_BSS) { - ts_cache = &timestamp_cache; + ts_cache = &timestamp_cache.table; } else if (USE_TIMESTAMP_REGION) { if (REGION_SIZE(timestamp) < sizeof(*ts_cache)) BUG(); @@ -122,17 +122,14 @@ static struct timestamp_table *timestamp_table_get(void) { struct timestamp_table *ts_table; - struct timestamp_cache *ts_cache; ts_table = car_get_ptr(glob_ts_table); if (ts_table) return ts_table; - ts_cache = timestamp_cache_get(); - if (ts_cache) - ts_table = &ts_cache->table; - + ts_table = timestamp_cache_get(); car_set_ptr(glob_ts_table, ts_table); + return ts_table; } @@ -196,7 +193,7 @@ void timestamp_init(uint64_t base) { - struct timestamp_cache *ts_cache; + struct timestamp_table *ts_cache; assert(ENV_ROMSTAGE_OR_BEFORE); @@ -211,7 +208,7 @@ } timestamp_cache_init(ts_cache, base); - timestamp_table_set(&ts_cache->table); + timestamp_table_set(ts_cache); } static void timestamp_sync_cache_to_cbmem(struct timestamp_table *ts_cbmem_table) -- To view, visit https://review.coreboot.org/c/coreboot/+/35290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifcd75630e562af302312f93bdf180aa90f18d21d Gerrit-Change-Number: 35290 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: timestamps: Refactor CBMEM hook
by Kyösti Mälkki (Code Review) 12 Sep '19

12 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35280 ) Change subject: timestamps: Refactor CBMEM hook ...................................................................... timestamps: Refactor CBMEM hook Separate timestamp_sync_cache_to_cbmem() as it is only used with ENV_ROMSTAGE. Change-Id: Ibe18a5ecf09b2b87d8ee3e828728ad6a8a262206 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/lib/timestamp.c 1 file changed, 44 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/35280/1 diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index 92bd094..3d8999c 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -200,46 +200,14 @@ timestamp_table_set(&ts_cache->table); } -static void timestamp_sync_cache_to_cbmem(int is_recovery) +static void timestamp_sync_cache_to_cbmem(struct timestamp_table *ts_cbmem_table) { uint32_t i; struct timestamp_table *ts_cache_table; - struct timestamp_table *ts_cbmem_table; - - if (!timestamp_should_run()) - return; - - /* cbmem is being recovered. */ - if (is_recovery) { - /* x86 resume path expects timestamps to be reset. */ - if (CONFIG(ARCH_ROMSTAGE_X86_32) && ENV_ROMSTAGE) - ts_cbmem_table = timestamp_alloc_cbmem_table(); - else { - /* Find existing table in cbmem. */ - ts_cbmem_table = cbmem_find(CBMEM_ID_TIMESTAMP); - /* No existing timestamp table. */ - if (ts_cbmem_table == NULL) - ts_cbmem_table = timestamp_alloc_cbmem_table(); - } - } else - /* First time sync. Add new table. */ - ts_cbmem_table = timestamp_alloc_cbmem_table(); - - if (ts_cbmem_table == NULL) { - printk(BIOS_ERR, "ERROR: No timestamp table allocated\n"); - timestamp_table_set(NULL); - return; - } - - /* Seed the timestamp tick frequency in ENV_PAYLOAD_LOADER. */ - if (ENV_PAYLOAD_LOADER) - ts_cbmem_table->tick_freq_mhz = timestamp_tick_freq_mhz(); ts_cache_table = timestamp_table_get(); if (!ts_cache_table) { - if (ENV_ROMSTAGE) - printk(BIOS_ERR, "ERROR: No timestamp cache found\n"); - timestamp_table_set(ts_cbmem_table); + printk(BIOS_ERR, "ERROR: No timestamp cache found\n"); return; } @@ -276,10 +244,48 @@ ts_cbmem_table->base_time = ts_cache_table->base_time; /* Cache no longer required. */ - timestamp_table_set(ts_cbmem_table); ts_cache_table->num_entries = 0; } +static void timestamp_reinit(int is_recovery) +{ + struct timestamp_table *ts_cbmem_table; + + if (!timestamp_should_run()) + return; + + /* cbmem is being recovered. */ + if (is_recovery) { + /* x86 resume path expects timestamps to be reset. */ + if (CONFIG(ARCH_ROMSTAGE_X86_32) && ENV_ROMSTAGE) + ts_cbmem_table = timestamp_alloc_cbmem_table(); + else { + /* Find existing table in cbmem. */ + ts_cbmem_table = cbmem_find(CBMEM_ID_TIMESTAMP); + /* No existing timestamp table. */ + if (ts_cbmem_table == NULL) + ts_cbmem_table = timestamp_alloc_cbmem_table(); + } + } else + /* First time sync. Add new table. */ + ts_cbmem_table = timestamp_alloc_cbmem_table(); + + if (ts_cbmem_table == NULL) { + printk(BIOS_ERR, "ERROR: No timestamp table allocated\n"); + timestamp_table_set(NULL); + return; + } + + if (ENV_ROMSTAGE) + timestamp_sync_cache_to_cbmem(ts_cbmem_table); + + /* Seed the timestamp tick frequency in ENV_PAYLOAD_LOADER. */ + if (ENV_PAYLOAD_LOADER) + ts_cbmem_table->tick_freq_mhz = timestamp_tick_freq_mhz(); + + timestamp_table_set(ts_cbmem_table); +} + void timestamp_rescale_table(uint16_t N, uint16_t M) { uint32_t i; @@ -321,9 +327,9 @@ return (timestamp_get() - ts->base_time) / ts->tick_freq_mhz; } -ROMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem) -POSTCAR_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem) -RAMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem) +ROMSTAGE_CBMEM_INIT_HOOK(timestamp_reinit) +POSTCAR_CBMEM_INIT_HOOK(timestamp_reinit) +RAMSTAGE_CBMEM_INIT_HOOK(timestamp_reinit) /* Provide default timestamp implementation using monotonic timer. */ uint64_t __weak timestamp_get(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/35280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe18a5ecf09b2b87d8ee3e828728ad6a8a262206 Gerrit-Change-Number: 35280 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sifive: Update devicetree
by Patrick Rudolph (Code Review) 12 Sep '19

12 Sep '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35122 ) Change subject: sifive: Update devicetree ...................................................................... sifive: Update devicetree With the current devicetree the kernel doesn't provide any serial after serial init. Update the devicetree to resolve this issue. Tested on HiFive Unleashed. Change-Id: I4427d34a12902e0eaa2186121a53152b719cadff Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/sifive/hifive-unleashed/Makefile.inc A src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi A src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts D src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts 4 files changed, 343 insertions(+), 641 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/35122/1 diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc index 8ce266f..88ea145 100644 --- a/src/mainboard/sifive/hifive-unleashed/Makefile.inc +++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc @@ -24,7 +24,7 @@ DTB=$(obj)/hifive-unleashed.dtb -DTS=src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts +DTS=src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts $(DTB): $(DTS) dtc -I dts -O dtb -o $(DTB) $(DTS) diff --git a/src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi b/src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi new file mode 100644 index 0000000..3dc27c3 --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi @@ -0,0 +1,245 @@ +/* + * This file is part of the Linux kernel. + * + * Copyright (c) 2018-2019 SiFive, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + cpu0: cpu@0 { + compatible = "sifive,e51", "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "disabled"; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; + ranges; + plic0: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev = <53>; + interrupt-controller; + interrupts-extended = < + &cpu0_intc 0xffffffff + &cpu1_intc 0xffffffff &cpu1_intc 9 + &cpu2_intc 0xffffffff &cpu2_intc 9 + &cpu3_intc 0xffffffff &cpu3_intc 9 + &cpu4_intc 0xffffffff &cpu4_intc 9>; + }; + prci: clock-controller@10000000 { + compatible = "sifive,fu540-c000-prci"; + reg = <0x0 0x10000000 0x0 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + }; + uart0: serial@10010000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10010000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <4>; + clocks = <&prci 3>; + status = "disabled"; + }; + uart1: serial@10011000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10011000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <5>; + clocks = <&prci 3>; + status = "disabled"; + }; + i2c0: i2c@10030000 { + compatible = "sifive,fu540-c000-i2c", "sifive,i2c0"; + reg = <0x0 0x10030000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <50>; + clocks = <&prci 3>; + reg-shift = <2>; + reg-io-width = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi0: spi@10040000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10040000 0x0 0x1000 + 0x0 0x20000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <51>; + clocks = <&prci 3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi1: spi@10041000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10041000 0x0 0x1000 + 0x0 0x30000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <52>; + clocks = <&prci 3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi2: spi@10050000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10050000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <6>; + clocks = <&prci 3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + eth0: ethernet@10090000 { + compatible = "sifive,fu540-c000-gem"; + interrupt-parent = <&plic0>; + interrupts = <53>; + reg = <0x0 0x10090000 0x0 0x2000 + 0x0 0x100a0000 0x0 0x1000>; + local-mac-address = [00 00 00 00 00 00]; + clock-names = "pclk", "hclk"; + clocks = <&prci 2>, <&prci 2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + }; +}; diff --git a/src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts b/src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts new file mode 100644 index 0000000..454c3d8 --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts @@ -0,0 +1,97 @@ +/* + * This file is part of the Linux kernel. + * + * Copyright (c) 2018-2019 SiFive, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "fu540-c000.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "SiFive HiFive Unleashed A00"; + compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; + + chosen { + }; + + cpus { + /* Clock frequency (in Hz) of the PCB crystal for rtcclk */ + timebase-frequency = <1000000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; + + soc { + }; + + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1000000>; + clock-output-names = "rtcclk"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&qspi0 { + status = "okay"; + flash@0 { + compatible = "issi,is25wp256", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&qspi2 { + status = "okay"; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; +}; + +&eth0 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; diff --git a/src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts b/src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts deleted file mode 100644 index 6b9bbaa..0000000 --- a/src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts +++ /dev/null @@ -1,640 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 SiFive, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -/dts-v1/; - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "sifive,fu540g", "sifive,fu500"; - model = "sifive,hifive-unleashed-a00"; - - aliases { - serial0 = &L28; - serial1 = &L29; - }; - - chosen { - }; -/* - firmware { - sifive,fsbl = "YYYY-MM-DD"; - }; -*/ - L3: cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <1000000>; - L9: cpu@0 { - clock-frequency = <0>; - compatible = "sifive,rocket0", "riscv"; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <16384>; - next-level-cache = <&L24 &L0>; - reg = <0>; - riscv,isa = "rv64imac"; - sifive,dtim = <&L8>; - sifive,itim = <&L7>; - status = "okay"; - L10: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - L12: cpu@1 { - clock-frequency = <0>; - compatible = "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - next-level-cache = <&L24 &L0>; - reg = <1>; - riscv,isa = "rv64imafdc"; - sifive,itim = <&L11>; - status = "okay"; - tlb-split; - L13: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - L15: cpu@2 { - clock-frequency = <0>; - compatible = "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - next-level-cache = <&L24 &L0>; - reg = <2>; - riscv,isa = "rv64imafdc"; - sifive,itim = <&L14>; - status = "okay"; - tlb-split; - L16: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - L18: cpu@3 { - clock-frequency = <0>; - compatible = "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - next-level-cache = <&L24 &L0>; - reg = <3>; - riscv,isa = "rv64imafdc"; - sifive,itim = <&L17>; - status = "okay"; - tlb-split; - L19: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - L21: cpu@4 { - clock-frequency = <0>; - compatible = "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - next-level-cache = <&L24 &L0>; - reg = <4>; - riscv,isa = "rv64imafdc"; - sifive,itim = <&L20>; - status = "okay"; - tlb-split; - L22: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - }; - L36: memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x2 0x00000000>; - }; - L2: soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus"; - ranges; - refclk: refclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <33333333>; - clock-output-names = "xtal"; - }; - prci: prci@10000000 { - /* compatible = "sifive,ux00prci0"; */ - compatible = "sifive,aloeprci0"; - reg = <0x0 0x10000000 0x0 0x1000>; - reg-names = "control"; - clocks = <&refclk>; - #clock-cells = <1>; - }; - tlclk: tlclk { - compatible = "fixed-factor-clock"; - clocks = <&prci 0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - L51: cadence-gemgxl-mgmt@100a0000 { - compatible = "sifive,cadencegemgxlmgmt0"; - reg = <0x0 0x100a0000 0x0 0x1000>; - reg-names = "control"; - #clock-cells = <0>; - }; - L35: bus-blocker@100b8000 { - compatible = "sifive,bus-blocker0"; - reg = <0x0 0x100b8000 0x0 0x1000>; - reg-names = "control"; - }; - L0: cache-controller@2010000 { - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <2048>; - cache-size = <2097152>; - cache-unified; - compatible = "sifive,ccache0", "cache"; - interrupt-parent = <&L4>; - interrupts = <1 2 3>; - next-level-cache = <&L25 &L40 &L36>; - reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>; - reg-names = "control", "sideband"; - }; - L33: cadence-ddr-mgmt@100c0000 { - compatible = "sifive,cadenceddrmgmt0"; - reg = <0x0 0x100c0000 0x0 0x1000>; - reg-names = "control"; - }; - L40: chiplink@40000000 { - #address-cells = <2>; - #size-cells = <2>; - compatible = "sifive,chiplink", "simple-bus"; - ranges = <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000 0x30 0x0 0x30 0x0 0x10 0x0 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000 0x20 0x0 0x20 0x0 0x10 0x0>; - }; - L5: clint@2000000 { - compatible = "riscv,clint0"; - interrupts-extended = <&L10 3 &L10 7 &L13 3 &L13 7 &L16 3 &L16 7 &L19 3 &L19 7 &L22 3 &L22 7>; - reg = <0x0 0x2000000 0x0 0x10000>; - reg-names = "control"; - }; - L6: debug-controller@0 { - compatible = "sifive,debug-013", "riscv,debug-013"; - interrupts-extended = <&L10 65535 &L13 65535 &L16 65535 &L19 65535 &L22 65535>; - reg = <0x0 0x0 0x0 0x1000>; - reg-names = "control"; - }; - L32: dma@3000000 { - #dma-cells = <1>; - compatible = "riscv,dma0"; - dma-channels = <4>; - dma-requests = <0>; - interrupt-parent = <&L4>; - interrupts = <23 24 25 26 27 28 29 30>; - reg = <0x0 0x3000000 0x0 0x100000>; - reg-names = "control"; - riscv,dma-pools = <1>; - }; - L8: dtim@1000000 { - compatible = "sifive,dtim0"; - reg = <0x0 0x1000000 0x0 0x2000>; - reg-names = "mem"; - }; - L44: ememoryotp@10070000 { - compatible = "sifive,ememoryotp0"; - reg = <0x0 0x10070000 0x0 0x1000>; - reg-names = "control"; - }; - L24: error-device@18000000 { - compatible = "sifive,error0"; - reg = <0x0 0x18000000 0x0 0x8000000>; - reg-names = "mem"; - }; - L52: ethernet@10090000 { - compatible = "cdns,macb"; - interrupt-parent = <&L4>; - interrupts = <53>; - reg = <0x0 0x10090000 0x0 0x2000>; - reg-names = "control"; - - local-mac-address = [00 00 00 00 00 00]; - phy-mode = "gmii"; - clock-names = "pclk", "hclk", "tx_clk"; - clocks = <&prci 1>, <&prci 1>, <&L51>; - - #address-cells = <1>; - #size-cells = <0>; - phy1: ethernet-phy@0 { - reg = <0>; - reset-gpios = <&L31 12 1>; - }; - }; - L31: gpio@10060000 { - compatible = "sifive,gpio0"; - interrupt-parent = <&L4>; - interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>; - reg = <0x0 0x10060000 0x0 0x1000>; - reg-names = "control"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - gpio-restart { - compatible = "gpio-restart"; - gpios = <&L31 10 1>; - }; - L47: i2c@10030000 { - compatible = "sifive,i2c0", "opencores,i2c-ocores"; - reg = <0x0 0x10030000 0x0 0x1000>; - reg-names = "control"; - clocks = <&tlclk>; - - reg-shift = <2>; - reg-io-width = <1>; - - #address-cells = <1>; - #size-cells = <0>; - - /* On pre-production boards only */ -/* - ina233-vdd_soc_core@40 { - compatible = "ti,pmbus"; - reg = <0x40>; - }; - ina233-vdd_ddr_soc@44 { - compatible = "ti,pmbus"; - reg = <0x44>; - }; - ina233-vdd_ddr_mem@45 { - compatible = "ti,pmbus"; - reg = <0x45>; - }; - ina233-vdd_corepll@47 { - compatible = "ti,pmbus"; - reg = <0x47>; - }; - ina233-vdd_otp@4a { - compatible = "ti,pmbus"; - reg = <0x4a>; - }; - ina233-vdd_io@4b { - compatible = "ti,pmbus"; - reg = <0x4b>; - }; - ina233-vdd_ddrpll@48 { - compatible = "ti,pmbus"; - reg = <0x48>; - }; - ina233-avdd_ddrpll@49 { - compatible = "ti,pmbus"; - reg = <0x49>; - }; - ina233-vdd_givdd@4c { - compatible = "ti,pmbus"; - reg = <0x4c>; - }; - ina233vdd_gemgxlpll@4d { - compatible = "ti,pmbus"; - reg = <0x4d>; - }; -*/ - /* On the tester board */ -/* - m24c02 { - compatible = "st,24c02"; - reg = <0x51>; - }; -*/ - }; - L4: interrupt-controller@c000000 { - #interrupt-cells = <1>; - compatible = "riscv,plic0"; - interrupt-controller; - interrupts-extended = <&L10 11 &L13 11 &L13 9 &L16 11 &L16 9 &L19 11 &L19 9 &L22 11 &L22 9>; - reg = <0x0 0xc000000 0x0 0x4000000>; - reg-names = "control"; - riscv,max-priority = <7>; - riscv,ndev = <53>; - }; - L7: itim@1800000 { - compatible = "sifive,itim0"; - reg = <0x0 0x1800000 0x0 0x4000>; - reg-names = "mem"; - }; - L11: itim@1808000 { - compatible = "sifive,itim0"; - reg = <0x0 0x1808000 0x0 0x8000>; - reg-names = "mem"; - }; - L14: itim@1810000 { - compatible = "sifive,itim0"; - reg = <0x0 0x1810000 0x0 0x8000>; - reg-names = "mem"; - }; - L17: itim@1818000 { - compatible = "sifive,itim0"; - reg = <0x0 0x1818000 0x0 0x8000>; - reg-names = "mem"; - }; - L20: itim@1820000 { - compatible = "sifive,itim0"; - reg = <0x0 0x1820000 0x0 0x8000>; - reg-names = "mem"; - }; - L37: memory-controller@100b0000 { - /* compatible = "sifive,ux00ddr0"; */ - compatible = "sifive,aloeddr0"; - interrupt-parent = <&L4>; - interrupts = <31>; - reg = <0x0 0x100b0000 0x0 0x4000>; - reg-names = "control"; - }; - pci@2000000000 { - #address-cells = <3>; - #interrupt-cells = <1>; - #size-cells = <2>; - compatible = "xlnx,axi-pcie-host-1.00.a"; - device_type = "pci"; - interrupt-map = <0 0 0 1 &xil_pcie_intc 1 0 0 0 2 &xil_pcie_intc 2 0 0 0 3 &xil_pcie_intc 3 0 0 0 4 &xil_pcie_intc 4>; - interrupt-map-mask = <0 0 0 7>; - interrupt-parent = <&L4>; - interrupts = <32>; - ranges = <0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>; - reg = <0x020 0x0 0x0 0x4000000>; - reg-names = "control"; - xil_pcie_intc: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; -/* - pci@2030000000 { - #address-cells = <3>; - #interrupt-cells = <1>; - #size-cells = <2>; - compatible = "ms-pf,axi-pcie-host"; - device_type = "pci"; - bus-range = <0x01 0x7f>; - interrupt-map = <0 0 0 1 &ms_pcie_intc 1 0 0 0 2 &ms_pcie_intc 2 0 0 0 3 &ms_pcie_intc 3 0 0 0 4 &ms_pcie_intc 4>; - interrupt-map-mask = <0 0 0 7>; - interrupt-parent = <&L4>; - interrupts = <32>; - ranges = <0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>; - reg = <0x20 0x30000000 0x0 0x4000000 0x20 0x0 0x0 0x100000>; - reg-names = "control", "apb"; - ms_pcie_intc: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; -*/ - L53: pinctrl@10080000 { - compatible = "sifive,pinctrl0"; - reg = <0x0 0x10080000 0x0 0x1000>; - reg-names = "control"; - }; - L45: pwm@10020000 { - compatible = "sifive,pwm0"; - interrupt-parent = <&L4>; - interrupts = <42 43 44 45>; - reg = <0x0 0x10020000 0x0 0x1000>; - reg-names = "control"; - clocks = <&tlclk>; - sifive,approx-period = <1000000>; - #pwm-cells = <2>; - }; - L46: pwm@10021000 { - compatible = "sifive,pwm0"; - interrupt-parent = <&L4>; - interrupts = <46 47 48 49>; - reg = <0x0 0x10021000 0x0 0x1000>; - reg-names = "control"; - clocks = <&tlclk>; - sifive,approx-period = <1000000>; - #pwm-cells = <2>; - }; - pwmleds { - compatible = "pwm-leds"; - heartbeat { - pwms = <&L45 0 0>; - max-brightness = <255>; - linux,default-trigger = "heartbeat"; - }; - mtd { - pwms = <&L45 1 0>; - max-brightness = <255>; - linux,default-trigger = "mtd"; - }; - netdev { - pwms = <&L45 2 0>; - max-brightness = <255>; - linux,default-trigger = "netdev"; - }; - panic { - pwms = <&L45 3 0>; - max-brightness = <255>; - linux,default-trigger = "panic"; - }; - /* These LEDs are on the tester board */ -/* - testled { - pwms = <&L46 0 0>; - max-brightness = <255>; - }; - green { - pwms = <&L46 1 0>; - max-brightness = <255>; - }; - red { - pwms = <&L46 2 0>; - max-brightness = <255>; - }; - blue { - pwms = <&L46 3 0>; - max-brightness = <255>; - }; -*/ - }; - L27: rom@1000 { - compatible = "sifive,modeselect0"; - reg = <0x0 0x1000 0x0 0x1000>; - reg-names = "mem"; - }; - L26: rom@10000 { - compatible = "sifive,maskrom0"; - reg = <0x0 0x10000 0x0 0x8000>; - reg-names = "mem"; - }; - L25: rom@a000000 { - compatible = "ucbbar,cacheable-zero0"; - reg = <0x0 0xa000000 0x0 0x2000000>; - reg-names = "mem"; - }; - L28: serial@10010000 { - compatible = "sifive,uart0"; - interrupt-parent = <&L4>; - interrupts = <4>; - reg = <0x0 0x10010000 0x0 0x1000>; - reg-names = "control"; - clocks = <&tlclk>; - }; - L29: serial@10011000 { - compatible = "sifive,uart0"; - interrupt-parent = <&L4>; - interrupts = <5>; - reg = <0x0 0x10011000 0x0 0x1000>; - reg-names = "control"; - clocks = <&tlclk>; - }; - L49: spi@10040000 { - compatible = "sifive,spi0"; - interrupt-parent = <&L4>; - interrupts = <51>; - reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>; - reg-names = "control", "mem"; - clocks = <&tlclk>; - - #address-cells = <1>; - #size-cells = <0>; - flash@0 { - compatible = "issi,is25wp256d", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; - }; - L50: spi@10041000 { - compatible = "sifive,spi0"; - interrupt-parent = <&L4>; - interrupts = <52>; - reg = <0x0 0x10041000 0x0 0x1000 0x0 0x30000000 0x0 0x10000000>; - reg-names = "control", "mem"; - clocks = <&tlclk>; - - #address-cells = <1>; - #size-cells = <0>; - - /* These flash chips are on the tester board */ -/* - flash@0 { - compatible = "issi,is25wp032", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <25000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; - flash@1 { - compatible = "issi,is25wp032", "jedec,spi-nor"; - reg = <1>; - spi-max-frequency = <25000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; - flash@2 { - compatible = "issi,is25wp032", "jedec,spi-nor"; - reg = <2>; - spi-max-frequency = <25000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; - flash@3 { - compatible = "issi,is25wp032", "jedec,spi-nor"; - reg = <3>; - spi-max-frequency = <25000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -*/ - }; - L30: spi@10050000 { - compatible = "sifive,spi0"; - interrupt-parent = <&L4>; - interrupts = <6>; - reg = <0x0 0x10050000 0x0 0x1000>; - reg-names = "control"; - clocks = <&tlclk>; - - #address-cells = <1>; - #size-cells = <0>; - mmc@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3300 3300>; - disable-wp; - gpios = <&L31 11 1>; - }; - }; - L23: teststatus@4000 { - compatible = "sifive,test0"; - reg = <0x0 0x4000 0x0 0x1000>; - reg-names = "control"; - }; - }; -}; -- To view, visit https://review.coreboot.org/c/coreboot/+/35122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4427d34a12902e0eaa2186121a53152b719cadff Gerrit-Change-Number: 35122 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel: always use pcidev_path_on_root_debug()
by Angel Pons (Code Review) 12 Sep '19

12 Sep '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35088 ) Change subject: soc/intel: always use pcidev_path_on_root_debug() ...................................................................... soc/intel: always use pcidev_path_on_root_debug() PCI devices love to play hide and seek on these chips for mysterious reasons. Therefore, always assume any device could just go missing, even the root bus. BUG=cursed xyz Change-Id: I2283554dfff4e9f2d89ec7bde9304a734a2546b5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/apollolake/uart.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/finalize.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/broadwell/systemagent.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/cannonlake/uart.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/thermal/thermal.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/icelake/uart.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/smmrelocate.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/skylake/uart.c M src/soc/intel/skylake/vr_config.c 38 files changed, 87 insertions(+), 87 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/35088/1 diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index f729f31..785b253 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -175,7 +175,7 @@ static unsigned long soc_fill_dmar(unsigned long current) { - struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + struct device *const igfx_dev = pcidev_path_on_root_debug(SA_DEVFN_IGD); uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; uint64_t defvtbar = MCHBAR64(DEFVTBAR) & VTBAR_MASK; bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; @@ -208,7 +208,7 @@ * get the info and hide it again when done. */ p2sb_unhide(); - struct device *p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB); + struct device *p2sb_dev = pcidev_path_on_root_debug(PCH_DEVFN_P2SB); uint16_t ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF); uint16_t hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF); p2sb_hide(); diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index b69f9ee..0440267 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -256,7 +256,7 @@ int i; unsigned int inc = PCI_DEVFN(0, 1); - func0 = pcidev_path_on_root(devfn0); + func0 = pcidev_path_on_root_debug(devfn0); if (func0 == NULL) return; @@ -272,7 +272,7 @@ * as that port was move to func0. */ for (i = 1; i < num_funcs; i++, devfn += inc) { - struct device *dev = pcidev_path_on_root(devfn); + struct device *dev = pcidev_path_on_root_debug(devfn); if (dev == NULL) continue; @@ -538,7 +538,7 @@ static void parse_devicetree(FSP_S_CONFIG *silconfig) { - struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + struct device *dev = pcidev_path_on_root_debug(SA_DEVFN_ROOT); if (!dev) { printk(BIOS_ERR, "Could not find root device\n"); @@ -672,7 +672,7 @@ /* Load VBT before devicetree-specific config. */ silconfig->GraphicsConfigPtr = (uintptr_t)vbt_get(); - dev = pcidev_path_on_root(SA_DEVFN_ROOT); + dev = pcidev_path_on_root_debug(SA_DEVFN_ROOT); cfg = config_of(dev); mainboard_devtree_update(dev); @@ -743,7 +743,7 @@ apl_fsp_silicon_init_params_cb(cfg, silconfig); /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = pcidev_path_on_root(PCH_DEVFN_XDCI); + dev = pcidev_path_on_root_debug(PCH_DEVFN_XDCI); if (!xdci_can_enable()) dev->enabled = 0; silconfig->UsbOtg = dev->enabled; diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 1464d2c..ae67582 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -332,7 +332,7 @@ static void parse_devicetree_setting(FSPM_UPD *m_upd) { #if CONFIG(SOC_INTEL_GLK) - DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_NPK); + DEVTREE_CONST struct device *dev = pcidev_path_on_root_debug(PCH_DEVFN_NPK); if (!dev) return; diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index f8c4aaf..da61a3f 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -82,13 +82,13 @@ */ switch (uart_console) { case 0: - return pcidev_path_on_root(PCH_DEVFN_UART0); + return pcidev_path_on_root_debug(PCH_DEVFN_UART0); case 1: - return pcidev_path_on_root(PCH_DEVFN_UART1); + return pcidev_path_on_root_debug(PCH_DEVFN_UART1); case 2: - return pcidev_path_on_root(PCH_DEVFN_UART2); + return pcidev_path_on_root_debug(PCH_DEVFN_UART2); case 3: - return pcidev_path_on_root(PCH_DEVFN_UART3); + return pcidev_path_on_root_debug(PCH_DEVFN_UART3); default: printk(BIOS_ERR, "Invalid UART console index\n"); return NULL; diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 705bc00..5e5460c 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -580,7 +580,7 @@ static unsigned long acpi_fill_dmar(unsigned long current) { - struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + struct device *const igfx_dev = pcidev_path_on_root_debug(SA_DEVFN_IGD); const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff; const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1; diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 06cc18d..85a0e74 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -96,7 +96,7 @@ static void broadwell_finalize(void *unused) { - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + struct device *sa_dev = pcidev_path_on_root_debug(SA_DEVFN_ROOT); printk(BIOS_DEBUG, "Finalizing chipset.\n"); diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index b385d6b..1406c28 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -365,7 +365,7 @@ { u32 reg32; u16 reg16; - struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); + struct device *igd_dev = pcidev_path_on_root_debug(SA_DEVFN_IGD); /* DMI */ RCBA32_OR(0x2234, 0xf); diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 61b0c4c..364d98e 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -272,7 +272,7 @@ void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { - struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + struct device *dev = pcidev_path_on_root_debug(SA_DEVFN_ROOT); printk(BIOS_DEBUG, "Setting up SMI for CPU\n"); @@ -321,7 +321,7 @@ void smm_lock(void) { - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + struct device *sa_dev = pcidev_path_on_root_debug(SA_DEVFN_ROOT); /* LOCK the SMM memory window and enable normal SMM. * After running this function, only a full reset can * make the SMM registers writable again. diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index b6b5608..1e32c5b 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -32,20 +32,20 @@ u8 systemagent_revision(void) { - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + struct device *sa_dev = pcidev_path_on_root_debug(SA_DEVFN_ROOT); return pci_read_config8(sa_dev, PCI_REVISION_ID); } uintptr_t sa_get_tolud_base(void) { - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + struct device *sa_dev = pcidev_path_on_root_debug(SA_DEVFN_ROOT); /* Bit 0 is lock bit, not part of address */ return pci_read_config32(sa_dev, TOLUD) & ~1; } uintptr_t sa_get_gsm_base(void) { - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + struct device *sa_dev = pcidev_path_on_root_debug(SA_DEVFN_ROOT); /* Bit 0 is lock bit, not part of address */ return pci_read_config32(sa_dev, BGSM) & ~1; } @@ -294,7 +294,7 @@ uint64_t mc_values[NUM_MAP_ENTRIES]; unsigned long dpr_size = 0; u32 dpr_reg; - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + struct device *sa_dev = pcidev_path_on_root_debug(SA_DEVFN_ROOT); /* Read in the MAP registers and report their values. */ mc_read_map_entries(dev, &mc_values[0]); diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 89770c0..30c1361 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -294,7 +294,7 @@ static unsigned long soc_fill_dmar(unsigned long current) { - struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + struct device *const igfx_dev = pcidev_path_on_root_debug(SA_DEVFN_IGD); uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK; bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED; @@ -307,7 +307,7 @@ acpi_dmar_drhd_fixup(tmp, current); } - struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU); + struct device *const ipu_dev = pcidev_path_on_root_debug(SA_DEVFN_IPU); uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK; bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 494c1db..b6a2df5 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -53,7 +53,7 @@ { struct device *dev; - dev = pcidev_path_on_root(serial_io_dev[dev_offset]); + dev = pcidev_path_on_root_debug(serial_io_dev[dev_offset]); if (!dev || !dev->enabled) return PCH_SERIAL_IO_INDEX(PchSerialIoDisabled); @@ -175,7 +175,7 @@ params->PchLockDownRtcMemoryLock = 0; /* SATA */ - dev = pcidev_path_on_root(PCH_DEVFN_SATA); + dev = pcidev_path_on_root_debug(PCH_DEVFN_SATA); if (!dev) params->SataEnable = 0; else { @@ -189,7 +189,7 @@ } /* Lan */ - dev = pcidev_path_on_root(PCH_DEVFN_GBE); + dev = pcidev_path_on_root_debug(PCH_DEVFN_GBE); if (!dev) params->PchLanEnable = 0; else { @@ -272,7 +272,7 @@ } /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); + dev = pcidev_path_on_root_debug(PCH_DEVFN_USBOTG); if (dev) { if (!xdci_can_enable()) dev->enabled = 0; @@ -287,7 +287,7 @@ #endif /* Enable CNVi Wifi if enabled in device tree */ - dev = pcidev_path_on_root(PCH_DEVFN_CNViWIFI); + dev = pcidev_path_on_root_debug(PCH_DEVFN_CNViWIFI); #if CONFIG(SOC_INTEL_COMETLAKE) if (dev) params->CnviMode = dev->enabled; @@ -314,7 +314,7 @@ sizeof(config->PcieRpHotPlug)); /* eMMC and SD */ - dev = pcidev_path_on_root(PCH_DEVFN_EMMC); + dev = pcidev_path_on_root_debug(PCH_DEVFN_EMMC); if (!dev) params->ScsEmmcEnabled = 0; else { @@ -329,7 +329,7 @@ } } - dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); + dev = pcidev_path_on_root_debug(PCH_DEVFN_SDCARD); if (!dev) { params->ScsSdCardEnabled = 0; } else { @@ -341,7 +341,7 @@ #endif } - dev = pcidev_path_on_root(PCH_DEVFN_UFS); + dev = pcidev_path_on_root_debug(PCH_DEVFN_UFS); if (!dev) params->ScsUfsEnabled = 0; else diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 3ba997d..6ed4b3c 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -30,7 +30,7 @@ { unsigned int i; uint32_t mask = 0; - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_ISH); + const struct device *dev = pcidev_path_on_root_debug(PCH_DEVFN_ISH); /* Set IGD stolen size to 64MB. */ m_cfg->IgdDvmt50PreAlloc = 2; @@ -85,7 +85,7 @@ m_cfg->PchIshEnable = dev->enabled; /* If HDA is enabled, enable HDA elements */ - dev = pcidev_path_on_root(PCH_DEVFN_HDA); + dev = pcidev_path_on_root_debug(PCH_DEVFN_HDA); if (!dev) m_cfg->PchHdaEnable = 0; else @@ -93,15 +93,15 @@ /* Enable IPU only if the device is enabled */ m_cfg->SaIpuEnable = 0; - dev = pcidev_path_on_root(SA_DEVFN_IPU); + dev = pcidev_path_on_root_debug(SA_DEVFN_IPU); if (dev) m_cfg->SaIpuEnable = dev->enabled; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); - const struct device *smbus = pcidev_path_on_root(PCH_DEVFN_SMBUS); + const struct device *dev = pcidev_path_on_root_debug(PCH_DEVFN_LPC); + const struct device *smbus = pcidev_path_on_root_debug(PCH_DEVFN_SMBUS); assert(dev != NULL); const config_t *config = config_of(dev); FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 493d003..0b8b7e2 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -257,7 +257,7 @@ void smm_lock(void) { - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + struct device *sa_dev = pcidev_path_on_root_debug(SA_DEVFN_ROOT); /* * LOCK the SMM memory window and enable normal SMM. * After running this function, only a full reset can diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index ae19acc..2d7e1d1 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -58,11 +58,11 @@ */ switch (uart_console) { case 0: - return pcidev_path_on_root(PCH_DEVFN_UART0); + return pcidev_path_on_root_debug(PCH_DEVFN_UART0); case 1: - return pcidev_path_on_root(PCH_DEVFN_UART1); + return pcidev_path_on_root_debug(PCH_DEVFN_UART1); case 2: - return pcidev_path_on_root(PCH_DEVFN_UART2); + return pcidev_path_on_root_debug(PCH_DEVFN_UART2); default: printk(BIOS_ERR, "Invalid UART console index\n"); return NULL; diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 2b4c4a7..b050320 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -56,7 +56,7 @@ uintptr_t graphics_get_memory_base(void) { uintptr_t memory_base; - struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + struct device *dev = pcidev_path_on_root_debug(SA_DEVFN_IGD); if (is_graphics_disabled(dev)) return 0; @@ -75,7 +75,7 @@ static uintptr_t graphics_get_gtt_base(void) { static uintptr_t gtt_base; - struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + struct device *dev = pcidev_path_on_root_debug(SA_DEVFN_IGD); if (is_graphics_disabled(dev)) die("IGD is disabled!"); diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index f937bd6..4224b22 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -236,7 +236,7 @@ if (devfn < 0) return 0; - dev = pcidev_path_on_root(devfn); + dev = pcidev_path_on_root_debug(devfn); if (!dev || !dev->enabled) return 0; @@ -474,7 +474,7 @@ * devfn is already validated as part of gspi_ctrlr_params_init. * No need to revalidate it again. */ - device = pcidev_path_on_root(devfn); + device = pcidev_path_on_root_debug(devfn); /* Ensure controller is in D0 state */ lpss_set_power_state(device, STATE_D0); diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 854a61a..3dbe6dd 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -65,7 +65,7 @@ /* Look up the controller device in the devicetree */ dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); - tree_dev = pcidev_path_on_root(devfn); + tree_dev = pcidev_path_on_root_debug(devfn); if (!tree_dev || !tree_dev->enabled) { printk(BIOS_ERR, "I2C%u device not enabled\n", bus); return -1; @@ -137,7 +137,7 @@ return (uintptr_t)NULL; /* devfn -> dev */ - dev = pcidev_path_on_root(devfn); + dev = pcidev_path_on_root_debug(devfn); if (!dev || !dev->enabled) return (uintptr_t)NULL; diff --git a/src/soc/intel/common/block/thermal/thermal.c b/src/soc/intel/common/block/thermal/thermal.c index 39a98a4..9fe19a5 100644 --- a/src/soc/intel/common/block/thermal/thermal.c +++ b/src/soc/intel/common/block/thermal/thermal.c @@ -62,7 +62,7 @@ struct device *dev; struct resource *res; - dev = pcidev_path_on_root(PCH_DEVFN_THERMAL); + dev = pcidev_path_on_root_debug(PCH_DEVFN_THERMAL); if (!dev) { printk(BIOS_ERR, "ERROR: PCH_DEVFN_THERMAL device not found!\n"); return; diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 0bdf1d9..d0c1494 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -75,7 +75,7 @@ struct drivers_usb_acpi_config *config; bool enable; - xhci = pcidev_path_on_root(PCH_DEVFN_XHCI); + xhci = pcidev_path_on_root_debug(PCH_DEVFN_XHCI); if (!xhci) { printk(BIOS_ERR, "%s: Could not locate XHCI device in DT\n", __func__); return; diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index 0cca4b9..685affe 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -30,7 +30,7 @@ #if defined(__SIMPLE_DEVICE__) pci_devfn_t dev = SA_DEV_ROOT; #else - struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + struct device *dev = pcidev_path_on_root_debug(SA_DEVFN_ROOT); #endif /* All regions concerned for have 1 MiB alignment. */ return ALIGN_DOWN(pci_read_config32(dev, reg), 1 * MiB); diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index fb941ab..8bd3818 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -175,7 +175,7 @@ void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - struct device *lpcdev = pcidev_path_on_root(FADT_SOC_LPC_DEVFN); + struct device *lpcdev = pcidev_path_on_root_debug(FADT_SOC_LPC_DEVFN); u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0; config_t *config = config_of(lpcdev); diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index 48f0cdd..61604a8 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -80,7 +80,7 @@ DEVTREE_CONST config_t *config; printk(FSP_INFO_LEVEL, "Configure Default UPD Data\n"); - dev = pcidev_path_on_root(SOC_DEV_FUNC); + dev = pcidev_path_on_root_debug(SOC_DEV_FUNC); config = config_of(dev); /* Set up default verb tables - Just HDMI audio */ diff --git a/src/soc/intel/fsp_broadwell_de/acpi.c b/src/soc/intel/fsp_broadwell_de/acpi.c index fef7773..692bf98 100644 --- a/src/soc/intel/fsp_broadwell_de/acpi.c +++ b/src/soc/intel/fsp_broadwell_de/acpi.c @@ -316,7 +316,7 @@ static unsigned long acpi_fill_dmar(unsigned long current) { uint32_t vtbar, tmp = current; - struct device *dev = pcidev_path_on_root(VTD_DEV_FUNC); + struct device *dev = pcidev_path_on_root_debug(VTD_DEV_FUNC); uint16_t bdf, hpet_bdf[8]; uint8_t i, j; @@ -333,7 +333,7 @@ current += acpi_create_dmar_ds_ioapic(current, 9, 0, 5, 4); /* Get the PCI BDF for the PCH I/O APIC */ - dev = pcidev_path_on_root(LPC_DEV_FUNC); + dev = pcidev_path_on_root_debug(LPC_DEV_FUNC); bdf = pci_read_config16(dev, 0x6c); current += acpi_create_dmar_ds_ioapic(current, 8, (bdf >> 8), PCI_SLOT(bdf), PCI_FUNC(bdf)); diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index e31e47b..3506e25 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -93,7 +93,7 @@ mainboard_silicon_init_params(params); - dev = pcidev_path_on_root(SA_DEVFN_IGD); + dev = pcidev_path_on_root_debug(SA_DEVFN_IGD); if (!dev || !dev->enabled) { /* diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index a78c8a4..f63440a 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -25,7 +25,7 @@ const struct soc_intel_icelake_config *config) { unsigned int i; - const struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + const struct device *dev = pcidev_path_on_root_debug(SA_DEVFN_IGD); uint32_t mask = 0; if (!dev || !dev->enabled) { @@ -49,7 +49,7 @@ m_cfg->SkipMbpHob = 1; /* If Audio Codec is enabled, enable FSP UPD */ - dev = pcidev_path_on_root(PCH_DEVFN_HDA); + dev = pcidev_path_on_root_debug(PCH_DEVFN_HDA); if (!dev) m_cfg->PchHdaEnable = 0; else diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 65505c4..8093b7a 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -256,7 +256,7 @@ void smm_lock(void) { - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + struct device *sa_dev = pcidev_path_on_root_debug(SA_DEVFN_ROOT); /* * LOCK the SMM memory window and enable normal SMM. * After running this function, only a full reset can diff --git a/src/soc/intel/icelake/uart.c b/src/soc/intel/icelake/uart.c index ae19acc..2d7e1d1 100644 --- a/src/soc/intel/icelake/uart.c +++ b/src/soc/intel/icelake/uart.c @@ -58,11 +58,11 @@ */ switch (uart_console) { case 0: - return pcidev_path_on_root(PCH_DEVFN_UART0); + return pcidev_path_on_root_debug(PCH_DEVFN_UART0); case 1: - return pcidev_path_on_root(PCH_DEVFN_UART1); + return pcidev_path_on_root_debug(PCH_DEVFN_UART1); case 2: - return pcidev_path_on_root(PCH_DEVFN_UART2); + return pcidev_path_on_root_debug(PCH_DEVFN_UART2); default: printk(BIOS_ERR, "Invalid UART console index\n"); return NULL; diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index aa51cbe..aafaa9f 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -552,7 +552,7 @@ static unsigned long acpi_fill_dmar(unsigned long current) { - struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD); + struct device *const igfx_dev = pcidev_path_on_root_debug(SA_DEVFN_IGD); const u32 gfx_vtbar = MCHBAR32(GFXVTBAR) & ~0xfff; const bool gfxvten = MCHBAR32(GFXVTBAR) & 1; @@ -575,7 +575,7 @@ acpi_dmar_rmrr_fixup(tmp, current); } - struct device *const p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB); + struct device *const p2sb_dev = pcidev_path_on_root_debug(PCH_DEVFN_P2SB); const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; const bool vtvc0en = MCHBAR32(VTVC0BAR) & 1; diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index a7d5872..fd283fc 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -92,7 +92,7 @@ /* UPD parameters to be initialized before SiliconInit */ void soc_silicon_init_params(SILICON_INIT_UPD *params) { - struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); + struct device *dev = pcidev_path_on_root_debug(PCH_DEVFN_LPC); const struct soc_intel_skylake_config *config = config_of(dev); int i; @@ -152,7 +152,7 @@ params->ScsSdCardEnabled = config->ScsSdCardEnabled; /* Enable ISH if device is on */ - dev = pcidev_path_on_root(PCH_DEVFN_ISH); + dev = pcidev_path_on_root_debug(PCH_DEVFN_ISH); if (dev) params->IshEnable = dev->enabled; else @@ -219,11 +219,11 @@ fill_vr_domain_config(params, i, &config->domain_vr_config[i]); /* Show SPI controller if enabled in devicetree.cb */ - dev = pcidev_path_on_root(PCH_DEVFN_SPI); + dev = pcidev_path_on_root_debug(PCH_DEVFN_SPI); params->ShowSpiController = dev->enabled; /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); + dev = pcidev_path_on_root_debug(PCH_DEVFN_USBOTG); if (!xdci_can_enable()) dev->enabled = 0; params->XdciEnable = dev->enabled; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 064f71e..c61937a 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -102,7 +102,7 @@ for (group = 0; group < pci_groups; group++) { devfn0 = pcie_rp_group[group].devfn; - func0 = pcidev_path_on_root(devfn0); + func0 = pcidev_path_on_root_debug(devfn0); if (func0 == NULL) continue; @@ -119,7 +119,7 @@ */ for (i = 1; i < pcie_rp_group[group].func_count; i++, devfn += inc) { - struct device *dev = pcidev_path_on_root(devfn); + struct device *dev = pcidev_path_on_root_debug(devfn); if (dev == NULL || !dev->enabled) continue; @@ -353,7 +353,7 @@ } /* If ISH is enabled, enable ISH elements */ - dev = pcidev_path_on_root(PCH_DEVFN_ISH); + dev = pcidev_path_on_root_debug(PCH_DEVFN_ISH); if (dev) params->PchIshEnable = dev->enabled; else @@ -432,11 +432,11 @@ fill_vr_domain_config(params, i, &config->domain_vr_config[i]); /* Show SPI controller if enabled in devicetree.cb */ - dev = pcidev_path_on_root(PCH_DEVFN_SPI); + dev = pcidev_path_on_root_debug(PCH_DEVFN_SPI); params->ShowSpiController = dev->enabled; /* Enable xDCI controller if enabled in devicetree and allowed */ - dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); + dev = pcidev_path_on_root_debug(PCH_DEVFN_USBOTG); if (!xdci_can_enable()) dev->enabled = 0; params->XdciEnable = dev->enabled; diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index ddaffda..2f02959 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -223,7 +223,7 @@ uint32_t i, intdeventry; u8 irq_config[PCH_MAX_IRQ_CONFIG]; - const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); + const struct device *dev = pcidev_path_on_root_debug(PCH_DEVFN_LPC); const struct soc_intel_skylake_config *config = config_of(dev); /* Get Device Int Count */ diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 9d3f377..c9f0f9d 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -113,7 +113,7 @@ /* Calculate Intel Traditional Memory size based on GSM, DSM, TSEG and DPR. */ static size_t calculate_traditional_mem_size(uintptr_t dram_base) { - const struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); + const struct device *igd_dev = pcidev_path_on_root_debug(SA_DEVFN_IGD); uintptr_t traditional_mem_base = dram_base; size_t traditional_mem_size; @@ -143,7 +143,7 @@ */ static size_t calculate_reserved_mem_size(uintptr_t dram_base) { - const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + const struct device *dev = pcidev_path_on_root_debug(SA_DEVFN_ROOT); uintptr_t reserve_mem_base = dram_base; size_t reserve_mem_size; const struct soc_intel_skylake_config *config; diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 8b5cd18..985c861 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -300,7 +300,7 @@ { const struct device *dev; - dev = pcidev_path_on_root(SA_DEVFN_IGD); + dev = pcidev_path_on_root_debug(SA_DEVFN_IGD); if (!dev || !dev->enabled) { /* * If iGPU is disabled or not defined in the devicetree.cb, diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index 9b7ea24..e444698 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -26,7 +26,7 @@ static void systemagent_vtd_init(void) { - const struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); + const struct device *const igd_dev = pcidev_path_on_root_debug(SA_DEVFN_IGD); const struct soc_intel_skylake_config *config = NULL; config = config_of_path(SA_DEVFN_ROOT); diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index e1779d1..f3117c2 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -256,7 +256,7 @@ void smm_lock(void) { - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + struct device *sa_dev = pcidev_path_on_root_debug(SA_DEVFN_ROOT); /* * LOCK the SMM memory window and enable normal SMM. * After running this function, only a full reset can diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index 410265f..2f56cf9 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -29,7 +29,7 @@ bool soc_is_vtd_capable(void) { - struct device *const root_dev = pcidev_path_on_root(SA_DEVFN_ROOT); + struct device *const root_dev = pcidev_path_on_root_debug(SA_DEVFN_ROOT); return root_dev && !(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE); } @@ -42,7 +42,7 @@ */ void soc_add_fixed_mmio_resources(struct device *dev, int *index) { - struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); + struct device *const igd_dev = pcidev_path_on_root_debug(SA_DEVFN_IGD); static const struct sa_mmio_descriptor soc_fixed_resources[] = { { PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH, diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 18fcf1b..d049c60 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -59,11 +59,11 @@ */ switch (uart_console) { case 0: - return pcidev_path_on_root(PCH_DEVFN_UART0); + return pcidev_path_on_root_debug(PCH_DEVFN_UART0); case 1: - return pcidev_path_on_root(PCH_DEVFN_UART1); + return pcidev_path_on_root_debug(PCH_DEVFN_UART1); case 2: - return pcidev_path_on_root(PCH_DEVFN_UART2); + return pcidev_path_on_root_debug(PCH_DEVFN_UART2); default: printk(BIOS_ERR, "Invalid UART console index\n"); return NULL; diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 089dd5d..5c92fb4 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -94,18 +94,18 @@ static uint16_t mch_id = 0, igd_id = 0, lpc_id = 0; if (!mch_id) { - struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + struct device *dev = pcidev_path_on_root_debug(SA_DEVFN_ROOT); mch_id = pci_read_config16(dev, PCI_DEVICE_ID); } if (!igd_id) { - struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + struct device *dev = pcidev_path_on_root_debug(SA_DEVFN_IGD); if (dev) igd_id = pci_read_config16(dev, PCI_DEVICE_ID); else igd_id = 0xffff; } if (!lpc_id) { - struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); + struct device *dev = pcidev_path_on_root_debug(PCH_DEVFN_LPC); lpc_id = pci_read_config16(dev, PCI_DEVICE_ID); } @@ -225,11 +225,11 @@ { static uint16_t mch_id = 0, igd_id = 0; if (!mch_id) { - struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + struct device *dev = pcidev_path_on_root_debug(SA_DEVFN_ROOT); mch_id = pci_read_config16(dev, PCI_DEVICE_ID); } if (!igd_id) { - struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + struct device *dev = pcidev_path_on_root_debug(SA_DEVFN_IGD); if (dev) igd_id = pci_read_config16(dev, PCI_DEVICE_ID); else -- To view, visit https://review.coreboot.org/c/coreboot/+/35088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2283554dfff4e9f2d89ec7bde9304a734a2546b5 Gerrit-Change-Number: 35088 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/google/hatch: Configure SATA DEVSLP pad reset config to PLT_RST
by Aamir Bohra (Code Review) 12 Sep '19

12 Sep '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35307 ) Change subject: mb/google/hatch: Configure SATA DEVSLP pad reset config to PLT_RST ...................................................................... mb/google/hatch: Configure SATA DEVSLP pad reset config to PLT_RST Change-Id: Ia12174e3254153dbca55070f5daf84fd8aac51d0 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/35307/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 8b5fc1a..866a2e5 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -24,6 +24,8 @@ register "SataMode" = "Sata_AHCI" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" + # Configure devslp pad reset to PLT_RST + register "SataPortsDevSlpResetConfig[1]" = "5" register "satapwroptimize" = "1" # Enable System Agent dynamic frequency register "SaGv" = "SaGv_Enabled" -- To view, visit https://review.coreboot.org/c/coreboot/+/35307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia12174e3254153dbca55070f5daf84fd8aac51d0 Gerrit-Change-Number: 35307 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

5 8

Change in coreboot[master]: soc/intel/cannonlake: Add config for sata devslp pad reset configuration
by Aamir Bohra (Code Review) 12 Sep '19

12 Sep '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35306 ) Change subject: soc/intel/cannonlake: Add config for sata devslp pad reset configuration ...................................................................... soc/intel/cannonlake: Add config for sata devslp pad reset configuration CML FSP now provides a provision to configure the SATA devslp GPIO pad reset configuration. This config would help set the the required pad reset configuration. Change-Id: I4eaea9c6da67f1274ad3e392046a68cddc1b99b6 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/chip.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/35306/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 2ebe017..8b74aec 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -139,6 +139,7 @@ uint8_t SataSalpSupport; uint8_t SataPortsEnable[8]; uint8_t SataPortsDevSlp[8]; + uint8_t SataPortsDevSlpResetConfig[8]; /* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */ uint8_t SlpS0WithGbeSupport; -- To view, visit https://review.coreboot.org/c/coreboot/+/35306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4eaea9c6da67f1274ad3e392046a68cddc1b99b6 Gerrit-Change-Number: 35306 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

5 12

Change in coreboot[master]: soc/intel/{cnl, icl}: Cache the TSEG region
by Subrata Banik (Code Review) 12 Sep '19

12 Sep '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35026 ) Change subject: soc/intel/{cnl, icl}: Cache the TSEG region ...................................................................... soc/intel/{cnl, icl}: Cache the TSEG region Change-Id: Ie92d2c9e50fa299db1cd8c57a6047ea3adaf1452 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/icelake/romstage/romstage.c 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/35026/1 diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 9f02c8b..9e2f2f8 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -165,5 +165,8 @@ /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + /* Cache the TSEG region. */ + enable_tseg_cache(&pcf); + run_postcar_phase(&pcf); } diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 8312f17..4d0cc17 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -149,5 +149,8 @@ /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); + /* Cache the TSEG region. */ + enable_tseg_cache(&pcf); + run_postcar_phase(&pcf); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie92d2c9e50fa299db1cd8c57a6047ea3adaf1452 Gerrit-Change-Number: 35026 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 25

Change in coreboot[master]: soc/{amd, intel}: Make use of common enable_tseg_cache() API
by Subrata Banik (Code Review) 12 Sep '19

12 Sep '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35025 ) Change subject: soc/{amd, intel}: Make use of common enable_tseg_cache() API ...................................................................... soc/{amd, intel}: Make use of common enable_tseg_cache() API This patch removes dedicated function call to make TSEG region cache from soc and refers to enable_tseg_cache(). Change-Id: I18a032b43a2093c8ae86735c119d8dfee40570b1 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 5 files changed, 10 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35025/1 diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 4f18b42..a41314d 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -44,8 +44,6 @@ { struct postcar_frame pcf; uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size; int s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); console_init(); @@ -87,15 +85,8 @@ /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + /* Cache the TSEG region. */ + enable_tseg_cache(&pcf); post_code(0x45); run_postcar_phase(&pcf); diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index 0d65ef6..09563bb 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -85,8 +85,6 @@ { struct postcar_frame pcf; uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size; msr_t base, mask; msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR); int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT; @@ -172,15 +170,8 @@ /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + /* Cache the TSEG region. */ + enable_tseg_cache(&pcf); post_code(0x45); run_postcar_phase(&pcf); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 1464d2c..ba86a43 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -246,15 +246,8 @@ /* Cache the memory-mapped boot media. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); - /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + /* Cache the TSEG region. */ + enable_tseg_cache(&pcf); run_postcar_phase(&pcf); } diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 9c41486..af65d38 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -142,8 +142,6 @@ struct postcar_frame pcf; uintptr_t top_of_ram; - uintptr_t smm_base; - size_t smm_size; console_init(); @@ -182,8 +180,8 @@ * region for other purposes. */ if (CONFIG(HAVE_SMI_HANDLER)) { - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, MTRR_TYPE_WRBACK); + /* Cache the TSEG region. */ + enable_tseg_cache(&pcf); } run_postcar_phase(&pcf); diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 8b5cd18..1d925b3 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -174,19 +174,8 @@ postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); if (CONFIG(HAVE_SMI_HANDLER)) { - uintptr_t smm_base; - size_t smm_size; - - /* - * Cache the TSEG region at the top of ram. This region is - * not restricted to SMM mode until SMM has been relocated. - * By setting the region to cacheable it provides faster access - * when relocating the SMM handler as well as using the TSEG - * region for other purposes. - */ - smm_region(&smm_base, &smm_size); - postcar_frame_add_mtrr(&pcf, smm_base, smm_size, - MTRR_TYPE_WRBACK); + /* Cache the TSEG region. */ + enable_tseg_cache(&pcf); } /* Cache the ROM as WP just below 4GiB. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18a032b43a2093c8ae86735c119d8dfee40570b1 Gerrit-Change-Number: 35025 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/{cnl, icl}: Allocate 64KB as FSP heap
by Subrata Banik (Code Review) 12 Sep '19

12 Sep '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35237 ) Change subject: soc/intel/{cnl, icl}: Allocate 64KB as FSP heap ...................................................................... soc/intel/{cnl, icl}: Allocate 64KB as FSP heap TEST=Build and boot CML-Hatch With this CL No "Smashed stack detected in romstage" msg in serial log. Change-Id: Icc39cdb71f427189186222ae53b8881cbbd5e0bc Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/icelake/Kconfig 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/35237/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index d949fff..ac100e2 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -125,6 +125,13 @@ The amount of anticipated stack usage in CAR by bootblock and other stages. +config DCACHE_BSP_HEAP_SIZE + hex + depends on FSP_USES_CB_STACK + default 0x10000 + help + The amount of anticipated heap usage in CAR by FSP. + config IFD_CHIPSET string default "cnl" diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 1bd478c..78bd133 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -76,6 +76,13 @@ The amount of anticipated stack usage in CAR by bootblock and other stages. +config DCACHE_BSP_HEAP_SIZE + hex + depends on FSP_USES_CB_STACK + default 0x10000 + help + The amount of anticipated heap usage in CAR by FSP. + config IFD_CHIPSET string default "icl" -- To view, visit https://review.coreboot.org/c/coreboot/+/35237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc39cdb71f427189186222ae53b8881cbbd5e0bc Gerrit-Change-Number: 35237 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2019