Change in coreboot[master]: soc/intel/cannonlake: Add config for sata devslp pad reset configuration

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35306 )

Change subject: soc/intel/cannonlake: Add config for sata devslp pad reset configuration
......................................................................

soc/intel/cannonlake: Add config for sata devslp pad reset configuration

CML FSP now provides a provision to configure the SATA devslp
GPIO pad reset configuration. This config would help set the
the required pad reset configuration.

Change-Id: I4eaea9c6da67f1274ad3e392046a68cddc1b99b6
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/cannonlake/chip.h
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/35306/1

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 2ebe017..8b74aec 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -139,6 +139,7 @@
    uint8_t SataSalpSupport;
    uint8_t SataPortsEnable[8];
    uint8_t SataPortsDevSlp[8];
+	uint8_t SataPortsDevSlpResetConfig[8];

/* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */
    uint8_t SlpS0WithGbeSupport;

[Aamir Bohra (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35306

to look at the new patch set (#2).

Change subject: soc/intel/cannonlake: Add config for sata devslp pad reset configuration
......................................................................

soc/intel/cannonlake: Add config for sata devslp pad reset configuration

CML FSP now provides a provision to configure the SATA devslp
GPIO pad reset configuration. This config would help set the
the required pad reset configuration.

Change-Id: I4eaea9c6da67f1274ad3e392046a68cddc1b99b6
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/35306/2

[Aamir Bohra (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35306

to look at the new patch set (#3).

Change subject: soc/intel/cannonlake: Add config for sata devslp pad reset configuration
......................................................................

soc/intel/cannonlake: Add config for sata devslp pad reset configuration

CML FSP now provides a provision to configure the SATA devslp
GPIO pad reset configuration. This config would help set the
the required pad reset configuration.

Change-Id: I4eaea9c6da67f1274ad3e392046a68cddc1b99b6
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/35306/3

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35306 )

Change subject: soc/intel/cannonlake: Add config for sata devslp pad reset configuration
......................................................................

Patch Set 3: Code-Review+2

LGTM Aamir, could we get BUG=b:133000685 in the commit msg?

[Aamir Bohra (Code Review)]

Hello Patrick Rudolph, Subrata Banik, Tim Wawrzynczak, build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35306

to look at the new patch set (#4).

Change subject: soc/intel/cannonlake: Add config for sata devslp pad reset configuration
......................................................................

soc/intel/cannonlake: Add config for sata devslp pad reset configuration

CML FSP now provides a provision to configure the SATA devslp
GPIO pad reset configuration. This config would help set the
the required pad reset configuration.

BUG=b:133000685

Change-Id: I4eaea9c6da67f1274ad3e392046a68cddc1b99b6
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/35306/4

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35306 )

Change subject: soc/intel/cannonlake: Add config for sata devslp pad reset configuration
......................................................................

Patch Set 4:
> Patch Set 3: Code-Review+2
>
> LGTM Aamir, could we get BUG=b:133000685 in the commit msg?

Ok, Done.

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35306 )

Change subject: soc/intel/cannonlake: Add config for sata devslp pad reset configuration
......................................................................

Patch Set 4: Code-Review+2

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35306 )

Change subject: soc/intel/cannonlake: Add config for sata devslp pad reset configuration
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35306/4/src/soc/intel/cannonlake/ch... 
File src/soc/intel/cannonlake/chip.h:

https://review.coreboot.org/c/coreboot/+/35306/4/src/soc/intel/cannonlake/ch... 
PS4, Line 145: 7
do we need a comma here ?

[Aamir Bohra (Code Review)]

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35306 )

Change subject: soc/intel/cannonlake: Add config for sata devslp pad reset configuration
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35306/4/src/soc/intel/cannonlake/ch... 
File src/soc/intel/cannonlake/chip.h:

https://review.coreboot.org/c/coreboot/+/35306/4/src/soc/intel/cannonlake/ch... 
PS4, Line 145: 7
> do we need a comma here ?

not required.

[V Sowmya (Code Review)]

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35306 )

Change subject: soc/intel/cannonlake: Add config for sata devslp pad reset configuration
......................................................................

Patch Set 4: Code-Review+2

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35306 )

Change subject: soc/intel/cannonlake: Add config for sata devslp pad reset configuration
......................................................................

Patch Set 4: Code-Review+2

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35306 )

Change subject: soc/intel/cannonlake: Add config for sata devslp pad reset configuration
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35306/4/src/soc/intel/cannonlake/ch... 
File src/soc/intel/cannonlake/chip.h:

https://review.coreboot.org/c/coreboot/+/35306/4/src/soc/intel/cannonlake/ch... 
PS4, Line 145: 7
> not required.

Done

[Furquan Shaikh (Code Review)]

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35306 )

Change subject: soc/intel/cannonlake: Add config for sata devslp pad reset configuration
......................................................................

soc/intel/cannonlake: Add config for sata devslp pad reset configuration

CML FSP now provides a provision to configure the SATA devslp
GPIO pad reset configuration. This config would help set the
the required pad reset configuration.

BUG=b:133000685

Change-Id: I4eaea9c6da67f1274ad3e392046a68cddc1b99b6
Signed-off-by: Aamir Bohra 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35306
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
Reviewed-by: V Sowmya 
Reviewed-by: Subrata Banik 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 15 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  V Sowmya: Looks good to me, approved
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 2ebe017..9c7c171 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -136,9 +136,19 @@
    	Sata_AHCI,
    	Sata_RAID,
    } SataMode;
+
+	/* SATA devslp pad reset configuration */
+	enum {
+		SataDevSlpResumeReset = 1,
+		SataDevSlpHostDeepReset = 3,
+		SataDevSlpPlatformReset = 5,
+		SataDevSlpDswReset = 7
+	} SataDevSlpRstConfig;
+
    uint8_t SataSalpSupport;
    uint8_t SataPortsEnable[8];
    uint8_t SataPortsDevSlp[8];
+	uint8_t SataPortsDevSlpResetConfig[8];

/* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */
    uint8_t SlpS0WithGbeSupport;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 4038335..f48a626 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -186,6 +186,11 @@
    		sizeof(params->SataPortsEnable));
    	memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
    		sizeof(params->SataPortsDevSlp));
+#if CONFIG(SOC_INTEL_COMETLAKE)
+		memcpy(params->SataPortsDevSlpResetConfig,
+			config->SataPortsDevSlpResetConfig,
+			sizeof(params->SataPortsDevSlpResetConfig));
+#endif
    }

/* Lan */