Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35122 )
Change subject: sifive: Update devicetree ......................................................................
sifive: Update devicetree
With the current devicetree the kernel doesn't provide any serial after serial init. Update the devicetree to resolve this issue.
Tested on HiFive Unleashed.
Change-Id: I4427d34a12902e0eaa2186121a53152b719cadff Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/sifive/hifive-unleashed/Makefile.inc A src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi A src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts D src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts 4 files changed, 343 insertions(+), 641 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/35122/1
diff --git a/src/mainboard/sifive/hifive-unleashed/Makefile.inc b/src/mainboard/sifive/hifive-unleashed/Makefile.inc index 8ce266f..88ea145 100644 --- a/src/mainboard/sifive/hifive-unleashed/Makefile.inc +++ b/src/mainboard/sifive/hifive-unleashed/Makefile.inc @@ -24,7 +24,7 @@
DTB=$(obj)/hifive-unleashed.dtb -DTS=src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts +DTS=src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts $(DTB): $(DTS) dtc -I dts -O dtb -o $(DTB) $(DTS)
diff --git a/src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi b/src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi new file mode 100644 index 0000000..3dc27c3 --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi @@ -0,0 +1,245 @@ +/* + * This file is part of the Linux kernel. + * + * Copyright (c) 2018-2019 SiFive, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + cpu0: cpu@0 { + compatible = "sifive,e51", "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "disabled"; + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu1: cpu@1 { + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu2: cpu@2 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu3: cpu@3 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + cpu4: cpu@4 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + tlb-split; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; + ranges; + plic0: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev = <53>; + interrupt-controller; + interrupts-extended = < + &cpu0_intc 0xffffffff + &cpu1_intc 0xffffffff &cpu1_intc 9 + &cpu2_intc 0xffffffff &cpu2_intc 9 + &cpu3_intc 0xffffffff &cpu3_intc 9 + &cpu4_intc 0xffffffff &cpu4_intc 9>; + }; + prci: clock-controller@10000000 { + compatible = "sifive,fu540-c000-prci"; + reg = <0x0 0x10000000 0x0 0x1000>; + clocks = <&hfclk>, <&rtcclk>; + #clock-cells = <1>; + }; + uart0: serial@10010000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10010000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <4>; + clocks = <&prci 3>; + status = "disabled"; + }; + uart1: serial@10011000 { + compatible = "sifive,fu540-c000-uart", "sifive,uart0"; + reg = <0x0 0x10011000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <5>; + clocks = <&prci 3>; + status = "disabled"; + }; + i2c0: i2c@10030000 { + compatible = "sifive,fu540-c000-i2c", "sifive,i2c0"; + reg = <0x0 0x10030000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <50>; + clocks = <&prci 3>; + reg-shift = <2>; + reg-io-width = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi0: spi@10040000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10040000 0x0 0x1000 + 0x0 0x20000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <51>; + clocks = <&prci 3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi1: spi@10041000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10041000 0x0 0x1000 + 0x0 0x30000000 0x0 0x10000000>; + interrupt-parent = <&plic0>; + interrupts = <52>; + clocks = <&prci 3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + qspi2: spi@10050000 { + compatible = "sifive,fu540-c000-spi", "sifive,spi0"; + reg = <0x0 0x10050000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <6>; + clocks = <&prci 3>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + eth0: ethernet@10090000 { + compatible = "sifive,fu540-c000-gem"; + interrupt-parent = <&plic0>; + interrupts = <53>; + reg = <0x0 0x10090000 0x0 0x2000 + 0x0 0x100a0000 0x0 0x1000>; + local-mac-address = [00 00 00 00 00 00]; + clock-names = "pclk", "hclk"; + clocks = <&prci 2>, <&prci 2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + }; +}; diff --git a/src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts b/src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts new file mode 100644 index 0000000..454c3d8 --- /dev/null +++ b/src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts @@ -0,0 +1,97 @@ +/* + * This file is part of the Linux kernel. + * + * Copyright (c) 2018-2019 SiFive, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/include/ "fu540-c000.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "SiFive HiFive Unleashed A00"; + compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; + + chosen { + }; + + cpus { + /* Clock frequency (in Hz) of the PCB crystal for rtcclk */ + timebase-frequency = <1000000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; + + soc { + }; + + hfclk: hfclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "hfclk"; + }; + + rtcclk: rtcclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <1000000>; + clock-output-names = "rtcclk"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&qspi0 { + status = "okay"; + flash@0 { + compatible = "issi,is25wp256", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&qspi2 { + status = "okay"; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + }; +}; + +ð0 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; diff --git a/src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts b/src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts deleted file mode 100644 index 6b9bbaa..0000000 --- a/src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts +++ /dev/null @@ -1,640 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2018 SiFive, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -/dts-v1/; - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "sifive,fu540g", "sifive,fu500"; - model = "sifive,hifive-unleashed-a00"; - - aliases { - serial0 = &L28; - serial1 = &L29; - }; - - chosen { - }; -/* - firmware { - sifive,fsbl = "YYYY-MM-DD"; - }; -*/ - L3: cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <1000000>; - L9: cpu@0 { - clock-frequency = <0>; - compatible = "sifive,rocket0", "riscv"; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <16384>; - next-level-cache = <&L24 &L0>; - reg = <0>; - riscv,isa = "rv64imac"; - sifive,dtim = <&L8>; - sifive,itim = <&L7>; - status = "okay"; - L10: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - L12: cpu@1 { - clock-frequency = <0>; - compatible = "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - next-level-cache = <&L24 &L0>; - reg = <1>; - riscv,isa = "rv64imafdc"; - sifive,itim = <&L11>; - status = "okay"; - tlb-split; - L13: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - L15: cpu@2 { - clock-frequency = <0>; - compatible = "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - next-level-cache = <&L24 &L0>; - reg = <2>; - riscv,isa = "rv64imafdc"; - sifive,itim = <&L14>; - status = "okay"; - tlb-split; - L16: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - L18: cpu@3 { - clock-frequency = <0>; - compatible = "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - next-level-cache = <&L24 &L0>; - reg = <3>; - riscv,isa = "rv64imafdc"; - sifive,itim = <&L17>; - status = "okay"; - tlb-split; - L19: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - L21: cpu@4 { - clock-frequency = <0>; - compatible = "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - next-level-cache = <&L24 &L0>; - reg = <4>; - riscv,isa = "rv64imafdc"; - sifive,itim = <&L20>; - status = "okay"; - tlb-split; - L22: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - }; - L36: memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x2 0x00000000>; - }; - L2: soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus"; - ranges; - refclk: refclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <33333333>; - clock-output-names = "xtal"; - }; - prci: prci@10000000 { - /* compatible = "sifive,ux00prci0"; */ - compatible = "sifive,aloeprci0"; - reg = <0x0 0x10000000 0x0 0x1000>; - reg-names = "control"; - clocks = <&refclk>; - #clock-cells = <1>; - }; - tlclk: tlclk { - compatible = "fixed-factor-clock"; - clocks = <&prci 0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - L51: cadence-gemgxl-mgmt@100a0000 { - compatible = "sifive,cadencegemgxlmgmt0"; - reg = <0x0 0x100a0000 0x0 0x1000>; - reg-names = "control"; - #clock-cells = <0>; - }; - L35: bus-blocker@100b8000 { - compatible = "sifive,bus-blocker0"; - reg = <0x0 0x100b8000 0x0 0x1000>; - reg-names = "control"; - }; - L0: cache-controller@2010000 { - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <2048>; - cache-size = <2097152>; - cache-unified; - compatible = "sifive,ccache0", "cache"; - interrupt-parent = <&L4>; - interrupts = <1 2 3>; - next-level-cache = <&L25 &L40 &L36>; - reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>; - reg-names = "control", "sideband"; - }; - L33: cadence-ddr-mgmt@100c0000 { - compatible = "sifive,cadenceddrmgmt0"; - reg = <0x0 0x100c0000 0x0 0x1000>; - reg-names = "control"; - }; - L40: chiplink@40000000 { - #address-cells = <2>; - #size-cells = <2>; - compatible = "sifive,chiplink", "simple-bus"; - ranges = <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000 0x30 0x0 0x30 0x0 0x10 0x0 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000 0x20 0x0 0x20 0x0 0x10 0x0>; - }; - L5: clint@2000000 { - compatible = "riscv,clint0"; - interrupts-extended = <&L10 3 &L10 7 &L13 3 &L13 7 &L16 3 &L16 7 &L19 3 &L19 7 &L22 3 &L22 7>; - reg = <0x0 0x2000000 0x0 0x10000>; - reg-names = "control"; - }; - L6: debug-controller@0 { - compatible = "sifive,debug-013", "riscv,debug-013"; - interrupts-extended = <&L10 65535 &L13 65535 &L16 65535 &L19 65535 &L22 65535>; - reg = <0x0 0x0 0x0 0x1000>; - reg-names = "control"; - }; - L32: dma@3000000 { - #dma-cells = <1>; - compatible = "riscv,dma0"; - dma-channels = <4>; - dma-requests = <0>; - interrupt-parent = <&L4>; - interrupts = <23 24 25 26 27 28 29 30>; - reg = <0x0 0x3000000 0x0 0x100000>; - reg-names = "control"; - riscv,dma-pools = <1>; - }; - L8: dtim@1000000 { - compatible = "sifive,dtim0"; - reg = <0x0 0x1000000 0x0 0x2000>; - reg-names = "mem"; - }; - L44: ememoryotp@10070000 { - compatible = "sifive,ememoryotp0"; - reg = <0x0 0x10070000 0x0 0x1000>; - reg-names = "control"; - }; - L24: error-device@18000000 { - compatible = "sifive,error0"; - reg = <0x0 0x18000000 0x0 0x8000000>; - reg-names = "mem"; - }; - L52: ethernet@10090000 { - compatible = "cdns,macb"; - interrupt-parent = <&L4>; - interrupts = <53>; - reg = <0x0 0x10090000 0x0 0x2000>; - reg-names = "control"; - - local-mac-address = [00 00 00 00 00 00]; - phy-mode = "gmii"; - clock-names = "pclk", "hclk", "tx_clk"; - clocks = <&prci 1>, <&prci 1>, <&L51>; - - #address-cells = <1>; - #size-cells = <0>; - phy1: ethernet-phy@0 { - reg = <0>; - reset-gpios = <&L31 12 1>; - }; - }; - L31: gpio@10060000 { - compatible = "sifive,gpio0"; - interrupt-parent = <&L4>; - interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>; - reg = <0x0 0x10060000 0x0 0x1000>; - reg-names = "control"; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - gpio-restart { - compatible = "gpio-restart"; - gpios = <&L31 10 1>; - }; - L47: i2c@10030000 { - compatible = "sifive,i2c0", "opencores,i2c-ocores"; - reg = <0x0 0x10030000 0x0 0x1000>; - reg-names = "control"; - clocks = <&tlclk>; - - reg-shift = <2>; - reg-io-width = <1>; - - #address-cells = <1>; - #size-cells = <0>; - - /* On pre-production boards only */ -/* - ina233-vdd_soc_core@40 { - compatible = "ti,pmbus"; - reg = <0x40>; - }; - ina233-vdd_ddr_soc@44 { - compatible = "ti,pmbus"; - reg = <0x44>; - }; - ina233-vdd_ddr_mem@45 { - compatible = "ti,pmbus"; - reg = <0x45>; - }; - ina233-vdd_corepll@47 { - compatible = "ti,pmbus"; - reg = <0x47>; - }; - ina233-vdd_otp@4a { - compatible = "ti,pmbus"; - reg = <0x4a>; - }; - ina233-vdd_io@4b { - compatible = "ti,pmbus"; - reg = <0x4b>; - }; - ina233-vdd_ddrpll@48 { - compatible = "ti,pmbus"; - reg = <0x48>; - }; - ina233-avdd_ddrpll@49 { - compatible = "ti,pmbus"; - reg = <0x49>; - }; - ina233-vdd_givdd@4c { - compatible = "ti,pmbus"; - reg = <0x4c>; - }; - ina233vdd_gemgxlpll@4d { - compatible = "ti,pmbus"; - reg = <0x4d>; - }; -*/ - /* On the tester board */ -/* - m24c02 { - compatible = "st,24c02"; - reg = <0x51>; - }; -*/ - }; - L4: interrupt-controller@c000000 { - #interrupt-cells = <1>; - compatible = "riscv,plic0"; - interrupt-controller; - interrupts-extended = <&L10 11 &L13 11 &L13 9 &L16 11 &L16 9 &L19 11 &L19 9 &L22 11 &L22 9>; - reg = <0x0 0xc000000 0x0 0x4000000>; - reg-names = "control"; - riscv,max-priority = <7>; - riscv,ndev = <53>; - }; - L7: itim@1800000 { - compatible = "sifive,itim0"; - reg = <0x0 0x1800000 0x0 0x4000>; - reg-names = "mem"; - }; - L11: itim@1808000 { - compatible = "sifive,itim0"; - reg = <0x0 0x1808000 0x0 0x8000>; - reg-names = "mem"; - }; - L14: itim@1810000 { - compatible = "sifive,itim0"; - reg = <0x0 0x1810000 0x0 0x8000>; - reg-names = "mem"; - }; - L17: itim@1818000 { - compatible = "sifive,itim0"; - reg = <0x0 0x1818000 0x0 0x8000>; - reg-names = "mem"; - }; - L20: itim@1820000 { - compatible = "sifive,itim0"; - reg = <0x0 0x1820000 0x0 0x8000>; - reg-names = "mem"; - }; - L37: memory-controller@100b0000 { - /* compatible = "sifive,ux00ddr0"; */ - compatible = "sifive,aloeddr0"; - interrupt-parent = <&L4>; - interrupts = <31>; - reg = <0x0 0x100b0000 0x0 0x4000>; - reg-names = "control"; - }; - pci@2000000000 { - #address-cells = <3>; - #interrupt-cells = <1>; - #size-cells = <2>; - compatible = "xlnx,axi-pcie-host-1.00.a"; - device_type = "pci"; - interrupt-map = <0 0 0 1 &xil_pcie_intc 1 0 0 0 2 &xil_pcie_intc 2 0 0 0 3 &xil_pcie_intc 3 0 0 0 4 &xil_pcie_intc 4>; - interrupt-map-mask = <0 0 0 7>; - interrupt-parent = <&L4>; - interrupts = <32>; - ranges = <0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>; - reg = <0x020 0x0 0x0 0x4000000>; - reg-names = "control"; - xil_pcie_intc: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; -/* - pci@2030000000 { - #address-cells = <3>; - #interrupt-cells = <1>; - #size-cells = <2>; - compatible = "ms-pf,axi-pcie-host"; - device_type = "pci"; - bus-range = <0x01 0x7f>; - interrupt-map = <0 0 0 1 &ms_pcie_intc 1 0 0 0 2 &ms_pcie_intc 2 0 0 0 3 &ms_pcie_intc 3 0 0 0 4 &ms_pcie_intc 4>; - interrupt-map-mask = <0 0 0 7>; - interrupt-parent = <&L4>; - interrupts = <32>; - ranges = <0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>; - reg = <0x20 0x30000000 0x0 0x4000000 0x20 0x0 0x0 0x100000>; - reg-names = "control", "apb"; - ms_pcie_intc: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; -*/ - L53: pinctrl@10080000 { - compatible = "sifive,pinctrl0"; - reg = <0x0 0x10080000 0x0 0x1000>; - reg-names = "control"; - }; - L45: pwm@10020000 { - compatible = "sifive,pwm0"; - interrupt-parent = <&L4>; - interrupts = <42 43 44 45>; - reg = <0x0 0x10020000 0x0 0x1000>; - reg-names = "control"; - clocks = <&tlclk>; - sifive,approx-period = <1000000>; - #pwm-cells = <2>; - }; - L46: pwm@10021000 { - compatible = "sifive,pwm0"; - interrupt-parent = <&L4>; - interrupts = <46 47 48 49>; - reg = <0x0 0x10021000 0x0 0x1000>; - reg-names = "control"; - clocks = <&tlclk>; - sifive,approx-period = <1000000>; - #pwm-cells = <2>; - }; - pwmleds { - compatible = "pwm-leds"; - heartbeat { - pwms = <&L45 0 0>; - max-brightness = <255>; - linux,default-trigger = "heartbeat"; - }; - mtd { - pwms = <&L45 1 0>; - max-brightness = <255>; - linux,default-trigger = "mtd"; - }; - netdev { - pwms = <&L45 2 0>; - max-brightness = <255>; - linux,default-trigger = "netdev"; - }; - panic { - pwms = <&L45 3 0>; - max-brightness = <255>; - linux,default-trigger = "panic"; - }; - /* These LEDs are on the tester board */ -/* - testled { - pwms = <&L46 0 0>; - max-brightness = <255>; - }; - green { - pwms = <&L46 1 0>; - max-brightness = <255>; - }; - red { - pwms = <&L46 2 0>; - max-brightness = <255>; - }; - blue { - pwms = <&L46 3 0>; - max-brightness = <255>; - }; -*/ - }; - L27: rom@1000 { - compatible = "sifive,modeselect0"; - reg = <0x0 0x1000 0x0 0x1000>; - reg-names = "mem"; - }; - L26: rom@10000 { - compatible = "sifive,maskrom0"; - reg = <0x0 0x10000 0x0 0x8000>; - reg-names = "mem"; - }; - L25: rom@a000000 { - compatible = "ucbbar,cacheable-zero0"; - reg = <0x0 0xa000000 0x0 0x2000000>; - reg-names = "mem"; - }; - L28: serial@10010000 { - compatible = "sifive,uart0"; - interrupt-parent = <&L4>; - interrupts = <4>; - reg = <0x0 0x10010000 0x0 0x1000>; - reg-names = "control"; - clocks = <&tlclk>; - }; - L29: serial@10011000 { - compatible = "sifive,uart0"; - interrupt-parent = <&L4>; - interrupts = <5>; - reg = <0x0 0x10011000 0x0 0x1000>; - reg-names = "control"; - clocks = <&tlclk>; - }; - L49: spi@10040000 { - compatible = "sifive,spi0"; - interrupt-parent = <&L4>; - interrupts = <51>; - reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>; - reg-names = "control", "mem"; - clocks = <&tlclk>; - - #address-cells = <1>; - #size-cells = <0>; - flash@0 { - compatible = "issi,is25wp256d", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; - }; - L50: spi@10041000 { - compatible = "sifive,spi0"; - interrupt-parent = <&L4>; - interrupts = <52>; - reg = <0x0 0x10041000 0x0 0x1000 0x0 0x30000000 0x0 0x10000000>; - reg-names = "control", "mem"; - clocks = <&tlclk>; - - #address-cells = <1>; - #size-cells = <0>; - - /* These flash chips are on the tester board */ -/* - flash@0 { - compatible = "issi,is25wp032", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <25000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; - flash@1 { - compatible = "issi,is25wp032", "jedec,spi-nor"; - reg = <1>; - spi-max-frequency = <25000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; - flash@2 { - compatible = "issi,is25wp032", "jedec,spi-nor"; - reg = <2>; - spi-max-frequency = <25000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; - flash@3 { - compatible = "issi,is25wp032", "jedec,spi-nor"; - reg = <3>; - spi-max-frequency = <25000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -*/ - }; - L30: spi@10050000 { - compatible = "sifive,spi0"; - interrupt-parent = <&L4>; - interrupts = <6>; - reg = <0x0 0x10050000 0x0 0x1000>; - reg-names = "control"; - clocks = <&tlclk>; - - #address-cells = <1>; - #size-cells = <0>; - mmc@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3300 3300>; - disable-wp; - gpios = <&L31 11 1>; - }; - }; - L23: teststatus@4000 { - compatible = "sifive,test0"; - reg = <0x0 0x4000 0x0 0x1000>; - reg-names = "control"; - }; - }; -};
Hello ron minnich, Philipp Hug, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35122
to look at the new patch set (#2).
Change subject: mainboard/sifive/hifive-unleashed: Update devicetree ......................................................................
mainboard/sifive/hifive-unleashed: Update devicetree
With the current devicetree the kernel doesn't provide any serial after serial init. Update the devicetree to resolve this issue.
Tested on HiFive Unleashed.
Change-Id: I4427d34a12902e0eaa2186121a53152b719cadff Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/sifive/hifive-unleashed/Makefile.inc A src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi A src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts D src/mainboard/sifive/hifive-unleashed/hifive-unleashed.dts 4 files changed, 343 insertions(+), 641 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/35122/2
Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35122 )
Change subject: mainboard/sifive/hifive-unleashed: Update devicetree ......................................................................
Patch Set 2: Code-Review+2
Thanks. fu540-c000.dtsi should be moved into the fu540 soc directory when there is more than one mainboard using that SoC.
-
Patrick Rudolph (Code Review) -
Philipp Hug (Code Review)