coreboot-gerrit September 2019

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Change in coreboot[master]: soc/amd/picasso: Update southbridge
by Marshall Dawson (Code Review) 09 Sep '19

09 Sep '19

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33770 ) Change subject: soc/amd/picasso: Update southbridge ...................................................................... Patch Set 14: (2 comments) https://review.coreboot.org/c/coreboot/+/33770/13/src/soc/amd/picasso/inclu… File src/soc/amd/picasso/include/soc/southbridge.h: https://review.coreboot.org/c/coreboot/+/33770/13/src/soc/amd/picasso/inclu… PS13, Line 169: #define GPP_CLK_REQ_MAP_CLK6 (1 << GPP_CLK6_REQ_SHL) > Mask values are overlapping, is it on purpose? […] Good catch. I missed that the fields narrowed. Oh, the newer PPR shows different names now too. https://review.coreboot.org/c/coreboot/+/33770/13/src/soc/amd/picasso/inclu… PS13, Line 229: 0x5b > This sounds strange, normally it's a pair with STATE being the second register... […] You're right. I'm completely tired of the way our AOAC was written, and the BKDG and PPR don't specify them in the same fashion. Redoing it with https://review.coreboot.org/q/Iffc87f39ebe38394a56d41bb0940e9701fd05db9 -- To view, visit https://review.coreboot.org/c/coreboot/+/33770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69dfc4a875006639aa330385680d150331840e40 Gerrit-Change-Number: 33770 Gerrit-PatchSet: 14 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 09 Sep 2019 01:08:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Update southbridge
by Marshall Dawson (Code Review) 09 Sep '19

09 Sep '19

Hello Richard Spiegel, build bot (Jenkins), Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/33770 to look at the new patch set (#14). Change subject: soc/amd/picasso: Update southbridge ...................................................................... soc/amd/picasso: Update southbridge Picasso's FCH has many similarities to Stoney Ridge, so few changes are necessary. The most notable changes are: * Update the index values for the C00/C01 interrupt routing * FORCE_STPCLK_RETRY is not present * PCIB is not defined * FCH MISC Registers 0xfed80e00 numbering has changed * C-state base moves from PM register to MSR Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I69dfc4a875006639aa330385680d150331840e40 --- M src/soc/amd/picasso/include/soc/amd_pci_int_defs.h M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/smihandler.c M src/soc/amd/picasso/southbridge.c 5 files changed, 104 insertions(+), 166 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/33770/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/33770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69dfc4a875006639aa330385680d150331840e40 Gerrit-Change-Number: 33770 Gerrit-PatchSet: 14 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/picasso: Create a hybrid romstage to begin in DRAM
by Marshall Dawson (Code Review) 09 Sep '19

09 Sep '19

Hello Edward O'Callaghan, Julius Werner, Richard Spiegel, build bot (Jenkins), Furquan Shaikh, Martin Roth, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/33759 to look at the new patch set (#14). Change subject: soc/amd/picasso: Create a hybrid romstage to begin in DRAM ...................................................................... soc/amd/picasso: Create a hybrid romstage to begin in DRAM Add the support files to begin execution in romstage and located in DRAM. Details for this implementation are found in Documentation/amd/picasso/family17.md. Combine steps typically found in bootblock, containing the reset vector and protected mode enable, with the parts of romstage that enable the console and cbmem. Duplicate the ROMSTAGE_ADDR symbol into Kconfig and give it a safe default value in DRAM. Define EARLYRAM values for stack and early storage prior to cbmem. (A subsequent patch to add an FSP driver will rely on the storage.) Remove all postcar support. This implementation assumes only a BSP will run the main romstage code. A subsequent change will add restrictions on APs, as AGESA is put in place to release them from reset. Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/early_stack.S M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/include/soc/romstage.h M src/soc/amd/picasso/romstage.c 6 files changed, 166 insertions(+), 93 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/33759/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/33759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976 Gerrit-Change-Number: 33759 Gerrit-PatchSet: 14 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: [WIP] ssdtgen for PNP devices
by Patrick Rudolph (Code Review) 08 Sep '19

08 Sep '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33033 Change subject: [WIP] ssdtgen for PNP devices ...................................................................... [WIP] ssdtgen for PNP devices Automatically create ACPI code for PNP devices. TODO: Add HID to devicetree. Change-Id: I2716ae0580d68e5d4fcc484cb1648a2cdc1f4ca0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A src/superio/common/chip.h A src/superio/common/ssdt.c A src/superio/common/ssdt.h 3 files changed, 386 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/33033/1 diff --git a/src/superio/common/chip.h b/src/superio/common/chip.h new file mode 100644 index 0000000..2d75c0f --- /dev/null +++ b/src/superio/common/chip.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SUPERIO_COMMON_CHIP_H__ +#define __SUPERIO_COMMON_CHIP_H__ + +struct common_superio_ldn_config { + const char *acpi_name; + const char *dos_device_name; + const char *acpi_hid; +}; + +#endif /* __SUPERIO_COMMON_CHIP_H__ */ diff --git a/src/superio/common/ssdt.c b/src/superio/common/ssdt.c new file mode 100644 index 0000000..0e2c59f --- /dev/null +++ b/src/superio/common/ssdt.c @@ -0,0 +1,334 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <superio/common/chip.h> +#include <superio/common/ssdt.h> + +#include <device/device.h> +#include <device/pnp.h> +#include <arch/acpigen.h> +#include <device/pnp_def.h> +#include <console/console.h> + +#define NUM_IO 4 +#define NUM_IRQ 2 + +struct superio_dev { + const char *acpi_hid; + u16 io_base[NUM_IO]; + u8 irq[NUM_IRQ]; +}; + +static const struct superio_dev superio_devs[] = { + {"PNP0700", {0x3f0, 0x3f2, 0x3f7}, {6, }}, + {"PNP0303", {60, 64, }, {1, }}, + {"PNP0F03", {60, 64, }, {12, }}, + {"PNP0501", {0x3f8, 0x2f8, 0x3e8, 0x2e8}, {4, 3}}, + {"PNP0400", {0x378, }, {7, }}, +}; + +static const u8 io_idx[NUM_IO] = {PNP_IDX_IO0, PNP_IDX_IO1, PNP_IDX_IO2, + PNP_IDX_IO3}; +static const u8 irq_idx[NUM_IRQ] = {PNP_IDX_IRQ0, PNP_IDX_IRQ1}; + + +static void superio_base_fill_ssdt_generator(struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + const char *name = acpi_device_name(dev); + + if (!scope || !name) { + printk(BIOS_ERR, "%s: Missing ACPI path/scope\n", dev_path(dev)); + return; + } + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(name); + + printk(BIOS_DEBUG, "%s.%s: %s\n", scope, name, dev_path(dev)); + + acpigen_write_name_string("_HID", "PNP0C02"); + acpigen_write_name_string("_DDN", dev_name(dev)); + + /* OperationRegion("IOID", SYSTEMIO, port, 2) */ + struct opregion opreg = OPREGION("IOID", SYSTEMIO, + dev->path.pnp.port, 2); + acpigen_write_opregion(&opreg); + + struct fieldlist l[] = { + FIELDLIST_OFFSET(0), + FIELDLIST_NAMESTR("INDX", 8), + FIELDLIST_NAMESTR("DATA", 8), + }; + + /* Field (IOID, AnyAcc, NoLock, Preserve) + * { + * Offset (0), + * INDX, 8, + * DATA, 8, + * } */ + acpigen_write_field(opreg.name, l, ARRAY_SIZE(l), FIELD_BYTEACC | + FIELD_NOLOCK | FIELD_PRESERVE); + + struct fieldlist i[] = { + FIELDLIST_OFFSET(0x07), + FIELDLIST_NAMESTR("LDN", 8), + FIELDLIST_OFFSET(0x21), + FIELDLIST_NAMESTR("SCF1", 8), + FIELDLIST_NAMESTR("SCF2", 8), + FIELDLIST_NAMESTR("SCF3", 8), + FIELDLIST_NAMESTR("SCF4", 8), + FIELDLIST_NAMESTR("SCF5", 8), + FIELDLIST_NAMESTR("SCF6", 8), + FIELDLIST_NAMESTR("SCF7", 8), + FIELDLIST_OFFSET(0x29), + FIELDLIST_NAMESTR("CKCF", 8), + FIELDLIST_OFFSET(0x2F), + FIELDLIST_NAMESTR("SCFF", 8), + FIELDLIST_NAMESTR("ACTR", 8), + FIELDLIST_OFFSET(0x60), + FIELDLIST_NAMESTR("IOAH", 8), + FIELDLIST_NAMESTR("IOAL", 8), + FIELDLIST_NAMESTR("IOH2", 8), + FIELDLIST_NAMESTR("IOL2", 8), + FIELDLIST_OFFSET(0x70), + FIELDLIST_NAMESTR("INTR", 4), + FIELDLIST_NAMESTR("INTT", 4), + FIELDLIST_OFFSET (0x74), + FIELDLIST_NAMESTR("DMCH", 8), + FIELDLIST_OFFSET(0xE0), + FIELDLIST_NAMESTR("RGE0", 8), + FIELDLIST_NAMESTR("RGE1", 8), + FIELDLIST_NAMESTR("RGE2", 8), + FIELDLIST_NAMESTR("RGE3", 8), + FIELDLIST_NAMESTR("RGE4", 8), + FIELDLIST_NAMESTR("RGE5", 8), + FIELDLIST_NAMESTR("RGE6", 8), + FIELDLIST_NAMESTR("RGE7", 8), + FIELDLIST_NAMESTR("RGE8", 8), + FIELDLIST_NAMESTR("RGE9", 8), + FIELDLIST_NAMESTR("RGEA", 8), + FIELDLIST_OFFSET(0xF0), + FIELDLIST_NAMESTR("OPT0", 8), + FIELDLIST_NAMESTR("OPT1", 8), + FIELDLIST_NAMESTR("OPT2", 8), + FIELDLIST_NAMESTR("OPT3", 8), + FIELDLIST_NAMESTR("OPT4", 8), + FIELDLIST_NAMESTR("OPT5", 8), + FIELDLIST_NAMESTR("OPT6", 8), + FIELDLIST_NAMESTR("OPT7", 8), + FIELDLIST_NAMESTR("OPT8", 8), + FIELDLIST_NAMESTR("OPT9", 8), + }; + + acpigen_write_indexfield("INDX", "DATA", i, ARRAY_SIZE(i), + FIELD_BYTEACC | FIELD_NOLOCK | FIELD_PRESERVE); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *superio_guess_hid(struct device *dev) +{ + for (size_t i = 0; i < ARRAY_SIZE(io_idx); i++) { + struct resource *res = probe_resource(dev, io_idx[i]); + if (!res || !res->base) + continue; + + for (size_t j = 0; j < ARRAY_SIZE(superio_devs); j++) { + for (size_t k = 0; k < NUM_IO; k++) { + if (!superio_devs[j].io_base[k]) + continue; + if (superio_devs[j].io_base[k] == res->base) + return superio_devs[j].acpi_hid; + } + } + } + for (size_t i = 0; i < ARRAY_SIZE(irq_idx); i++) { + struct resource *res = probe_resource(dev, irq_idx[i]); + if (!res || !res->size) + continue; + for (size_t j = 0; j < ARRAY_SIZE(superio_devs); j++) { + for (size_t k = 0; k < NUM_IRQ; k++) { + if (!superio_devs[j].irq[k]) + continue; + if (superio_devs[j].irq[k] == res->base) + return superio_devs[j].acpi_hid; + } + } + } + return NULL; +} + +static int ldn_resource_cnt(struct device *dev) +{ + int cnt = 0; + for (size_t i = 0; i < ARRAY_SIZE(io_idx); i++) { + struct resource *res = probe_resource(dev, io_idx[i]); + if (!res || !res->base) + continue; + cnt++; + } + for (size_t i = 0; i < NUM_IRQ; i++) { + struct resource *res = probe_resource(dev, irq_idx[i]); + if (!res || !res->size) + continue; + cnt++; + } + return cnt; +} + +/* Add IO and IRQ resources for _CRS or _PRS */ +static void ldn_gen_resources(struct device *dev) +{ + for (size_t i = 0; i < ARRAY_SIZE(io_idx); i++) { + struct resource *res = probe_resource(dev, io_idx[i]); + if (!res || !res->base) + continue; + resource_t base = res->base; + resource_t size = res->size; + while (size > 0) { + resource_t sz = size > 255 ? 255 : size; + acpigen_write_io16(base, base, 0, sz, 1); + size -= sz; + base += sz; + } + } + for (size_t i = 0; i < NUM_IRQ; i++) { + struct resource *res = probe_resource(dev, irq_idx[i]); + if (!res || !res->size) + continue; + acpigen_write_irq(res->base); + } +} + +/* Add resource base and size for additional SuperIO code */ +static void ldn_gen_resources_use(struct device *dev) +{ + char name[5]; + for (size_t i = 0; i < ARRAY_SIZE(io_idx); i++) { + struct resource *res = probe_resource(dev, io_idx[i]); + if (!res || !res->base || !res->size) + continue; + + snprintf(name, sizeof(name), "IO%XB", i); + name[4] = '\0'; + acpigen_write_name_integer(name, res->base); + + snprintf(name, sizeof(name), "IO%XS", i); + name[4] = '\0'; + acpigen_write_name_integer(name, res->size); + } +} + +static const char *ldn_acpi_name(const struct device *dev) +{ + u8 ldn = dev->path.pnp.device & 0xff; + u8 vldn = (dev->path.pnp.device >> 8) & 0x7; + static char name[5]; + + if (!vldn) + snprintf(name, sizeof(name), "LD%02X", ldn); + else + snprintf(name, sizeof(name), "VLD%X", vldn); + + name[4] = '\0'; + + return name; +} + + +void superio_common_fill_ssdt_generator(struct device *dev) +{ + struct common_superio_ldn_config *config = dev->chip_info; + const char *scope = acpi_device_path(dev); + const char *name = ldn_acpi_name(dev); + const char *hid = NULL; + const u8 ldn = dev->path.pnp.device & 0xff; + const u8 vldn = (dev->path.pnp.device >> 8) & 0x7; + bool has_resources; + + if (!scope || !name) { + printk(BIOS_ERR, "%s: Missing ACPI path/scope\n", dev_path(dev)); + return; + } + if (vldn) { + printk(BIOS_DEBUG, "%s: Ignoring virtual LDN\n", dev_path(dev)); + return; + } + + if (ldn == 0) + superio_base_fill_ssdt_generator(dev); + + printk(BIOS_DEBUG, "%s.%s: %s\n", scope, name, dev_path(dev)); + + /* Scope */ + acpigen_write_scope(scope); + + /* Device */ + acpigen_write_device(name); + + if (config && config->dos_device_name) + acpigen_write_name_string("_DDN", config->dos_device_name); + + acpigen_write_name_byte("_UID", 0); + acpigen_write_name_byte("LDN", ldn); + + acpigen_write_STA(dev->enabled ? 0xf : 0); + + if (!dev->enabled) { + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + return; + } + + has_resources = ldn_resource_cnt(dev); + + /* Resources - _CRS */ + if (has_resources) { + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + ldn_gen_resources(dev); + acpigen_write_resourcetemplate_footer(); + + /* Resources - _PRS */ + acpigen_write_name("_PRS"); + acpigen_write_resourcetemplate_header(); + ldn_gen_resources(dev); + acpigen_write_resourcetemplate_footer(); + + /* Resources base and size for 3rd party ACPI code */ + ldn_gen_resources_use(dev); + } + + if (config && config->acpi_hid) { + hid = config->acpi_hid; + } else { + printk(BIOS_WARNING, "%s: No HID set in devicetree\n", + dev_path(dev)); + + hid = superio_guess_hid(dev); + } + + if (hid) + acpigen_write_name_string("_HID", hid); + else + acpigen_write_name_string("_HID", "PNP0C02"); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} diff --git a/src/superio/common/ssdt.h b/src/superio/common/ssdt.h new file mode 100644 index 0000000..4d4e4b1 --- /dev/null +++ b/src/superio/common/ssdt.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 9elements Agency GmbH <patrick.rudolph(a)9elements.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SUPERIO_COMMON_SSDT_H__ +#define __SUPERIO_COMMON_SSDT_H__ + +#include <device/device.h> + +void superio_common_fill_ssdt_generator(struct device *dev); +const char *superio_common_acpi_name(const struct device *dev); +void superio_set_base_dev_ops(struct device *dev); + +#endif /* __SUPERIO_COMMON_SSDT_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2716ae0580d68e5d4fcc484cb1648a2cdc1f4ca0 Gerrit-Change-Number: 33033 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP For squash with I9c084ff]: Implement RESET_VECTOR_IN_RAM
by Marshall Dawson (Code Review) 07 Sep '19

07 Sep '19

Marshall Dawson has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35264 ) Change subject: [WIP For squash with I9c084ff]: Implement RESET_VECTOR_IN_RAM ...................................................................... Abandoned > Marshall; squashed as requested, using my old Change-Id. I will push update after rebasing and/or merging some related work. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/35264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If272118dd80e559f8fe45e24e10fa28c5b7bd1f9 Gerrit-Change-Number: 35264 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: security/tpm: Use correct hash digest lengths
by Jacob Garber (Code Review) 07 Sep '19

07 Sep '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35287 ) Change subject: security/tpm: Use correct hash digest lengths ...................................................................... security/tpm: Use correct hash digest lengths TPMU_HA is a union of all the different hash digests, and so sizeof(TPMU_HA) evaluates to 64 (the size of the largest one). This will lead to out-of-bounds writes when copying smaller digests, so use the specific digest size for each algorithm. Change-Id: Ic9101f157d5a19836b200ecd99f060de552498d2 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 14049{49,50,51,52,53,54,55,56,57,58,60,61,62} --- M src/security/tpm/tspi/tspi.c M src/security/tpm/tss/tcg-2.0/tss.c 2 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/35287/1 diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 4cf3711..e64e04f 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -219,12 +219,12 @@ case VB2_HASH_SHA1: tpml_digests.digests[0].hashAlg = TPM_ALG_SHA1; memcpy(tpml_digests.digests[0].digest.sha1, - digest, sizeof(TPMU_HA)); + digest, SHA1_DIGEST_SIZE); break; case VB2_HASH_SHA256: tpml_digests.digests[0].hashAlg = TPM_ALG_SHA256; memcpy(tpml_digests.digests[0].digest.sha256, - digest, sizeof(TPMU_HA)); + digest, SHA256_DIGEST_SIZE); break; default: return TPM_E_IOERROR; diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index fab334f..d9deba5 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -148,27 +148,27 @@ case TPM_ALG_SHA1: memcpy(pcr_ext_cmd.digests.digests[i].digest.sha1, tpml_digests->digests[i].digest.sha1, - sizeof(TPMU_HA)); + SHA1_DIGEST_SIZE); break; case TPM_ALG_SHA256: memcpy(pcr_ext_cmd.digests.digests[i].digest.sha256, tpml_digests->digests[i].digest.sha256, - sizeof(TPMU_HA)); + SHA256_DIGEST_SIZE); break; case TPM_ALG_SHA384: memcpy(pcr_ext_cmd.digests.digests[i].digest.sha384, tpml_digests->digests[i].digest.sha384, - sizeof(TPMU_HA)); + SHA384_DIGEST_SIZE); break; case TPM_ALG_SHA512: memcpy(pcr_ext_cmd.digests.digests[i].digest.sha512, tpml_digests->digests[i].digest.sha512, - sizeof(TPMU_HA)); + SHA512_DIGEST_SIZE); break; case TPM_ALG_SM3_256: memcpy(pcr_ext_cmd.digests.digests[i].digest.sm3_256, tpml_digests->digests[i].digest.sm3_256, - sizeof(TPMU_HA)); + SM3_256_DIGEST_SIZE); break; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/35287 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9101f157d5a19836b200ecd99f060de552498d2 Gerrit-Change-Number: 35287 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: Build fmap from intel descriptor
by Michael Niewöhner (Code Review) 07 Sep '19

07 Sep '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35281 ) Change subject: Build fmap from intel descriptor ...................................................................... Build fmap from intel descriptor Currently coreboot creates a non-working image when ifd, me and/or other reagions are provided because the bios region offset calculation does not take them into account. When an ifd is provided we can build the fmap by extracting the offsets from it to create working images for such systems. Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Change-Id: Ief153b08788f1f0484e83418e8308261301ebc44 --- M Makefile.inc M util/cbfstool/default-x86.fmd 2 files changed, 72 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/35281/1 diff --git a/Makefile.inc b/Makefile.inc index 3c3088d..57f4a59 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -151,6 +151,7 @@ tolower=$(shell echo '$1' | tr '[:upper:]' '[:lower:]') toupper=$(shell echo '$1' | tr '[:lower:]' '[:upper:]') ws_to_under=$(shell echo '$1' | tr ' \t' '_') +cut = $(word $3,$(subst $2, ,$1)) ####################################################################### # Helper functions for ramstage postprocess @@ -869,12 +870,75 @@ # entire flash FMAP_ROM_ADDR := $(call int-subtract, 0x100000000 $(CONFIG_ROM_SIZE)) FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE) + +# +# Get regions from ifd +# +FMAP_IFD_ENTRY := +FMAP_ME_ENTRY := +FMAP_EC_ENTRY := +FMAP_GBE_ENTRY := +ifeq ($(CONFIG_HAVE_IFD_BIN),y) + +# IFD region +ifneq ($(CONFIG_IFD_BIN_PATH),) +FMAP_IFD_REGION := $(shell $(IFDTOOL) -f /dev/stdout $(CONFIG_IFD_BIN_PATH) | grep 'fd$$' | sed 's/ .+$$//') +FMAP_IFD_BASE := 0x$(call cut,$(FMAP_IFD_REGION),:,1) +FMAP_IFD_END := 0x$(call cut,$(FMAP_IFD_REGION),:,2) +FMAP_IFD_SIZE := $(call int-subtract, $(call int-add, $(FMAP_IFD_END) 1) $(FMAP_IFD_BASE)) +FMAP_IFD_ENTRY := IFD@$(FMAP_IFD_BASE) $(FMAP_IFD_SIZE) +endif + +# ME region +ifeq ($(CONFIG_HAVE_ME_BIN),y) +ifneq ($(CONFIG_ME_BIN_PATH),) +FMAP_ME_REGION := $(shell $(IFDTOOL) -f /dev/stdout $(CONFIG_IFD_BIN_PATH) | grep 'me$$' | sed 's/ .+$$//') +FMAP_ME_BASE := 0x$(call cut,$(FMAP_ME_REGION),:,1) +FMAP_ME_END := 0x$(call cut,$(FMAP_ME_REGION),:,2) +FMAP_ME_SIZE := $(call int-subtract, $(call int-add, $(FMAP_ME_END) 1) $(FMAP_ME_BASE)) +FMAP_ME_ENTRY := ME@$(FMAP_ME_BASE) $(FMAP_ME_SIZE) +endif # ifneq ($(CONFIG_ME_BIN_PATH),) +endif # ifeq ($(CONFIG_HAVE_ME_BIN),y) + +# EC region +ifeq ($(CONFIG_HAVE_EC_BIN),y) +ifneq ($(CONFIG_EC_BIN_PATH),) +FMAP_EC_REGION := $(shell $(IFDTOOL) -f /dev/stdout $(CONFIG_IFD_BIN_PATH) | grep 'ec$$' | sed 's/ .+$$//') +FMAP_EC_BASE := 0x$(call cut,$(FMAP_EC_REGION),:,1) +FMAP_EC_END := 0x$(call cut,$(FMAP_EC_REGION),:,2) +FMAP_EC_SIZE := $(call int-subtract, $(call int-add, $(FMAP_EC_END) 1) $(FMAP_EC_BASE)) +FMAP_EC_ENTRY := EC@$(FMAP_EC_BASE) $(FMAP_EC_SIZE) +endif # ifneq ($(CONFIG_EC_BIN_PATH),) +endif # ifeq ($(CONFIG_HAVE_EC_BIN),y) + +# GBE region +ifeq ($(CONFIG_HAVE_GBE_BIN),y) +ifneq ($(CONFIG_GBE_BIN_PATH),) +FMAP_GBE_REGION := $(shell $(IFDTOOL) -f /dev/stdout $(CONFIG_IFD_BIN_PATH) | grep 'gbe$$' | sed 's/ .+$$//') +FMAP_GBE_BASE := 0x$(call cut,$(FMAP_GBE_REGION),:,1) +FMAP_GBE_END := 0x$(call cut,$(FMAP_GBE_REGION),:,2) +FMAP_GBE_SIZE := $(call int-subtract, $(call int-add, $(FMAP_GBE_END) 1) $(FMAP_GBE_BASE)) +FMAP_GBE_ENTRY := GBE@$(FMAP_GBE_BASE) $(FMAP_GBE_SIZE) +endif # ifneq ($(CONFIG_GBE_BIN_PATH),) +endif # ifeq ($(CONFIG_HAVE_GBE_BIN),y) + +# BIOS region +FMAP_BIOS_REGION := $(shell $(IFDTOOL) -f /dev/stdout $(CONFIG_IFD_BIN_PATH) | grep 'bios$$' | sed 's/ .+$$//') +FMAP_BIOS_BASE := 0x$(call cut,$(FMAP_BIOS_REGION),:,1) +FMAP_BIOS_END := 0x$(call cut,$(FMAP_BIOS_REGION),:,2) +FMAP_BIOS_SIZE := $(call int-subtract, $(call int-add, $(FMAP_BIOS_END) 1) $(FMAP_BIOS_BASE)) + +else # ifeq ($(CONFIG_HAVE_IFD_BIN),y) + +# BIOS region # entire "BIOS" region (everything directly of concern to the host system) # relative to ROM_BASE FMAP_BIOS_BASE := $(call int-align, $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)), 0x10000) FMAP_BIOS_SIZE := $(call int-align-down, $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f), 0x10000) # position and size of flashmap, relative to BIOS_BASE +endif # ifeq ($(CONFIG_HAVE_IFD_BIN),y) + # # X86 CONSOLE FMAP region # @@ -992,6 +1056,10 @@ $(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) $(obj)/config.h sed -e "s,##ROM_BASE##,$(FMAP_ROM_ADDR)," \ -e "s,##ROM_SIZE##,$(FMAP_ROM_SIZE)," \ + -e "s,##IFD_ENTRY##,$(FMAP_IFD_ENTRY)," \ + -e "s,##ME_ENTRY##,$(FMAP_ME_ENTRY)," \ + -e "s,##EC_ENTRY##,$(FMAP_EC_ENTRY)," \ + -e "s,##GBE_ENTRY##,$(FMAP_GBE_ENTRY)," \ -e "s,##BIOS_BASE##,$(FMAP_BIOS_BASE)," \ -e "s,##BIOS_SIZE##,$(FMAP_BIOS_SIZE)," \ -e "s,##FMAP_BASE##,$(FMAP_FMAP_BASE)," \ diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd index f0143e9..7554582 100644 --- a/util/cbfstool/default-x86.fmd +++ b/util/cbfstool/default-x86.fmd @@ -8,6 +8,10 @@ # +-------------+ <-- 4GB / end of flash FLASH@##ROM_BASE## ##ROM_SIZE## { + ##IFD_ENTRY## + ##ME_ENTRY## + ##EC_ENTRY## + ##GBE_ENTRY## BIOS@##BIOS_BASE## ##BIOS_SIZE## { ##CONSOLE_ENTRY## ##MRC_CACHE_ENTRY## -- To view, visit https://review.coreboot.org/c/coreboot/+/35281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief153b08788f1f0484e83418e8308261301ebc44 Gerrit-Change-Number: 35281 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1344
by Furquan Shaikh (Code Review) 06 Sep '19

06 Sep '19

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35245 ) Change subject: src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1344 ...................................................................... src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1344 Cq-Depend: chrome-internal:1759167 Change-Id: Ib5784eb8c0f7c6e56950dad5c8254e00aa73cef4 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35245 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h 2 files changed, 308 insertions(+), 80 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h index b623ba0..962463e 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h @@ -37,19 +37,19 @@ #pragma pack(1) - -#include <MemInfoHob.h> - -/// -/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. -/// -typedef struct { - UINT8 Revision; ///< Chipset Init Info Revision - UINT8 Rsvd[3]; ///< Reserved - UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table - UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table -} CHIPSET_INIT_INFO; - + +#include <MemInfoHob.h> + +/// +/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. +/// +typedef struct { + UINT8 Revision; ///< Chipset Init Info Revision + UINT8 Rsvd[3]; ///< Reserved + UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table + UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table +} CHIPSET_INIT_INFO; + /** Fsp M Configuration **/ @@ -1464,11 +1464,96 @@ **/ UINT8 SerialIoUartDebugDataBits; -/** Offset 0x0457 - ReservedPchPreMem +/** Offset 0x0457 - Enable HD Audio DSP + Enable/disable HD Audio DSP feature. + $EN_DIS +**/ + UINT8 PchHdaDspEnable; + +/** Offset 0x0458 - VC Type + Virtual Channel Type Select: 0: VC0, 1: VC1. + 0: VC0, 1: VC1 +**/ + UINT8 PchHdaVcType; + +/** Offset 0x0459 - Universal Audio Architecture compliance for DSP enabled system + 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox + driver or SST driver supported). + $EN_DIS +**/ + UINT8 PchHdaDspUaaCompliance; + +/** Offset 0x045A - Enable HD Audio Link + Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkHda; + +/** Offset 0x045B - Enable HD Audio DMIC0 Link + Deprecated. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkDmic0; + +/** Offset 0x045C - Enable HD Audio DMIC1 Link + Deprecated. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkDmic1; + +/** Offset 0x045D - Enable HD Audio SSP0 Link + Enable/disable HD Audio SSP0/I2S link. Muxed with HDA. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSsp0; + +/** Offset 0x045E - Enable HD Audio SSP1 Link + Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSsp1; + +/** Offset 0x045F - Enable HD Audio SSP2 Link + Enable/disable HD Audio SSP2/I2S link. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSsp2; + +/** Offset 0x0460 - Enable HD Audio SoundWire#1 Link + Enable/disable HD Audio SNDW1 link. Muxed with HDA. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSndw1; + +/** Offset 0x0461 - Enable HD Audio SoundWire#2 Link + Enable/disable HD Audio SNDW2 link. Muxed with SSP1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSndw2; + +/** Offset 0x0462 - Enable HD Audio SoundWire#3 Link + Enable/disable HD Audio SNDW3 link. Muxed with DMIC1. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSndw3; + +/** Offset 0x0463 - Enable HD Audio SoundWire#4 Link + Enable/disable HD Audio SNDW4 link. Muxed with DMIC0. + $EN_DIS +**/ + UINT8 PchHdaAudioLinkSndw4; + +/** Offset 0x0464 - Soundwire Clock Buffer GPIO RCOMP Setting + 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance. + $EN_DIS +**/ + UINT8 PchHdaSndwBufferRcomp; + +/** Offset 0x0465 - ReservedPchPreMem Reserved for Pch Pre-Mem $EN_DIS **/ - UINT8 ReservedPchPreMem[16]; + UINT8 ReservedPchPreMem[2]; /** Offset 0x0467 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. @@ -2284,7 +2369,7 @@ Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose. 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info, 5:Load Error Warnings Info and Verbose + Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose **/ UINT8 PcdSerialDebugLevel; @@ -2390,13 +2475,27 @@ **/ UINT8 Ddr4SkipRefreshEn; -/** Offset 0x0510 +/** Offset 0x0510 - SerialDebugMrcLevel + MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, + Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, + Info & Verbose. + 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load + Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose +**/ + UINT8 SerialDebugMrcLevel; + +/** Offset 0x0511 - Enable HD Audio Sndw Link IO Control + deprecated +**/ + UINT8 PchHdaSndwLinkIoControlEnabled[4]; + +/** Offset 0x0515 **/ UINT8 UnusedUpdSpace8[2]; -/** Offset 0x0512 +/** Offset 0x0517 **/ - UINT8 ReservedFspmUpd[6]; + UINT8 ReservedFspmUpd[1]; } FSP_M_CONFIG; /** Fsp M Test Configuration diff --git a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h index 49da429..0df3063 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cometlake/FspsUpd.h @@ -37,49 +37,49 @@ #pragma pack(1) - -/// -/// Azalia Header structure -/// -typedef struct { - UINT16 VendorId; ///< Codec Vendor ID - UINT16 DeviceId; ///< Codec Device ID - UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. - UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. - UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. - UINT32 Reserved; ///< Reserved for future use. Must be set to 0. -} AZALIA_HEADER; - -/// -/// Audio Azalia Verb Table structure -/// -typedef struct { - AZALIA_HEADER Header; ///< AZALIA PCH header - UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header -} AUDIO_AZALIA_VERB_TABLE; - -/// -/// Refer to the definition of PCH_INT_PIN -/// -typedef enum { - SiPchNoInt, ///< No Interrupt Pin - SiPchIntA, - SiPchIntB, - SiPchIntC, - SiPchIntD -} SI_PCH_INT_PIN; -/// -/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. -/// -typedef struct { - UINT8 Device; ///< Device number - UINT8 Function; ///< Device function - UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) - UINT8 Irq; ///< IRQ to be set for device. -} SI_PCH_DEVICE_INTERRUPT_CONFIG; - -#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices - + +/// +/// Azalia Header structure +/// +typedef struct { + UINT16 VendorId; ///< Codec Vendor ID + UINT16 DeviceId; ///< Codec Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. + UINT32 Reserved; ///< Reserved for future use. Must be set to 0. +} AZALIA_HEADER; + +/// +/// Audio Azalia Verb Table structure +/// +typedef struct { + AZALIA_HEADER Header; ///< AZALIA PCH header + UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header +} AUDIO_AZALIA_VERB_TABLE; + +/// +/// Refer to the definition of PCH_INT_PIN +/// +typedef enum { + SiPchNoInt, ///< No Interrupt Pin + SiPchIntA, + SiPchIntB, + SiPchIntC, + SiPchIntD +} SI_PCH_INT_PIN; +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} SI_PCH_DEVICE_INTERRUPT_CONFIG; + +#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices + /** Fsp S Configuration **/ @@ -1319,8 +1319,8 @@ UINT8 PmcModPhySusPgEnable; /** Offset 0x036F - SlpS0WithGbeSupport - Enable/Disable SLP_S0 with GBE Support. Default is 0 when paired with WHL V0 stepping - CPU and 1 for all other CPUs. 0: Disable, 1: Enable + Enable/Disable SLP_S0 with GBE Support. Default is 0 for PCH-LP, WHL V0 Stepping + CPU and 1 for PCH-H Series. 0: Disable, 1: Enable $EN_DIS **/ UINT8 SlpS0WithGbeSupport; @@ -2053,23 +2053,23 @@ UINT8 PchScsEmmcHs400TuningRequired; /** Offset 0x06A0 - Set HS400 Tuning Data Valid - Set if HS400 Tuning Data Valid. + Deprecated $EN_DIS **/ UINT8 PchScsEmmcHs400DllDataValid; /** Offset 0x06A1 - Rx Strobe Delay Control - Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode). + Deprecated **/ UINT8 PchScsEmmcHs400RxStrobeDll1; /** Offset 0x06A2 - Tx Data Delay Control - Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode). + Deprecated **/ UINT8 PchScsEmmcHs400TxDataDll; /** Offset 0x06A3 - I/O Driver Strength - Deprecated. + Deprecated 0:33 Ohm, 1:40 Ohm, 2:50 Ohm **/ UINT8 PchScsEmmcHs400DriverStrength; @@ -2440,11 +2440,30 @@ **/ UINT8 ScsSdCardWpPinEnabled; -/** Offset 0x074F - ReservedPchPostMem +/** Offset 0x074F - Set SATA DEVSLP GPIO Reset Config + Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset, + 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte + for each port, byte0 for port0, byte1 for port1, and so on. +**/ + UINT8 SataPortsDevSlpResetConfig[8]; + +/** Offset 0x0757 - Flash Configuration Lock Down + Enable/disable flash lock down. If platform decides to skip this programming, it + must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post. + $EN_DIS +**/ + UINT8 SpiFlashCfgLockDown; + +/** Offset 0x0758 - Enable HD Audio Sndw Link IO Control + 0:Disabled, 1:Enabled. Enables IO Control to Sndw link if it is Enabled +**/ + UINT8 PchHdaSndwLinkIoControlEnabled[4]; + +/** Offset 0x075C - ReservedPchPostMem Reserved for Pch Post-Mem $EN_DIS **/ - UINT8 ReservedPchPostMem[16]; + UINT8 ReservedPchPostMem[3]; /** Offset 0x075F **/ @@ -3326,11 +3345,51 @@ **/ UINT8 C3StateUnDemotion; -/** Offset 0x08BF - ReservedCpuPostMemTest +/** Offset 0x08BF - Ratio Limit Num Core 0 + Ratio Limit Num Core0: This register defines the active core ranges for each frequency point +**/ + UINT8 RatioLimitNumCore0; + +/** Offset 0x08C0 - Ratio Limit Num Core 1 + Ratio Limit Num Core1: This register defines the active core ranges for each frequency point +**/ + UINT8 RatioLimitNumCore1; + +/** Offset 0x08C1 - Ratio Limit Num Core 2 + Ratio Limit Num Core2: This register defines the active core ranges for each frequency point +**/ + UINT8 RatioLimitNumCore2; + +/** Offset 0x08C2 - Ratio Limit Core 3 + Ratio Limit Num Core3: This register defines the active core ranges for each frequency point +**/ + UINT8 RatioLimitNumCore3; + +/** Offset 0x08C3 - Ratio Limit Num Core 4 + Ratio Limit Num Core4: This register defines the active core ranges for each frequency point +**/ + UINT8 RatioLimitNumCore4; + +/** Offset 0x08C4 - Ratio Limit Num Core 5 + Ratio Limit Num Core5: This register defines the active core ranges for each frequency point +**/ + UINT8 RatioLimitNumCore5; + +/** Offset 0x08C5 - Ratio Limit Num Core 6 + Ratio Limit Num Core6: This register defines the active core ranges for each frequency point +**/ + UINT8 RatioLimitNumCore6; + +/** Offset 0x08C6 - Ratio Limit Num Core 7 + Ratio Limit Num Core7: This register defines the active core ranges for each frequency point +**/ + UINT8 RatioLimitNumCore7; + +/** Offset 0x08C7 - ReservedCpuPostMemTest Reserved for CPU Post-Mem Test $EN_DIS **/ - UINT8 ReservedCpuPostMemTest[19]; + UINT8 ReservedCpuPostMemTest[11]; /** Offset 0x08D2 - SgxSinitDataFromTpm SgxSinitDataFromTpm default values @@ -3338,8 +3397,7 @@ UINT8 SgxSinitDataFromTpm; /** Offset 0x08D3 - End of Post message - Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): - EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI + Deprecated 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved **/ UINT8 EndOfPostMessage; @@ -3488,11 +3546,82 @@ **/ UINT8 MctpBroadcastCycle; -/** Offset 0x0A8A +/** Offset 0x0A8A - Use DLL values from policy + Set if FSP should use HS400 DLL values from policy + $EN_DIS **/ - UINT8 UnusedUpdSpace29[2]; + UINT8 EmmcUseCustomDlls; -/** Offset 0x0A8C +/** Offset 0x0A8B +**/ + UINT8 UnusedUpdSpace29; + +/** Offset 0x0A8C - Emmc Tx CMD Delay control register value + Please see Tx CMD Delay Control register definition for help +**/ + UINT32 EmmcTxCmdDelayRegValue; + +/** Offset 0x0A90 - Emmc Tx DATA Delay control 1 register value + Please see Tx DATA Delay control 1 register definition for help +**/ + UINT32 EmmcTxDataDelay1RegValue; + +/** Offset 0x0A94 - Emmc Tx DATA Delay control 2 register value + Please see Tx DATA Delay control 2 register definition for help +**/ + UINT32 EmmcTxDataDelay2RegValue; + +/** Offset 0x0A98 - Emmc Rx CMD + DATA Delay control 1 register value + Please see Rx CMD + DATA Delay control 1 register definition for help +**/ + UINT32 EmmcRxCmdDataDelay1RegValue; + +/** Offset 0x0A9C - Emmc Rx CMD + DATA Delay control 2 register value + Please see Rx CMD + DATA Delay control 2 register definition for help +**/ + UINT32 EmmcRxCmdDataDelay2RegValue; + +/** Offset 0x0AA0 - Emmc Rx Strobe Delay control register value + Please see Rx Strobe Delay control register definition for help +**/ + UINT32 EmmcRxStrobeDelayRegValue; + +/** Offset 0x0AA4 - Use tuned DLL values from policy + Set if FSP should use HS400 DLL values from policy + $EN_DIS +**/ + UINT8 SdCardUseCustomDlls; + +/** Offset 0x0AA5 +**/ + UINT8 UnusedUpdSpace30[3]; + +/** Offset 0x0AA8 - SdCard Tx CMD Delay control register value + Please see Tx CMD Delay Control register definition for help +**/ + UINT32 SdCardTxCmdDelayRegValue; + +/** Offset 0x0AAC - SdCard Tx DATA Delay control 1 register value + Please see Tx DATA Delay control 1 register definition for help +**/ + UINT32 SdCardTxDataDelay1RegValue; + +/** Offset 0x0AB0 - SdCard Tx DATA Delay control 2 register value + Please see Tx DATA Delay control 2 register definition for help +**/ + UINT32 SdCardTxDataDelay2RegValue; + +/** Offset 0x0AB4 - SdCard Rx CMD + DATA Delay control 1 register value + Please see Rx CMD + DATA Delay control 1 register definition for help +**/ + UINT32 SdCardRxCmdDataDelay1RegValue; + +/** Offset 0x0AB8 - SdCard Rx CMD + DATA Delay control 2 register value + Please see Rx CMD + DATA Delay control 2 register definition for help +**/ + UINT32 SdCardRxCmdDataDelay2RegValue; + +/** Offset 0x0ABC **/ UINT8 ReservedFspsTestUpd[12]; } FSP_S_TEST_CONFIG; @@ -3513,11 +3642,11 @@ **/ FSP_S_TEST_CONFIG FspsTestConfig; -/** Offset 0x0A98 +/** Offset 0x0AC8 **/ - UINT8 UnusedUpdSpace30[6]; + UINT8 UnusedUpdSpace31[6]; -/** Offset 0x0A9E +/** Offset 0x0ACE **/ UINT16 UpdTerminator; } FSPS_UPD; -- To view, visit https://review.coreboot.org/c/coreboot/+/35245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5784eb8c0f7c6e56950dad5c8254e00aa73cef4 Gerrit-Change-Number: 35245 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common: Add missing stdint.h to acpummio.h
by Marshall Dawson (Code Review) 06 Sep '19

06 Sep '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35268 ) Change subject: soc/amd/common: Add missing stdint.h to acpummio.h ...................................................................... soc/amd/common: Add missing stdint.h to acpummio.h Change-Id: I3eae80a677e9d6932dc115523da2c0819a371fa7 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/acpimmio.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/35268/1 diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 32da867..59ab9e5 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -18,6 +18,7 @@ #ifndef __AMDBLOCKS_ACPIMMIO_H__ #define __AMDBLOCKS_ACPIMMIO_H__ +#include <stdint.h> /* iomap.h must indicate if the device uses a block, optional if unused. */ #include <soc/iomap.h> #ifndef SUPPORTS_ACPIMMIO_SMI_BASE -- To view, visit https://review.coreboot.org/c/coreboot/+/35268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3eae80a677e9d6932dc115523da2c0819a371fa7 Gerrit-Change-Number: 35268 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: soc/amd/common: Add missing stdint.h to BiosCallOuts.h
by Marshall Dawson (Code Review) 06 Sep '19

06 Sep '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35267 ) Change subject: soc/amd/common: Add missing stdint.h to BiosCallOuts.h ...................................................................... soc/amd/common: Add missing stdint.h to BiosCallOuts.h Change-Id: Ib0eea9bfd0c8d9e3eba257b561980accf5b4bab4 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35267/1 diff --git a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h index 829630b..9205499 100644 --- a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h +++ b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h @@ -18,6 +18,7 @@ #define __CALLOUTS_AMD_AGESA_H__ #include <amdblocks/agesawrapper.h> +#include <stdint.h> #define BIOS_HEAP_SIZE 0x30000 #define BSP_STACK_BASE_ADDR 0x30000 -- To view, visit https://review.coreboot.org/c/coreboot/+/35267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0eea9bfd0c8d9e3eba257b561980accf5b4bab4 Gerrit-Change-Number: 35267 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2019