Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34858 )
Change subject: mb/google/hatch/variants/helios: Modify FPU power on sequence
......................................................................
Patch Set 5: Code-Review+2
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Hello Philip Chen, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34858
to look at the new patch set (#5).
Change subject: mb/google/hatch/variants/helios: Modify FPU power on sequence
......................................................................
mb/google/hatch/variants/helios: Modify FPU power on sequence
pull in the FPU VDDIO turn on to fix the power leakage problem
on FPU VDDIO and FPU CS during power on sequence.
BUG=b:138638571
BRANCH=none
TEST=emerge-hatch coreboot chromeos-bootimage
Signed-off-by: Frank_Chu <frank_chu(a)pegatron.corp-partner.google.com>
Change-Id: I3f6bf3676922e987c2e282b697a2333e2d90289e
---
M src/mainboard/google/hatch/variants/helios/gpio.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/34858/5
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Hello Philip Chen, Tim Wawrzynczak, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34858
to look at the new patch set (#4).
Change subject: mb/google/hatch/variants/helios: Modify FPU power on sequence
......................................................................
mb/google/hatch/variants/helios: Modify FPU power on sequence
pull in the FPU VDDIO turn on to fix FPU VDDIO and FPU CS
during power on sequence.
BUG=b:138638571
BRANCH=none
TEST=emerge-hatch coreboot chromeos-bootimage
Signed-off-by: Frank_Chu <frank_chu(a)pegatron.corp-partner.google.com>
Change-Id: I3f6bf3676922e987c2e282b697a2333e2d90289e
---
M src/mainboard/google/hatch/variants/helios/gpio.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/34858/4
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Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34743 )
Change subject: mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2
......................................................................
Patch Set 2: Code-Review+2
As per the last reply from Hank Lin, providing my this comment.
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Hank Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34743 )
Change subject: mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2
......................................................................
Patch Set 2:
(1 comment)
> Patch Set 2:
>
> (1 comment)
https://review.coreboot.org/c/coreboot/+/34743/1/src/mainboard/google/hatch…
File src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl:
https://review.coreboot.org/c/coreboot/+/34743/1/src/mainboard/google/hatch…
PS1, Line 37: 13000
> Please, address this above comment. Thanks.
In RFQ, it is evaluated that the system must conform to the "Skin pass" state, and the CPU wattage needs to be below 10w.
The current setting is PL1: 8/13w. There are two factors for 13w.
1. Thermal module capacity considerations
2. Avoid the sudden drop of wattage, resulting in the drop of test score
After discussing with ASUS customers, import EVT first with PL1:8/13w settings.
DVT verification will be adjusted according to the situation.
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31933 )
Change subject: util/sconfig: Expose usable PCI and PNP device names
......................................................................
Patch Set 6: Code-Review+2
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/20979 )
Change subject: nb/intel/x4x/raminit: Move dummy reads after JEDEC init
......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/20979/7//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/20979/7//COMMIT_MSG@7
PS7, Line 7: nb/intel/x4x/raminit: Move dummy reads after JEDEC init
> It’s confusing right now, as they are already after JEDEC init. […]
specified in the next paragraph
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Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33770 )
Change subject: soc/amd/picasso: Update southbridge
......................................................................
Patch Set 13:
(2 comments)
https://review.coreboot.org/c/coreboot/+/33770/13/src/soc/amd/picasso/inclu…
File src/soc/amd/picasso/include/soc/southbridge.h:
https://review.coreboot.org/c/coreboot/+/33770/13/src/soc/amd/picasso/inclu…
PS13, Line 169: #define GPP_CLK_REQ_MAP_CLK6 (1 << GPP_CLK6_REQ_SHL)
Mask values are overlapping, is it on purpose?
GPP_CLK_REQ_MAP_MASK0 0x0000000f
GPP_CLK_REQ_MAP_MASK1 0x0000003c
GPP_CLK_REQ_MAP_MASK2 0x000000f0
GPP_CLK_REQ_MAP_MASK3 0x000003c0
GPP_CLK_REQ_MAP_MASK4 0x00000f00
GPP_CLK_REQ_MAP_MASK5 0x00003c00
GPP_CLK_REQ_MAP_MASK6 0x0000f000
https://review.coreboot.org/c/coreboot/+/33770/13/src/soc/amd/picasso/inclu…
PS13, Line 229: 0x5b
This sounds strange, normally it's a pair with STATE being the second register...so it should be 0x61
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