coreboot-gerrit September 2019

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Change in coreboot[master]: mb/google/drallion: modify UDB setting
by EricR Lai (Code Review) 09 Sep '19

09 Sep '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35283 ) Change subject: mb/google/drallion: modify UDB setting ...................................................................... mb/google/drallion: modify UDB setting Based on HW schematic to modify UDB setting. Drallion has two type C on left and two type A on right. BUG=b:138082886 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I925de209635d92ef61ccb9114efebb4b10f30e87 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb 1 file changed, 31 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/35283/1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 8870126..879b7f0 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -131,29 +131,22 @@ }" # Intel Common SoC Config - register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port - register "usb2_ports[1]" = "USB2_PORT_LONG(OC0)" # Left Type-A Port - register "usb2_ports[2]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port - register "usb2_ports[3]" = "USB2_PORT_EMPTY" - register "usb2_ports[4]" = "USB2_PORT_EMPTY" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port 1 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Left Type-C Port 2 + register "usb2_ports[2]" = "USB2_PORT_LONG(OC0)" # Right Type-A Port 1 + register "usb2_ports[3]" = "USB2_PORT_LONG(OC1)" # Right Type-A Port 2 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # WWAN register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # Camera - register "usb2_ports[6]" = "{ - .enable = 1, \ - .ocpin = OC_SKIP, \ - .tx_bias = USB2_BIAS_0MV, \ - .tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \ - .pre_emp_bias = USB2_BIAS_28P15MV, \ - .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, \ - }" # WWAN - register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # USH - register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[6]" = "USB2_PORT_EMPTY" + register "usb2_ports[7]" = "USB2_PORT_EMPTY" + register "usb2_ports[8]" = "USB2_PORT_EMPTY" register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Left Type-A Port - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN - register "usb3_ports[4]" = "USB3_PORT_EMPTY" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Left Type-C Port 2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Right Type-A Port 1 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Right Type-A Port 2 + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # WWAN register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Intel Common SoC Config @@ -248,8 +241,8 @@ device usb 2.0 on end end chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" - register "type" = "UPC_TYPE_A" + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(1, 2)" device usb 2.1 on end end @@ -260,24 +253,20 @@ device usb 2.2 on end end chip drivers/usb/acpi - register "desc" = ""Camera"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.5 on end + register "desc" = ""Right Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device usb 2.3 on end end chip drivers/usb/acpi register "desc" = ""WWAN"" register "type" = "UPC_TYPE_INTERNAL" - device usb 2.6 on end + device usb 2.4 on end end chip drivers/usb/acpi - register "desc" = ""USH"" + register "desc" = ""Camera"" register "type" = "UPC_TYPE_INTERNAL" - device usb 2.7 on end - end - chip drivers/usb/acpi - register "desc" = ""Fingerprint"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.8 on end + device usb 2.5 on end end chip drivers/usb/acpi register "desc" = ""Bluetooth"" @@ -292,21 +281,27 @@ device usb 3.0 on end end chip drivers/usb/acpi - register "desc" = ""Left Type-A Port"" + register "desc" = ""Right Type-A Port"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(1, 2)" + register "group" = "ACPI_PLD_GROUP(2, 1)" device usb 3.1 on end end chip drivers/usb/acpi register "desc" = ""Right Type-A Port"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(2, 1)" + register "group" = "ACPI_PLD_GROUP(2, 2)" device usb 3.2 on end end chip drivers/usb/acpi + register "desc" = ""Left Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.3 on end + end + chip drivers/usb/acpi register "desc" = ""WWAN"" register "type" = "UPC_TYPE_INTERNAL" - device usb 3.3 on end + device usb 3.4 on end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/35283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I925de209635d92ef61ccb9114efebb4b10f30e87 Gerrit-Change-Number: 35283 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mb/asrock/h110m: add missing pci devices to tree
by Maxim Polyakov (Code Review) 09 Sep '19

09 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35100 ) Change subject: mb/asrock/h110m: add missing pci devices to tree ...................................................................... mb/asrock/h110m: add missing pci devices to tree These devices turn on after initializing the Intel FSP Change-Id: I0a15537b6ba56fcf63267641ef2219f24d25d9c4 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/35100/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 24409a1..f51f477 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -273,6 +273,8 @@ device pci 02.0 on # Integrated Graphics Device subsystemid 0x1849 0x1912 end + device pci 04.0 on # Thermal Subsystem + device pci 08.0 on # Gaussian Mixture Model device pci 14.0 on # USB xHCI subsystemid 0x1849 0xa131 end -- To view, visit https://review.coreboot.org/c/coreboot/+/35100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a15537b6ba56fcf63267641ef2219f24d25d9c4 Gerrit-Change-Number: 35100 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asrock/h110m: disable unused sata ports
by Maxim Polyakov (Code Review) 09 Sep '19

09 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35071 ) Change subject: mb/asrock/h110m: disable unused sata ports ...................................................................... mb/asrock/h110m: disable unused sata ports Change-Id: I5b3ad372f1d6607cc7b4a78e3c59d2a5ae1d2cf5 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/35071/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index f87ca45..24409a1 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -184,8 +184,8 @@ [3] = 1, \ [4] = 1, \ [5] = 1, \ - [6] = 1, \ - [7] = 1, \ + [6] = 0, \ + [7] = 0, \ }" # PCH UART, SPI, I2C -- To view, visit https://review.coreboot.org/c/coreboot/+/35071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b3ad372f1d6607cc7b4a78e3c59d2a5ae1d2cf5 Gerrit-Change-Number: 35071 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: mb/asrock/h110m: remove unsed i2c_voltage settings
by Maxim Polyakov (Code Review) 09 Sep '19

09 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35069 ) Change subject: mb/asrock/h110m: remove unsed i2c_voltage settings ...................................................................... mb/asrock/h110m: remove unsed i2c_voltage settings The string "register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" was mistakenly taken from the Intel KBL-RVP8 devicetree.cb. Remove it, since the i2c4 bus is disabled in the "SerialIoDevMode" register Change-Id: I44ecd5c22efd66b02a2851dc14a1a95421f39a71 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/35069/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index bf718b8..934083a 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -146,8 +146,6 @@ }" register "EnableLan" = "0" - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V - register "PmTimerDisabled" = "0" # USB -- To view, visit https://review.coreboot.org/c/coreboot/+/35069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44ecd5c22efd66b02a2851dc14a1a95421f39a71 Gerrit-Change-Number: 35069 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/asrock/h110m: use VR_CFG_AMP() macro to set PSI threshold
by Maxim Polyakov (Code Review) 09 Sep '19

09 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35068 ) Change subject: mb/asrock/h110m: use VR_CFG_AMP() macro to set PSI threshold ...................................................................... mb/asrock/h110m: use VR_CFG_AMP() macro to set PSI threshold Change-Id: Iafeb7f7689a16d3b16eb0564c4dd72919a8d1382 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/35068/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 61d3e66..bf718b8 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -95,9 +95,9 @@ # * - is set automatically for the KBL-S/KBL-DT CPUs in the vr_config.c register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x10, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(4), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ .imon_slope = 0x0, \ @@ -108,9 +108,9 @@ register "domain_vr_config[VR_IA_CORE]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ .imon_slope = 0x0, \ @@ -121,9 +121,9 @@ register "domain_vr_config[VR_GT_UNSLICED]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ .imon_slope = 0x0, \ @@ -134,9 +134,9 @@ register "domain_vr_config[VR_GT_SLICED]" = "{ .vr_config_enable = 1, \ - .psi1threshold = 0x50, \ - .psi2threshold = 0x14, \ - .psi3threshold = 0x4, \ + .psi1threshold = VR_CFG_AMP(20), \ + .psi2threshold = VR_CFG_AMP(5), \ + .psi3threshold = VR_CFG_AMP(1), \ .psi3enable = 1, \ .psi4enable = 1, \ .imon_slope = 0x0, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/35068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iafeb7f7689a16d3b16eb0564c4dd72919a8d1382 Gerrit-Change-Number: 35068 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asrock/h110m: fix VR Settings Configuration info
by Maxim Polyakov (Code Review) 09 Sep '19

09 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35067 ) Change subject: mb/asrock/h110m: fix VR Settings Configuration info ...................................................................... mb/asrock/h110m: fix VR Settings Configuration info In accordance with changes in the initialization code for Skylake/Kaby Lake CPU [1], the IccMax is set automatically in vr_config.c The patch adds a comment about this and fixes invalid parameter values in the VR settings information. [1] https://review.coreboot.org/c/coreboot/+/34937 Change-Id: I6e1aefde135ffce75a5d837348595aa20aff0513 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35067/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 3067ffe..61d3e66 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -89,9 +89,10 @@ #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | 0 | - #| IccMax | 7A | 34A | 34A | 35A | 35A | - #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #| IccMax* | 0 | 0 | 0 | 0 | 0 | + #| VrVoltageLimit | 0 | 0 | 0 | 0 | 0 | #+----------------+-------+-------+-------------+-------------+-------+ + # * - is set automatically for the KBL-S/KBL-DT CPUs in the vr_config.c register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ .vr_config_enable = 1, \ .psi1threshold = 0x50, \ -- To view, visit https://review.coreboot.org/c/coreboot/+/35067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e1aefde135ffce75a5d837348595aa20aff0513 Gerrit-Change-Number: 35067 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/southbridge/amd/pi/hudson/lpc.c: add missing MCFG ACPI table gene...
by Michał Żygowski (Code Review) 09 Sep '19

09 Sep '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35286 ) Change subject: src/southbridge/amd/pi/hudson/lpc.c: add missing MCFG ACPI table generation ...................................................................... src/southbridge/amd/pi/hudson/lpc.c: add missing MCFG ACPI table generation The MCFG ACPI table was not being created. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I35bdefb2a565d18917a2f6517d443890f93bd252 --- M src/southbridge/amd/pi/hudson/lpc.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/35286/1 diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 5354a27..02123a1 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -332,7 +332,11 @@ unsigned long acpi_fill_mcfg(unsigned long current) { - /* Just a dummy */ + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + CONFIG_MMCONF_BASE_ADDRESS, + 0, + 0, + CONFIG_MMCONF_BUS_NUMBER); return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35bdefb2a565d18917a2f6517d443890f93bd252 Gerrit-Change-Number: 35286 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: soc/intel/cannonlake: Add ability to disable Heci1
by Bora Guvendik (Code Review) 09 Sep '19

09 Sep '19

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32992 Change subject: soc/intel/cannonlake: Add ability to disable Heci1 ...................................................................... soc/intel/cannonlake: Add ability to disable Heci1 Decide if HECI1 should be hidden prior to boot to OS. BUG=none TEST=Boot to OS, verify if Heci1 is disabled Change-Id: I7c63316c8b04fb101d34064daac5ba4fdc05a63c Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/romstage/fsp_params.c 3 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/32992/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 0d51c1c..6bea8fe 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -421,6 +421,7 @@ * Bit 0: MISCCFG_GPDLCGEN */ uint8_t gpio_pm[TOTAL_GPIO_COMM]; + uint8_t Heci1Disabled; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index dd93882..7dc1dd0 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -341,6 +341,7 @@ params->ScsUfsEnabled = dev->enabled; params->Heci3Enabled = config->Heci3Enabled; + params->Heci1Disabled = config->Heci1Disabled; params->Device4Enable = config->Device4Enable; /* VrConfig Settings for 5 domains diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 6e492bb..365fb9f 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -25,7 +25,6 @@ #include <vendorcode/google/chromeos/chromeos.h> #include "../chip.h" - static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config) { unsigned int i; -- To view, visit https://review.coreboot.org/c/coreboot/+/32992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c63316c8b04fb101d34064daac5ba4fdc05a63c Gerrit-Change-Number: 32992 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Fix minor whitespace
by Paul Menzel (Code Review) 09 Sep '19

09 Sep '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35265 ) Change subject: drivers/intel/fsp2_0: Fix minor whitespace ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/35265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03a62c6a35053b67bfc609a365068cf284bcc1a0 Gerrit-Change-Number: 35265 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 09 Sep 2019 09:27:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Fix minor whitespace
by Kyösti Mälkki (Code Review) 09 Sep '19

09 Sep '19

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35265 ) Change subject: drivers/intel/fsp2_0: Fix minor whitespace ...................................................................... drivers/intel/fsp2_0: Fix minor whitespace Change-Id: I03a62c6a35053b67bfc609a365068cf284bcc1a0 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35265 Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/intel/fsp2_0/memory_init.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Richard Spiegel: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 9789c96..08afffc 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -225,7 +225,7 @@ arch_upd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; } - printk(BIOS_SPEW, "bootmode is set to :%d\n", arch_upd->BootMode); + printk(BIOS_SPEW, "bootmode is set to: %d\n", arch_upd->BootMode); return CB_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03a62c6a35053b67bfc609a365068cf284bcc1a0 Gerrit-Change-Number: 35265 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit September 2019