Change in coreboot[master]: soc/mediatek: Fix USB enumeration issue

[Ran Bi (Code Review)]

Ran Bi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35150 )

Change subject: soc/mediatek: Fix USB enumeration issue
......................................................................

soc/mediatek: Fix USB enumeration issue

Some USB3.0 devices are failed to enumerate after USB reset,
and xhci port status register show device is disconnected.
After measure USB signal, we can find usb disconnect threshold is lower
and disconnect event is triggered unexpectedly.

USB designer suggest to change discth to 15.

BUG=b:122047652
TEST=emerge-kukui coreboot chromeos-bootimage

Change-Id: I0e8556035b49d693a42cbe1099a6882a1c0ed0d1
Signed-off-by: Changqi Hu 
---
M src/soc/mediatek/common/include/soc/usb_common.h
M src/soc/mediatek/common/usb.c
2 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/35150/1

diff --git a/src/soc/mediatek/common/include/soc/usb_common.h b/src/soc/mediatek/common/include/soc/usb_common.h
old mode 100644
new mode 100755
index 8a36c6a..22704e7
--- a/src/soc/mediatek/common/include/soc/usb_common.h
+++ b/src/soc/mediatek/common/include/soc/usb_common.h
@@ -70,6 +70,8 @@
 #define PA6_RG_U2_ISO_EN			(0x1 << 31)
 #define PA6_RG_U2_BC11_SW_EN		(0x1 << 23)
 #define PA6_RG_U2_OTG_VBUSCMP_EN	(0x1 << 20)
+#define PA6_RG_U2_DISCTH		(0xf << 4)
+#define PA6_RG_U2_DISCTH_VAL(x)		((0xf & (x)) << 4)
 #define PA6_RG_U2_SQTH			(0xf << 0)
 #define PA6_RG_U2_SQTH_VAL(x)		((0xf & (x)) << 0)

diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c
old mode 100644
new mode 100755
index dcb9307..f5263fb
--- a/src/soc/mediatek/common/usb.c
+++ b/src/soc/mediatek/common/usb.c
@@ -76,6 +76,10 @@
    /* Set USB 2.0 slew rate value */
    clrsetbits_le32(&phy->u2phy.usbphyacr5,
    	PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4));
+
+	/*Set USB 2.0 disconnect threshold*/
+	clrsetbits_le32(&phy->u2phy.usbphyacr6,
+		PA6_RG_U2_DISCTH, PA6_RG_U2_DISCTH_VAL(15));
 }

static void u3phy_power_on(void)

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35150 )

Change subject: soc/mediatek: Fix USB enumeration issue
......................................................................

Patch Set 1:

(5 comments)

https://review.coreboot.org/c/coreboot/+/35150/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/35150/1//COMMIT_MSG@11 
PS1, Line 11: measure
measuring

https://review.coreboot.org/c/coreboot/+/35150/1//COMMIT_MSG@11 
PS1, Line 11: can find
found that

https://review.coreboot.org/c/coreboot/+/35150/1//COMMIT_MSG@12 
PS1, Line 12: is
was

https://review.coreboot.org/c/coreboot/+/35150/1//COMMIT_MSG@14 
PS1, Line 14: suggest
suggests

https://review.coreboot.org/c/coreboot/+/35150/1/src/soc/mediatek/common/usb... 
File src/soc/mediatek/common/usb.c:

https://review.coreboot.org/c/coreboot/+/35150/1/src/soc/mediatek/common/usb... 
PS1, Line 80: Set
/* Set ... threshold */

(add space)

[Ran Bi (Code Review)]

Hello Yu-Ping Wu, Julius Werner, CK HU, You-Cheng Syu, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35150

to look at the new patch set (#2).

Change subject: soc/mediatek: Fix USB enumeration issue
......................................................................

soc/mediatek: Fix USB enumeration issue

Some USB3.0 devices are failed to enumerate after USB reset,
and xhci port status register show device is disconnected.
After measuring USB signal, we found that usb disconnect threshold was lower
and disconnect event is triggered unexpectedly.

USB designer suggests to change discth to 15.

BUG=b:122047652
TEST=emerge-kukui coreboot chromeos-bootimage

Change-Id: I0e8556035b49d693a42cbe1099a6882a1c0ed0d1
Signed-off-by: Changqi Hu 
---
M src/soc/mediatek/common/include/soc/usb_common.h
M src/soc/mediatek/common/usb.c
2 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/35150/2

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35150 )

Change subject: soc/mediatek: Fix USB enumeration issue
......................................................................

Patch Set 2:

File src/soc/mediatek/common/include/soc/usb_common.h has one or more executable bits set in the file permissions.
File src/soc/mediatek/common/usb.c has one or more executable bits set in the file permissions.

Please do

chmod -x src/soc/mediatek/common/include/soc/usb_common.h  src/soc/mediatek/common/usb.c
 git add src/soc/mediatek/common/include/soc/usb_common.h  src/soc/mediatek/common/usb.c
 git commit --amend

then upload again

[Ran Bi (Code Review)]

Hello Yu-Ping Wu, Julius Werner, CK HU, You-Cheng Syu, Tristan Hsieh, Hung-Te Lin, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35150

to look at the new patch set (#3).

Change subject: soc/mediatek: Fix USB enumeration issue
......................................................................

soc/mediatek: Fix USB enumeration issue

Some USB3.0 devices are failed to enumerate after USB reset,
and xhci port status register show device is disconnected.
After measuring USB signal, we found that usb disconnect threshold was lower
and disconnect event is triggered unexpectedly.

USB designer suggests to change discth to 15.

BUG=b:122047652
TEST=emerge-kukui coreboot chromeos-bootimage

Change-Id: I0e8556035b49d693a42cbe1099a6882a1c0ed0d1
Signed-off-by: Changqi Hu 
---
M src/soc/mediatek/common/include/soc/usb_common.h
M src/soc/mediatek/common/usb.c
2 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/35150/3

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35150 )

Change subject: soc/mediatek: Fix USB enumeration issue
......................................................................

Patch Set 3: Code-Review+2

[Hung-Te Lin (Code Review)]

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35150 )

Change subject: soc/mediatek: Fix USB enumeration issue
......................................................................

Patch Set 3:

(5 comments)

https://review.coreboot.org/c/coreboot/+/35150/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/35150/1//COMMIT_MSG@11 
PS1, Line 11: measure
> measuring

Done

https://review.coreboot.org/c/coreboot/+/35150/1//COMMIT_MSG@11 
PS1, Line 11: can find
> found that

Done

https://review.coreboot.org/c/coreboot/+/35150/1//COMMIT_MSG@12 
PS1, Line 12: is
> was

Done

https://review.coreboot.org/c/coreboot/+/35150/1//COMMIT_MSG@14 
PS1, Line 14: suggest
> suggests

Done

https://review.coreboot.org/c/coreboot/+/35150/1/src/soc/mediatek/common/usb... 
File src/soc/mediatek/common/usb.c:

https://review.coreboot.org/c/coreboot/+/35150/1/src/soc/mediatek/common/usb... 
PS1, Line 80: Set
> /* Set ... threshold */ […]

Done

[Yu-Ping Wu (Code Review)]

Yu-Ping Wu has uploaded a new patch set (#4) to the change originally created by Ran Bi. ( https://review.coreboot.org/c/coreboot/+/35150 )

Change subject: soc/mediatek: Fix USB enumeration issue
......................................................................

soc/mediatek: Fix USB enumeration issue

Some USB 3.0 devices fail to enumerate after USB reset, and xhci port
status register shows the device is disconnected. After measuring the
USB signal, we found that the USB disconnect threshold was lower and
that the disconnect event was triggered unexpectedly.

USB designers suggest changing discth to 15.

BUG=b:122047652
TEST=emerge-kukui coreboot chromeos-bootimage

Change-Id: I0e8556035b49d693a42cbe1099a6882a1c0ed0d1
Signed-off-by: Changqi Hu 
---
M src/soc/mediatek/common/include/soc/usb_common.h
M src/soc/mediatek/common/usb.c
2 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/35150/4

[Yu-Ping Wu (Code Review)]

Yu-Ping Wu has uploaded a new patch set (#5) to the change originally created by Ran Bi. ( https://review.coreboot.org/c/coreboot/+/35150 )

Change subject: soc/mediatek: Fix USB enumeration issue
......................................................................

soc/mediatek: Fix USB enumeration issue

Some USB 3.0 devices fail to be enumerated after USB reset, and xhci
port status register shows the device is disconnected. After measuring
the USB signal, we found that the USB disconnect threshold was lower and
that the disconnect event was triggered unexpectedly.

USB designers suggest changing discth to 15.

BUG=b:122047652
TEST=emerge-kukui coreboot chromeos-bootimage

Change-Id: I0e8556035b49d693a42cbe1099a6882a1c0ed0d1
Signed-off-by: Changqi Hu 
---
M src/soc/mediatek/common/include/soc/usb_common.h
M src/soc/mediatek/common/usb.c
2 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/35150/5

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35150 )

Change subject: soc/mediatek: Fix USB enumeration issue
......................................................................

soc/mediatek: Fix USB enumeration issue

Some USB 3.0 devices fail to be enumerated after USB reset, and xhci
port status register shows the device is disconnected. After measuring
the USB signal, we found that the USB disconnect threshold was lower and
that the disconnect event was triggered unexpectedly.

USB designers suggest changing discth to 15.

BUG=b:122047652
TEST=emerge-kukui coreboot chromeos-bootimage

Change-Id: I0e8556035b49d693a42cbe1099a6882a1c0ed0d1
Signed-off-by: Changqi Hu 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35150
Tested-by: build bot (Jenkins) 
Reviewed-by: Hung-Te Lin 
---
M src/soc/mediatek/common/include/soc/usb_common.h
M src/soc/mediatek/common/usb.c
2 files changed, 6 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Hung-Te Lin: Looks good to me, approved

diff --git a/src/soc/mediatek/common/include/soc/usb_common.h b/src/soc/mediatek/common/include/soc/usb_common.h
index 8a36c6a..22704e7 100644
--- a/src/soc/mediatek/common/include/soc/usb_common.h
+++ b/src/soc/mediatek/common/include/soc/usb_common.h
@@ -70,6 +70,8 @@
 #define PA6_RG_U2_ISO_EN			(0x1 << 31)
 #define PA6_RG_U2_BC11_SW_EN		(0x1 << 23)
 #define PA6_RG_U2_OTG_VBUSCMP_EN	(0x1 << 20)
+#define PA6_RG_U2_DISCTH		(0xf << 4)
+#define PA6_RG_U2_DISCTH_VAL(x)		((0xf & (x)) << 4)
 #define PA6_RG_U2_SQTH			(0xf << 0)
 #define PA6_RG_U2_SQTH_VAL(x)		((0xf & (x)) << 0)

diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c
index dcb9307..328bf66 100644
--- a/src/soc/mediatek/common/usb.c
+++ b/src/soc/mediatek/common/usb.c
@@ -76,6 +76,10 @@
    /* Set USB 2.0 slew rate value */
    clrsetbits_le32(&phy->u2phy.usbphyacr5,
    	PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4));
+
+	/* Set USB 2.0 disconnect threshold */
+	clrsetbits_le32(&phy->u2phy.usbphyacr6,
+		PA6_RG_U2_DISCTH, PA6_RG_U2_DISCTH_VAL(15));
 }

static void u3phy_power_on(void)