coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: soc/mediatek: Register coreboot table for ATF
by Hung-Te Lin (Code Review) 05 Sep '19

05 Sep '19

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32541 Change subject: soc/mediatek: Register coreboot table for ATF ...................................................................... soc/mediatek: Register coreboot table for ATF Register coreboot table into BL31 parameter so ATF can find coreboot information and use it (for example, use memory console). BUG=None TEST=emerge-kukui coreboot; Boots on Kukui. Change-Id: I6e39495988159608c1c4bbf16a97c86e526bd82b Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/soc/mediatek/common/bl31_plat_params.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/32541/1 diff --git a/src/soc/mediatek/common/bl31_plat_params.c b/src/soc/mediatek/common/bl31_plat_params.c index eb7477a..51edab3 100644 --- a/src/soc/mediatek/common/bl31_plat_params.c +++ b/src/soc/mediatek/common/bl31_plat_params.c @@ -14,6 +14,7 @@ */ #include <arm_tf.h> +#include <cbmem.h> #include <soc/bl31_plat_params.h> static struct bl31_plat_param *plat_params; @@ -26,5 +27,13 @@ void *soc_get_bl31_plat_params(bl31_params_t *bl31_params) { + static struct bl31_u64_param cbtable_param = { + .h = { .type = PARAM_COREBOOT_TABLE, }, + }; + if (!cbtable_param.value) { + cbtable_param.value = (uint64_t)cbmem_find(CBMEM_ID_CBTABLE); + if (cbtable_param.value) + register_bl31_param(&cbtable_param.h); + } return plat_params; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32541 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e39495988159608c1c4bbf16a97c86e526bd82b Gerrit-Change-Number: 32541 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2
by Sumeet R Pawnikar (Code Review) 05 Sep '19

05 Sep '19

Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34743 ) Change subject: mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2 ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/34743/1/src/mainboard/google/hatch… File src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl: https://review.coreboot.org/c/coreboot/+/34743/1/src/mainboard/google/hatch… PS1, Line 37: 13000 > How did you arrive to 13W for PowerLimitMaximum ? Shouldn't this to 15W ? Please, address this above comment. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/34743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a96c33ce710c32b57e2ad8066830ff83398c57 Gerrit-Change-Number: 34743 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 05 Sep 2019 06:24:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Fix minor whitespace
by Martin Roth (Code Review) 05 Sep '19

05 Sep '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35265 ) Change subject: drivers/intel/fsp2_0: Fix minor whitespace ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03a62c6a35053b67bfc609a365068cf284bcc1a0 Gerrit-Change-Number: 35265 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 05 Sep 2019 00:15:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Create a hybrid romstage to begin in DRAM
by Marshall Dawson (Code Review) 05 Sep '19

05 Sep '19

Hello Edward O'Callaghan, Julius Werner, Richard Spiegel, build bot (Jenkins), Furquan Shaikh, Martin Roth, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/33759 to look at the new patch set (#13). Change subject: soc/amd/picasso: Create a hybrid romstage to begin in DRAM ...................................................................... soc/amd/picasso: Create a hybrid romstage to begin in DRAM Add the support files to begin execution in romstage and located in DRAM. Details for this implementation are found in Documentation/amd/picasso/family17.md. Combine steps typically found in bootblock, containing the reset vector and protected mode enable, with the parts of romstage that enable the console and cbmem. Duplicate the ROMSTAGE_ADDR symbol into Kconfig and give it a safe default value in DRAM. Define EARLYRAM values for stack and early storage prior to cbmem. (A subsequent patch to add an FSP driver will rely on the storage.) Remove all postcar support. Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/early_stack.S A src/soc/amd/picasso/hybrid_romstage.c M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/include/soc/romstage.h D src/soc/amd/picasso/romstage.c 7 files changed, 279 insertions(+), 138 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/33759/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/33759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976 Gerrit-Change-Number: 33759 Gerrit-PatchSet: 13 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/picasso: Update southbridge
by Marshall Dawson (Code Review) 05 Sep '19

05 Sep '19

Hello build bot (Jenkins), Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/33770 to look at the new patch set (#13). Change subject: soc/amd/picasso: Update southbridge ...................................................................... soc/amd/picasso: Update southbridge Picasso's FCH has many similarities to Stoney Ridge, so few changes are necessary. The most notable changes are: * Update the index values for the C00/C01 interrupt routing * FORCE_STPCLK_RETRY is not present * PCIB is not defined * FCH MISC Registers 0xfed80e00 numbering has changed * AOAC device assignment has changed * C-state base moves from PM register to MSR Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I69dfc4a875006639aa330385680d150331840e40 --- M src/soc/amd/picasso/include/soc/amd_pci_int_defs.h M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/smihandler.c M src/soc/amd/picasso/southbridge.c 5 files changed, 110 insertions(+), 166 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/33770/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/33770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69dfc4a875006639aa330385680d150331840e40 Gerrit-Change-Number: 33770 Gerrit-PatchSet: 13 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/ppc64: add arch_timer
by Marty E. Plummer (Code Review) 05 Sep '19

05 Sep '19

Marty E. Plummer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35171 ) Change subject: arch/ppc64: add arch_timer ...................................................................... arch/ppc64: add arch_timer Based on code from hostboot's timemgr.C file. looks right and the resultant assembly looks correct. Change-Id: I65d7be0fd384e69a069fe8278c313db914763b80 Signed-off-by: Marty E. Plummer <hanetzer(a)startmail.com> --- M src/arch/ppc64/Kconfig M src/arch/ppc64/Makefile.inc A src/arch/ppc64/arch_timer.c A src/arch/ppc64/include/arch/asm.h 4 files changed, 101 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/35171/1 diff --git a/src/arch/ppc64/Kconfig b/src/arch/ppc64/Kconfig index 0f65c0c..41ff074 100644 --- a/src/arch/ppc64/Kconfig +++ b/src/arch/ppc64/Kconfig @@ -20,3 +20,9 @@ select ARCH_PPC64 source "src/arch/ppc64/power8/Kconfig" +source "src/arch/ppc64/power9/Kconfig" + +config PPC64_USE_ARCH_TIMER + bool + default n + diff --git a/src/arch/ppc64/Makefile.inc b/src/arch/ppc64/Makefile.inc index 7a069cd..d6f0b77 100644 --- a/src/arch/ppc64/Makefile.inc +++ b/src/arch/ppc64/Makefile.inc @@ -30,6 +30,7 @@ bootblock-y += stages.c bootblock-y += boot.c bootblock-y += rom_media.c +bootblock-$(CONFIG_PPC64_USE_ARCH_TIMER) += arch_timer.c bootblock-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ @@ -55,6 +56,7 @@ romstage-y += boot.c romstage-y += stages.c romstage-y += rom_media.c +romstage-$(CONFIG_PPC64_USE_ARCH_TIMER) += arch_timer.c romstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ @@ -84,6 +86,7 @@ ramstage-y += stages.c ramstage-y += boot.c ramstage-y += tables.c +ramstage-$(CONFIG_PPC64_USE_ARCH_TIMER) += arch_timer.c ramstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ diff --git a/src/arch/ppc64/arch_timer.c b/src/arch/ppc64/arch_timer.c new file mode 100644 index 0000000..c988a34 --- /dev/null +++ b/src/arch/ppc64/arch_timer.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <timer.h> +#include <arch/asm.h> + +void timer_monotonic_get(struct mono_time *mt) +{ + // TODO: see src/kernel/timemgr.C + // looks right for now... + uint64_t value = raw_read_tb(); + uint64_t freq = 512000000ULL; + long usecs = (value * 1000000) / freq; + mono_time_set_usecs(mt, usecs); +} diff --git a/src/arch/ppc64/include/arch/asm.h b/src/arch/ppc64/include/arch/asm.h new file mode 100644 index 0000000..4692f87 --- /dev/null +++ b/src/arch/ppc64/include/arch/asm.h @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __PPC_PPC64_ASM_H +#define __PPC_PPC64_ASM_H + +#define ENDPROC(name) \ + .type name, % function; \ + END(name) + +#define ENTRY_WITH_ALIGN(name, bits) \ + .section.text.name, "ax", % progbits; \ + .global name; \ + .align bits; \ + name: + +#define ENTRY(name) ENTRY_WITH_ALIGN(name, 2) + +#define END(name) .size name, .- name + +/* Special Purpose Registers */ +#define SPRN_TBRL 268 +#define SPRN_TBRU 269 + + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + +#define MAKE_REGISTER_READ(reg) \ + static inline uint64_t raw_read_##reg(void) \ + { \ + uint64_t value; \ + __asm__ __volatile__("mfspr %0, " #reg "\n\t" : "=r"(value)); \ + return value; \ + } + +#define MAKE_REGISTER_WRITE(reg) \ + static inline void raw_write_##reg(uint64_t value) \ + { \ + __asm__ __volatile__("mtspr " #reg ", %0\n\t" : : "r"(value) : "memory"); \ + } + +#define MAKE_REGISTER_ACCESSORS(reg) \ + MAKE_REGISTER_READ(##reg) \ + MAKE_REGISTER_WRITE(##reg) + +static inline uint64_t raw_read_tb(void) +{ + uint64_t value; + __asm__ __volatile__("mfspr %0, %1\n\t" : "=r"(value) : "i"(SPRN_TBRL)); + return value; +} + +#endif /* __ASSEMBLER__ */ + +#endif /* __PPC_PPC64_ASM_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65d7be0fd384e69a069fe8278c313db914763b80 Gerrit-Change-Number: 35171 Gerrit-PatchSet: 1 Gerrit-Owner: Marty E. Plummer <hanetzer(a)startmail.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: drivers/spi/spi_flash.c: Add SPI vendor IDs
by Richard Spiegel (Code Review) 05 Sep '19

05 Sep '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35240 ) Change subject: drivers/spi/spi_flash.c: Add SPI vendor IDs ...................................................................... drivers/spi/spi_flash.c: Add SPI vendor IDs Currently SPI vendor IDs are magic numbers in spi_flash.c. These definitions are needed for AMD's fch_spi. So add the definitions to spi_generic.h and use it at spi_flash.c BUG=b:136595978 TEST=Build test of several platforms that don't use stoneyridge. Build and boot grunt (using stoneyridge new fch_spi). Change-Id: Ie39485d8c092151db8c9d88afaf02e19c507c93f Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/drivers/spi/spi_flash.c M src/include/spi-generic.h 2 files changed, 25 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/35240/1 diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index e2485ab..a7b10a8 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -100,7 +100,6 @@ #pragma GCC diagnostic push #if defined(__GNUC__) && !defined(__clang__) #pragma GCC diagnostic ignored "-Wstack-usage=" -#pragma GCC diagnostic ignored "-Wvla" #endif int spi_flash_cmd_write(const struct spi_slave *spi, const u8 *cmd, size_t cmd_len, const void *data, size_t data_len) @@ -282,38 +281,38 @@ } flashes[] = { /* Keep it sorted by define name */ #if CONFIG(SPI_FLASH_AMIC) - { 0, 0x37, spi_flash_probe_amic, }, + { 0, VENDOR_ID_AMIC, spi_flash_probe_amic, }, #endif #if CONFIG(SPI_FLASH_ATMEL) - { 0, 0x1f, spi_flash_probe_atmel, }, + { 0, VENDOR_ID_ATMEL, spi_flash_probe_atmel, }, #endif #if CONFIG(SPI_FLASH_EON) - { 0, 0x1c, spi_flash_probe_eon, }, + { 0, VENDOR_ID_EON, spi_flash_probe_eon, }, #endif #if CONFIG(SPI_FLASH_GIGADEVICE) - { 0, 0xc8, spi_flash_probe_gigadevice, }, + { 0, VENDOR_ID_GIGADEVICE, spi_flash_probe_gigadevice, }, #endif #if CONFIG(SPI_FLASH_MACRONIX) - { 0, 0xc2, spi_flash_probe_macronix, }, + { 0, VENDOR_ID_MACRONIX, spi_flash_probe_macronix, }, #endif #if CONFIG(SPI_FLASH_SPANSION) - { 0, 0x01, spi_flash_probe_spansion, }, + { 0, VENDOR_ID_SPANSION, spi_flash_probe_spansion, }, #endif #if CONFIG(SPI_FLASH_SST) - { 0, 0xbf, spi_flash_probe_sst, }, + { 0, VENDOR_ID_SST, spi_flash_probe_sst, }, #endif #if CONFIG(SPI_FLASH_STMICRO) - { 0, 0x20, spi_flash_probe_stmicro, }, + { 0, VENDOR_ID_STMICRO, spi_flash_probe_stmicro, }, #endif #if CONFIG(SPI_FLASH_WINBOND) - { 0, 0xef, spi_flash_probe_winbond, }, + { 0, VENDOR_ID_WINBOND, spi_flash_probe_winbond, }, #endif /* Keep it sorted by best detection */ #if CONFIG(SPI_FLASH_STMICRO) - { 0, 0xff, spi_flash_probe_stmicro, }, + { 0, VENDOR_ID_STMICRO_FF, spi_flash_probe_stmicro, }, #endif #if CONFIG(SPI_FLASH_ADESTO) - { 0, 0x1f, spi_flash_probe_adesto, }, + { 0, VENDOR_ID_ADESTO, spi_flash_probe_adesto, }, #endif }; #define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index ffd3d2d..2f26dc5 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -28,6 +28,20 @@ #include <stdint.h> #include <stddef.h> +/* SPI vendor IDs */ + +#define VENDOR_ID_ADESTO 0x1f +#define VENDOR_ID_AMIC 0x37 +#define VENDOR_ID_ATMEL 0x1f +#define VENDOR_ID_EON 0x1c +#define VENDOR_ID_GIGADEVICE 0xc8 +#define VENDOR_ID_MACRONIX 0xc2 +#define VENDOR_ID_SPANSION 0x01 +#define VENDOR_ID_SST 0xbf +#define VENDOR_ID_STMICRO 0x20 +#define VENDOR_ID_STMICRO_FF 0xff +#define VENDOR_ID_WINBOND 0xef + /* Controller-specific definitions: */ struct spi_ctrlr; -- To view, visit https://review.coreboot.org/c/coreboot/+/35240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie39485d8c092151db8c9d88afaf02e19c507c93f Gerrit-Change-Number: 35240 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST-ONLY]Update the memory timing table for Treeya to the 2T table....
by Peichao Li (Code Review) 05 Sep '19

05 Sep '19

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35116 ) Change subject: [TEST-ONLY]Update the memory timing table for Treeya to the 2T table. Rename the table from Liara specific to simply specifying that it's using 2T command rate ...................................................................... [TEST-ONLY]Update the memory timing table for Treeya to the 2T table. Rename the table from Liara specific to simply specifying that it's using 2T command rate BUG=139841929 TEST=build and do stress test Change-Id: I6e10b95c8aea50e68d8a3b710f30dda4f6b807d3 --- M src/mainboard/google/kahlee/OemCustomize.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/35116/1 diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c index 886e14f..1b33b03 100644 --- a/src/mainboard/google/kahlee/OemCustomize.c +++ b/src/mainboard/google/kahlee/OemCustomize.c @@ -39,7 +39,7 @@ PSO_END }; /* Liara-specific 2T memory configuration */ -static const PSO_ENTRY DDR4LiaraMemoryConfiguration[] = { +static const PSO_ENTRY DDR4_T2_MemoryConfiguration[] = { DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL), NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH), @@ -58,9 +58,9 @@ void OemPostParams(AMD_POST_PARAMS *PostParams) { - if (CONFIG(BOARD_GOOGLE_LIARA)) + if (CONFIG(BOARD_GOOGLE_LIARA) || CONFIG(BOARD_GOOGLE_TREEYA)) PostParams->MemConfig.PlatformMemoryConfiguration = - (PSO_ENTRY *)DDR4LiaraMemoryConfiguration; + (PSO_ENTRY *)DDR4_T2_MemoryConfiguration; else PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; -- To view, visit https://review.coreboot.org/c/coreboot/+/35116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e10b95c8aea50e68d8a3b710f30dda4f6b807d3 Gerrit-Change-Number: 35116 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/kahlee/treeya: override sku_id() function
by Peichao Li (Code Review) 04 Sep '19

04 Sep '19

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35214 ) Change subject: mb/google/kahlee/treeya: override sku_id() function ...................................................................... mb/google/kahlee/treeya: override sku_id() function override 'uint32_t sku_id(void)' so that lib_sysinfo.sku_id get a correct value in depthcharge. BUG=b:140010592 BRANCH=none TEST=boot treeya board, in depthcharge stage, lib_sysinfo.sku_id print correct value. Signed-off-by: Peichao Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I631f62021e8104a69a43667a811c9c23e3105596 --- M src/mainboard/google/kahlee/variants/baseboard/mainboard.c 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/35214/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c index 95274eb..30fcc8c 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/mainboard.c +++ b/src/mainboard/google/kahlee/variants/baseboard/mainboard.c @@ -15,6 +15,7 @@ #include <ec/google/chromeec/ec.h> #include <baseboard/variants.h> +#include <boardid.h> #include <cbfs.h> #include <gpio.h> #include <smbios.h> @@ -24,7 +25,7 @@ #include <device/pci_ops.h> #include <drivers/generic/bayhub/bh720.h> -uint8_t variant_board_sku(void) +uint32_t sku_id(void) { static int sku = -1; @@ -34,6 +35,11 @@ return sku; } +uint8_t variant_board_sku(void) +{ + return sku_id(); +} + void variant_mainboard_suspend_resume(void) { /* Enable backlight - GPIO 133 active low */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I631f62021e8104a69a43667a811c9c23e3105596 Gerrit-Change-Number: 35214 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/var/kindred: Update DPTF parameters and TDP PL1/PL2
by David Wu (Code Review) 04 Sep '19

04 Sep '19

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35131 ) Change subject: mb/google/hatch/var/kindred: Update DPTF parameters and TDP PL1/PL2 ...................................................................... mb/google/hatch/var/kindred: Update DPTF parameters and TDP PL1/PL2 Add TEMP_SENSOR_3 to DPTF, Update DPTF parameters and TDP PL1/PL2 values Cq-Depend: chromium:1751304 BUG=b:140127035 TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-ec chromeos-bootimage Change-Id: I1817e277f4641db6bedc8b640b1dc5d57502d5dd Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl M src/mainboard/google/hatch/variants/kindred/overridetree.cb 2 files changed, 121 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/35131/1 diff --git a/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl index f1f0943..6f79cd5 100644 --- a/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/kindred/include/variant/acpi/dptf.asl @@ -13,4 +13,121 @@ * GNU General Public License for more details. */ -#include <baseboard/acpi/dptf.asl> +#define DPTF_CPU_PASSIVE 90 +#define DPTF_CPU_CRITICAL 105 +#define DPTF_CPU_ACTIVE_AC0 95 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor - Charger" +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor - CPU" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 75 +#define DPTF_TSR1_ACTIVE_AC0 51 +#define DPTF_TSR1_ACTIVE_AC1 48 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 39 +#define DPTF_TSR1_ACTIVE_AC5 36 +#define DPTF_TSR1_ACTIVE_AC6 33 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - WIFI" +#define DPTF_TSR2_PASSIVE 65 +#define DPTF_TSR2_CRITICAL 75 +#define DPTF_TSR2_ACTIVE_AC0 55 +#define DPTF_TSR2_ACTIVE_AC1 50 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 100, 80, 70, 60, 50, 40, 30, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 80, 70, 60, 50, 40, 30, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 80, 70, 60, 50, 40, 30, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 100, 80, 0, 0, 0, 0, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on Charger (TSR0) */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on CPU (TSR1) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on WIFI (TSR2) */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 51000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 32000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/kindred/overridetree.cb b/src/mainboard/google/hatch/variants/kindred/overridetree.cb index a4ca176..f3f926d 100644 --- a/src/mainboard/google/hatch/variants/kindred/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kindred/overridetree.cb @@ -49,6 +49,9 @@ # Enable eMMC HS400 register "ScsEmmcHs400Enabled" = "1" + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "51" + device domain 0 on device pci 15.0 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/35131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1817e277f4641db6bedc8b640b1dc5d57502d5dd Gerrit-Change-Number: 35131 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2019