coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/timer: Fix cosmetic errors as per CB:35148 review
by Subrata Banik (Code Review) 03 Sep '19

03 Sep '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35234 ) Change subject: soc/intel/common/timer: Fix cosmetic errors as per CB:35148 review ...................................................................... soc/intel/common/timer: Fix cosmetic errors as per CB:35148 review BUG=b:139798422, b:129839774 TEST=Able to build and boot KBL/CML/ICL. Change-Id: I341eec13d275504545511904db0acd23ad34e940 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/timer/timer.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/35234/1 diff --git a/src/soc/intel/common/block/timer/timer.c b/src/soc/intel/common/block/timer/timer.c index 8fde541..70072cc 100644 --- a/src/soc/intel/common/block/timer/timer.c +++ b/src/soc/intel/common/block/timer/timer.c @@ -38,7 +38,7 @@ static unsigned long get_hardcoded_crystal_freq(void) { - unsigned int core_crystal_nominal_freq_khz; + unsigned long core_crystal_nominal_freq_khz = 0; /* * Denverton SoCs don't report crystal clock, and also don't support @@ -70,7 +70,7 @@ */ static unsigned long calculate_tsc_freq_from_core_crystal(void) { - unsigned int core_crystal_nominal_freq_khz; + unsigned long core_crystal_nominal_freq_khz; struct cpuid_result cpuidr_15h; if (get_max_cpuid_func() < 0x15) -- To view, visit https://review.coreboot.org/c/coreboot/+/35234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I341eec13d275504545511904db0acd23ad34e940 Gerrit-Change-Number: 35234 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/drallion: memory spd data debug
by EricR Lai (Code Review) 03 Sep '19

03 Sep '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35157 ) Change subject: mb/google/drallion: memory spd data debug ...................................................................... mb/google/drallion: memory spd data debug Add debug function for printing SPD data. This can be enable by unmark the SPD_DEBUG flag. BUG=b:139397313 BRANCH=N/A TEST=Tested the same code on Hatch and checked cbmem log. Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ie8e448f6f53db4ea0fd2ffdc58699064716c1d57 --- M src/mainboard/google/drallion/romstage.c 1 file changed, 114 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/35157/1 diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c index 20eee7f..12cc3b3 100644 --- a/src/mainboard/google/drallion/romstage.c +++ b/src/mainboard/google/drallion/romstage.c @@ -17,6 +17,117 @@ #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> +//#define SPD_DEBUG +#ifdef SPD_DEBUG +#include <variant/gpio.h> +#include <console/console.h> +#include <cbfs.h> + +/* Offset to identify DRAM type. */ +#define SPD_DRAM_TYPE_OFF 2 +#define SPD_DRAM_DDR4 0x0c + +/* Length of SPD data. */ +#define SPD_LEN_DDR4 512 + +/* Fields that are common across different memory types. */ +#define SPD_DENSITY_BANKS_OFF 4 +#define SPD_ADDRESSING_OFF 5 +#define SPD_PART_LEN 18 + +/* Fields that are different depending upon memory type. */ +#define SPD_ORG_OFF_DDR4 12 +#define SPD_BUSW_OFF_DDR4 13 +#define SPD_PART_OFF_DDR4 329 + +static const struct dram_info { + const char *str; + uint16_t type_code; + uint16_t len; + uint16_t org_off; + uint16_t busw_off; + uint16_t part_off; +} spd_info = { + .str = "DDR4", + .type_code = SPD_DRAM_DDR4, + .len = SPD_LEN_DDR4, + .org_off = SPD_ORG_OFF_DDR4, + .busw_off = SPD_BUSW_OFF_DDR4, + .part_off = SPD_PART_OFF_DDR4, +}; + +static void mainboard_print_spd_info(const uint8_t *spd) +{ + const int spd_banks[10] = { 4, 8, -1, -1, 8, 16, -1, -1, 16, 32 }; + const int spd_capmb[10] = { 1, 2, 4, 8, 16, 32, 64, 128, 48, 96 }; + const int spd_rows[8] = { 12, 13, 14, 15, 16, 17, 18, -1 }; + const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; + const int spd_ranks[8] = { 1, 2, 3, 4, 5, 6, 7, 8 }; + const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; + const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + char spd_name[SPD_PART_LEN+1] = { 0 }; + const struct dram_info *info = &spd_info; + + /* Module type */ + printk(BIOS_INFO, "SPD: module type is %s\n", info->str); + + int banks = spd_banks[(spd[SPD_DENSITY_BANKS_OFF] >> 4) & 7]; + int capmb = spd_capmb[spd[SPD_DENSITY_BANKS_OFF] & 7] * 256; + int rows = spd_rows[(spd[SPD_ADDRESSING_OFF] >> 3) & 7]; + int cols = spd_cols[spd[SPD_ADDRESSING_OFF] & 7]; + int ranks = spd_ranks[(spd[info->org_off] >> 3) & 7]; + int devw = spd_devw[spd[info->org_off] & 7]; + int busw = spd_busw[spd[info->busw_off] & 7]; + + /* Module Part Number */ + memcpy(spd_name, &spd[info->part_off], SPD_PART_LEN); + spd_name[SPD_PART_LEN] = 0; + printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); + + printk(BIOS_INFO, + "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", + banks, ranks, rows, cols, capmb); + printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", + devw, busw); + + if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { + /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ + printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", + capmb / 8 * busw / devw * ranks); + } +} + +static void mainboard_debug_spd_data(void) +{ + char *spd_file; + size_t spd_file_len; + int spd_index; + const size_t spd_len = spd_info.len; + const char *spd_bin = "spd.bin"; + + spd_index = variant_memory_sku(); + + printk(BIOS_INFO, "SPD: index %d\n", spd_index); + + /* Load SPD data from CBFS */ + spd_file = cbfs_boot_map_with_leak(spd_bin, CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + /* make sure we have at least one SPD in the file. */ + if (spd_file_len < spd_len) + die("Missing SPD data."); + + /* Make sure we did not overrun the buffer */ + if (spd_file_len < ((spd_index + 1) * spd_len)) + die("Invalid SPD index."); + + spd_index *= spd_len; + mainboard_print_spd_info((uint8_t *)(spd_file + spd_index)); +} +#endif + static const struct cnl_mb_cfg memcfg = { /* Access memory info through SMBUS. */ .spd[0] = { @@ -58,6 +169,8 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { wilco_ec_romstage_init(); - +#ifdef SPD_DEBUG + mainboard_debug_spd_data(); +#endif cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35157 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8e448f6f53db4ea0fd2ffdc58699064716c1d57 Gerrit-Change-Number: 35157 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2
by Hank Lin (Code Review) 03 Sep '19

03 Sep '19

Hank Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34743 ) Change subject: mb/google/hatch/variants/helios: Update DPTF parameters and TDP PL1/PL2 ...................................................................... Patch Set 2: > Patch Set 2: > > (1 comment) In RFQ, it is evaluated that the system must conform to the "Skin pass" state, and the CPU wattage needs to be below 10w. The current setting is PL1: 8/13w. There are two factors for 13w. 1. Thermal module capacity considerations 2. Avoid the sudden drop of wattage, resulting in the drop of test score After discussing with ASUS customers, import EVT first with PL1:8/13w settings DVT verification will be adjusted according to the situation. -- To view, visit https://review.coreboot.org/c/coreboot/+/34743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7a96c33ce710c32b57e2ad8066830ff83398c57 Gerrit-Change-Number: 34743 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 03 Sep 2019 08:01:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors
by Sumeet R Pawnikar (Code Review) 03 Sep '19

03 Sep '19

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35127 ) Change subject: soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors ...................................................................... soc/intel/common/acpi/dptf: Add fan based active cooling for TSR sensors Add fan based active cooling for TSR sensors temperature range. BUG=None BRANCH=None TEST=Verified Fan control functionality for TSR0/1 on Hatch. Change-Id: I957ae96cf6fa7d2467e73155d64f76a6bd652e31 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/common/acpi/dptf/thermal.asl 1 file changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/35127/1 diff --git a/src/soc/intel/common/acpi/dptf/thermal.asl b/src/soc/intel/common/acpi/dptf/thermal.asl index ca128c9..534ab9b 100644 --- a/src/soc/intel/common/acpi/dptf/thermal.asl +++ b/src/soc/intel/common/acpi/dptf/thermal.asl @@ -155,6 +155,51 @@ { \_SB.PCI0.LPCB.EC0.PATD (TMPI) } + +#ifdef DPTF_ENABLE_FAN_CONTROL +#ifdef DPTF_TSR0_ACTIVE_AC0 + Method (_AC0) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC0)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC1 + Method (_AC1) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC1)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC2 + Method (_AC2) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC2)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC3 + Method (_AC3) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC3)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC4 + Method (_AC4) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC4)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC5 + Method (_AC5) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC5)) + } +#endif +#ifdef DPTF_TSR0_ACTIVE_AC6 + Method (_AC6) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC6)) + } +#endif +#endif } #endif @@ -219,6 +264,39 @@ { \_SB.PCI0.LPCB.EC0.PATD (TMPI) } + +#ifdef DPTF_ENABLE_FAN_CONTROL +#ifdef DPTF_TSR1_ACTIVE_AC0 + Method (_AC0) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC0)) + } +#endif +#ifdef DPTF_TSR1_ACTIVE_AC1 + Method (_AC1) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC1)) + } +#endif +#ifdef DPTF_TSR1_ACTIVE_AC2 + Method (_AC2) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC2)) + } +#endif +#ifdef DPTF_TSR1_ACTIVE_AC3 + Method (_AC3) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC3)) + } +#endif +#ifdef DPTF_TSR1_ACTIVE_AC4 + Method (_AC4) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR1_ACTIVE_AC4)) + } +#endif +#endif } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I957ae96cf6fa7d2467e73155d64f76a6bd652e31 Gerrit-Change-Number: 35127 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/timer: Make TSC frequency calculation dynamically
by Subrata Banik (Code Review) 03 Sep '19

03 Sep '19

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Change in coreboot[master]: soc/intel/common/timer: Make TSC frequency calculation dynamically
by Subrata Banik (Code Review) 03 Sep '19

03 Sep '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35148 ) Change subject: soc/intel/common/timer: Make TSC frequency calculation dynamically ...................................................................... Patch Set 12: (3 comments) https://review.coreboot.org/c/coreboot/+/35148/11/src/soc/intel/common/bloc… File src/soc/intel/common/block/timer/timer.c: https://review.coreboot.org/c/coreboot/+/35148/11/src/soc/intel/common/bloc… PS11, Line 41: int > i will push another patch a s this been merged to fix those cosmetic errors, these are valid comment […] Done https://review.coreboot.org/c/coreboot/+/35148/11/src/soc/intel/common/bloc… PS11, Line 41: ; > Set it to 0 here in case this function is called for a processor model other than CPU_MODEL_INTEL_AT […] Done https://review.coreboot.org/c/coreboot/+/35148/11/src/soc/intel/common/bloc… PS11, Line 73: int > long Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Gerrit-Change-Number: 35148 Gerrit-PatchSet: 12 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 03 Sep 2019 06:22:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/x4x/raminit: Move dummy reads after JEDEC init
by Felix Held (Code Review) 03 Sep '19

03 Sep '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/20979 ) Change subject: nb/intel/x4x/raminit: Move dummy reads after JEDEC init ...................................................................... Patch Set 10: Code-Review+2 (3 comments) https://review.coreboot.org/c/coreboot/+/20979/8/src/northbridge/intel/x4x/… File src/northbridge/intel/x4x/raminit_ddr23.c: https://review.coreboot.org/c/coreboot/+/20979/8/src/northbridge/intel/x4x/… PS8, Line 2163: (ch << 29) | (r * 0x08000000) > FYI: I'm waiting for this to be addressed before I'll give this patch a +2 Done https://review.coreboot.org/c/coreboot/+/20979/8/src/northbridge/intel/x4x/… PS8, Line 2164: 0x800000 > me too Done https://review.coreboot.org/c/coreboot/+/20979/9/src/northbridge/intel/x4x/… File src/northbridge/intel/x4x/raminit_ddr23.c: https://review.coreboot.org/c/coreboot/+/20979/9/src/northbridge/intel/x4x/… PS9, Line 2163: test_address(ch, r) | 0x800000 | (bank << 12) > probably some parenthesis are missing around this statement, so that not only the first element gets […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/20979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8069f9c08ad5e5268ddbe3711d58bc42522f938c Gerrit-Change-Number: 20979 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Sep 2019 05:51:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/timer: Make TSC frequency calculation dynamically
by Subrata Banik (Code Review) 03 Sep '19

03 Sep '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35148 ) Change subject: soc/intel/common/timer: Make TSC frequency calculation dynamically ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/c/coreboot/+/35148/11/src/soc/intel/common/bloc… File src/soc/intel/common/block/timer/timer.c: https://review.coreboot.org/c/coreboot/+/35148/11/src/soc/intel/common/bloc… PS11, Line 41: int > long to match it with the return type i will push another patch a s this been merged to fix those cosmetic errors, these are valid comments. Although DNV is seperate case and hopefully we wouldn't see anything else but its better to have coverage -- To view, visit https://review.coreboot.org/c/coreboot/+/35148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Gerrit-Change-Number: 35148 Gerrit-PatchSet: 12 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 03 Sep 2019 02:22:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/timer: Make TSC frequency calculation dynamically
by Subrata Banik (Code Review) 03 Sep '19

03 Sep '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35148 ) Change subject: soc/intel/common/timer: Make TSC frequency calculation dynamically ...................................................................... Patch Set 12: > Patch Set 11: > > why "soc/" ? can this be also used for the other intel's CPU ? > (model_1067x, model_6fx, model_f6x, f4x,..) i could see this recommendation been introduced after SPT PCH so i'm not very sure if CPUID.15h can support for older chipsets. Can you please take a look after porting the same if works then move it to Intel common? -- To view, visit https://review.coreboot.org/c/coreboot/+/35148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Gerrit-Change-Number: 35148 Gerrit-PatchSet: 12 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 03 Sep 2019 02:18:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Add Razer Blade Stealth (2016) H2U
by build bot (Jenkins) (Code Review) 03 Sep '19

03 Sep '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34475 ) Change subject: Add Razer Blade Stealth (2016) H2U ...................................................................... Patch Set 34: (2 comments) https://review.coreboot.org/c/coreboot/+/34475/34/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c: https://review.coreboot.org/c/coreboot/+/34475/34/src/mainboard/razer/blade… PS34, Line 26: {0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00}}; space required after that close brace '}' https://review.coreboot.org/c/coreboot/+/34475/34/src/mainboard/razer/blade… PS34, Line 33: const u8 dqs_map[2][8] = {{0, 1, 3, 2, 4, 5, 6, 7}, {1, 0, 4, 5, 2, 3, 6, 7}}; space required after that close brace '}' -- To view, visit https://review.coreboot.org/c/coreboot/+/34475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Gerrit-Change-Number: 34475 Gerrit-PatchSet: 34 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 02 Sep 2019 22:32:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit September 2019