coreboot-gerrit September 2019

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Change in coreboot[master]: device/device_simple: Warn about secondary bus usage
by Nico Huber (Code Review) 02 Sep '19

02 Sep '19

Nico Huber has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/26291 ) Change subject: device/device_simple: Warn about secondary bus usage ...................................................................... Abandoned dev_find_slot() is not used as much anymore -- To view, visit https://review.coreboot.org/c/coreboot/+/26291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I312d3506fc2d6ce8cc28cf9557b21d1c1cbd2d12 Gerrit-Change-Number: 26291 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...libgfxinit[master]: gma display_probing: End probing after all ports failed
by Nico Huber (Code Review) 02 Sep '19

02 Sep '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/32728 Change subject: gma display_probing: End probing after all ports failed ...................................................................... gma display_probing: End probing after all ports failed In case of failure, we kept trying the last port in the list for further pipelines. Fix that. Change-Id: Id434492a7186f3b9431fd98dc16c0a7aa0e92501 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-display_probing.adb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/28/32728/1 diff --git a/common/hw-gfx-gma-display_probing.adb b/common/hw-gfx-gma-display_probing.adb index cd2a452..d21b277 100644 --- a/common/hw-gfx-gma-display_probing.adb +++ b/common/hw-gfx-gma-display_probing.adb @@ -1,5 +1,6 @@ -- -- Copyright (C) 2015-2016 secunet Security Networks AG +-- Copyright (C) 2019 Nico Huber <nico.h(a)gmx.de> -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -183,6 +184,7 @@ for Pipe in Pipe_Index range Pipe_Index'First .. Pipe_Index'Min (Max_Pipe, Config.Max_Pipe) loop + Success := False; while Ports (Port_Idx) /= Disabled loop if not Port_Configured (Configs, Ports (Port_Idx)) and (not Has_Sibling_Port (Ports (Port_Idx)) or @@ -198,6 +200,7 @@ exit when Success; end loop; + exit when not Success; end loop; -- Restore power settings -- To view, visit https://review.coreboot.org/c/libgfxinit/+/32728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: Id434492a7186f3b9431fd98dc16c0a7aa0e92501 Gerrit-Change-Number: 32728 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in libgfxinit[master]: gma pipe setup: Fix secondary pipe cursors <= Sandy Bridge
by Nico Huber (Code Review) 02 Sep '19

02 Sep '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/libgfxinit/+/27154 ) Change subject: gma pipe setup: Fix secondary pipe cursors <= Sandy Bridge ...................................................................... gma pipe setup: Fix secondary pipe cursors <= Sandy Bridge The secondary cursor registers used to have a different offset. Change-Id: I4d79f59a8cb693d73d6da666525f091021efb4fd Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/27154 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Reto Buerki <reet(a)codelabs.ch> --- M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma-pipe_setup.adb M common/hw-gfx-gma-pipe_setup.ads M common/hw-gfx-gma-registers.ads M common/hw-gfx-gma.ads 5 files changed, 81 insertions(+), 35 deletions(-) Approvals: Nico Huber: Verified Reto Buerki: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 2667333..8711e54 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -155,7 +155,7 @@ Has_Plane_Control : <genbool> := Broxton_On; Has_DSP_Linoff : <genbool> := Up_To_Ironlake; Has_PF_Pipe_Select : <ilkhswbool> := CPU_Ivybridge or CPU_Haswell; - Has_Cursor_FBC_Control : <ilkbool> := Ivybridge_On; + Has_Ivybridge_Cursors : <ilkbool> := Ivybridge_On; VGA_Plane_Workaround : <ilkbool> := CPU_Ivybridge; Has_GMCH_DP_Transcoder : <genbool> := Gen_G45; Has_GMCH_VGACNTRL : <genbool> := Gen_G45; diff --git a/common/hw-gfx-gma-pipe_setup.adb b/common/hw-gfx-gma-pipe_setup.adb index bb7b989..000c536 100644 --- a/common/hw-gfx-gma-pipe_setup.adb +++ b/common/hw-gfx-gma-pipe_setup.adb @@ -15,7 +15,6 @@ with HW.Debug; with GNAT.Source_Info; -with HW.GFX.GMA.Config; with HW.GFX.GMA.Transcoder; package body HW.GFX.GMA.Pipe_Setup is @@ -352,7 +351,7 @@ -- on some platforms writing CUR_CTL disables self-arming of CUR_POS -- so keep it first Registers.Write - (Register => Controllers (Pipe).CUR_CTL, + (Register => Cursors (Pipe).CTL, Value => CUR_CTL_PIPE_SELECT (Pipe) or CUR_CTL_MODE (Cursor.Mode, Cursor.Size)); Place_Cursor (Pipe, FB, Cursor); @@ -376,11 +375,11 @@ Y := -Width; end if; Registers.Write - (Register => Controllers (Pipe).CUR_POS, + (Register => Cursors (Pipe).POS, Value => CUR_POS_Y (Y) or CUR_POS_X (X)); -- write to CUR_BASE always arms other CUR_* registers Registers.Write - (Register => Controllers (Pipe).CUR_BASE, + (Register => Cursors (Pipe).BASE, Value => Shift_Left (Word32 (Cursor.GTT_Offset), 12)); end Place_Cursor; @@ -699,11 +698,13 @@ ---------------------------------------------------------------------------- - procedure Planes_Off (Controller : Controller_Type) is + procedure Planes_Off (Controller : Controller_Type; CUR : Cursor_Regs) + is + use type Registers.Registers_Invalid_Index; begin - Registers.Write (Controller.CUR_CTL, 16#0000_0000#); - if Config.Has_Cursor_FBC_Control then - Registers.Write (Controller.CUR_FBC_CTL, 16#0000_0000#); + Registers.Write (CUR.CTL, 16#0000_0000#); + if CUR.FBC_CTL /= Registers.Invalid_Register then + Registers.Write (CUR.FBC_CTL, 16#0000_0000#); end if; Registers.Unset_Mask (Controller.SPCNTR, DSPCNTR_ENABLE); if Config.Has_Plane_Control then @@ -720,7 +721,7 @@ begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); - Planes_Off (Controllers (Pipe)); + Planes_Off (Controllers (Pipe), Cursors (Pipe)); Transcoder.Off (Pipe); Panel_Fitter_Off (Controllers (Pipe)); Transcoder.Clk_Off (Pipe); @@ -746,7 +747,7 @@ Legacy_VGA_Off; for Pipe in Pipe_Index loop - Planes_Off (Controllers (Pipe)); + Planes_Off (Controllers (Pipe), Cursors (Pipe)); Transcoder.Off (Pipe); Panel_Fitter_Off (Controllers (Pipe)); Transcoder.Clk_Off (Pipe); diff --git a/common/hw-gfx-gma-pipe_setup.ads b/common/hw-gfx-gma-pipe_setup.ads index fe877ad..0edb0c9 100644 --- a/common/hw-gfx-gma-pipe_setup.ads +++ b/common/hw-gfx-gma-pipe_setup.ads @@ -12,6 +12,7 @@ -- GNU General Public License for more details. -- +with HW.GFX.GMA.Config; with HW.GFX.GMA.Registers; use type HW.Int32; @@ -78,10 +79,6 @@ DSPSURF : Registers.Registers_Index; DSPTILEOFF : Registers.Registers_Index; SPCNTR : Registers.Registers_Index; - CUR_CTL : Registers.Registers_Index; - CUR_BASE : Registers.Registers_Index; - CUR_POS : Registers.Registers_Index; - CUR_FBC_CTL : Registers.Registers_Index; -- Skylake registers (partially aliased) PLANE_CTL : Registers.Registers_Index; PLANE_OFFSET : Registers.Registers_Index; @@ -117,10 +114,6 @@ DSPSURF => Registers.DSPASURF, DSPTILEOFF => Registers.DSPATILEOFF, SPCNTR => Registers.SPACNTR, - CUR_CTL => Registers.CUR_CTL_A, - CUR_BASE => Registers.CUR_BASE_A, - CUR_POS => Registers.CUR_POS_A, - CUR_FBC_CTL => Registers.CUR_FBC_CTL_A, PLANE_CTL => Registers.DSPACNTR, PLANE_OFFSET => Registers.DSPATILEOFF, PLANE_POS => Registers.PLANE_POS_1_A, @@ -166,10 +159,6 @@ DSPSURF => Registers.DSPBSURF, DSPTILEOFF => Registers.DSPBTILEOFF, SPCNTR => Registers.SPBCNTR, - CUR_CTL => Registers.CUR_CTL_B, - CUR_BASE => Registers.CUR_BASE_B, - CUR_POS => Registers.CUR_POS_B, - CUR_FBC_CTL => Registers.CUR_FBC_CTL_B, PLANE_CTL => Registers.DSPBCNTR, PLANE_OFFSET => Registers.DSPBTILEOFF, PLANE_POS => Registers.PLANE_POS_1_B, @@ -215,10 +204,6 @@ DSPSURF => Registers.DSPCSURF, DSPTILEOFF => Registers.DSPCTILEOFF, SPCNTR => Registers.SPCCNTR, - CUR_CTL => Registers.CUR_CTL_C, - CUR_BASE => Registers.CUR_BASE_C, - CUR_POS => Registers.CUR_POS_C, - CUR_FBC_CTL => Registers.CUR_FBC_CTL_C, PLANE_CTL => Registers.DSPCCNTR, PLANE_OFFSET => Registers.DSPCTILEOFF, PLANE_POS => Registers.PLANE_POS_1_C, @@ -252,4 +237,40 @@ Registers.CUR_WM_C_6, Registers.CUR_WM_C_7))); + type Cursor_Regs is record + CTL : Registers.Registers_Index; + BASE : Registers.Registers_Index; + POS : Registers.Registers_Index; + FBC_CTL : Registers.Registers_Invalid_Index; + end record; + + function Cursors (Pipe : Pipe_Index) return Cursor_Regs is + (if not Config.Has_Ivybridge_Cursors then + (if Pipe = Primary then + (CTL => Registers.CURACNTR, + BASE => Registers.CURABASE, + POS => Registers.CURAPOS, + FBC_CTL => Registers.Invalid_Register) + else + (CTL => Registers.CURBCNTR, + BASE => Registers.CURBBASE, + POS => Registers.CURBPOS, + FBC_CTL => Registers.Invalid_Register)) + else + (if Pipe = Primary then + (CTL => Registers.CUR_CTL_A, + BASE => Registers.CUR_BASE_A, + POS => Registers.CUR_POS_A, + FBC_CTL => Registers.CUR_FBC_CTL_A) + elsif Pipe = Secondary then + (CTL => Registers.CUR_CTL_B, + BASE => Registers.CUR_BASE_B, + POS => Registers.CUR_POS_B, + FBC_CTL => Registers.CUR_FBC_CTL_B) + else + (CTL => Registers.CUR_CTL_C, + BASE => Registers.CUR_BASE_C, + POS => Registers.CUR_POS_C, + FBC_CTL => Registers.CUR_FBC_CTL_C))); + end HW.GFX.GMA.Pipe_Setup; diff --git a/common/hw-gfx-gma-registers.ads b/common/hw-gfx-gma-registers.ads index ac0f023..5cffe76 100644 --- a/common/hw-gfx-gma-registers.ads +++ b/common/hw-gfx-gma-registers.ads @@ -473,6 +473,9 @@ CUR_BASE_A, CUR_POS_A, CUR_FBC_CTL_A, + CURBCNTR, + CURBBASE, + CURBPOS, CUR_WM_A_0, CUR_WM_A_1, CUR_WM_A_2, @@ -927,6 +930,9 @@ PS_CTRL_2_B => 16#06_8a80# / Register_Width, -- cursor control + CURBCNTR => 16#07_00c0# / Register_Width, -- <= SNB + CURBBASE => 16#07_00c4# / Register_Width, -- <= SNB + CURBPOS => 16#07_00c8# / Register_Width, -- <= SNB CUR_CTL_B => 16#07_1080# / Register_Width, CUR_BASE_B => 16#07_1084# / Register_Width, CUR_POS_B => 16#07_1088# / Register_Width, @@ -1632,6 +1638,9 @@ GMCH_ADPA : constant Registers_Index := FDI_TX_CTL_B; GMCH_HDMIB : constant Registers_Index := GMCH_SDVOB; GMCH_HDMIC : constant Registers_Index := GMCH_SDVOC; + CURACNTR : constant Registers_Index := CUR_CTL_A; + CURABASE : constant Registers_Index := CUR_BASE_A; + CURAPOS : constant Registers_Index := CUR_POS_A; --------------------------------------------------------------------------- diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 8b1c85a..f9444e8 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -129,12 +129,19 @@ Proof_In => (Init_State)), Pre => Is_Initialized; + pragma Warnings (GNATprove, Off, "no check message justified by this", + Reason => "see Annotate aspects."); procedure Update_Cursor (Pipe : Pipe_Index; Cursor : Cursor_Type) with Global => - (In_Out => (State, Device_State), + (Input => (Config_State), + In_Out => (State, Device_State), Proof_In => (Init_State)), - Pre => Is_Initialized; + Pre => Is_Initialized, + Annotate => + (GNATprove, Intentional, + "global input ""GMA.Config_State"" of ""Update_Cursor"" not read", + "Reading of Config_State depends on the platform configuration."); procedure Place_Cursor (Pipe : Pipe_Index; @@ -142,9 +149,14 @@ Y : Cursor_Pos) with Global => - (In_Out => (State, Device_State), + (Input => (Config_State), + In_Out => (State, Device_State), Proof_In => (Init_State)), - Pre => Is_Initialized; + Pre => Is_Initialized, + Annotate => + (GNATprove, Intentional, + "global input ""GMA.Config_State"" of ""Place_Cursor"" not read", + "Reading of Config_State depends on the platform configuration."); procedure Move_Cursor (Pipe : Pipe_Index; @@ -152,9 +164,14 @@ Y : Cursor_Pos) with Global => - (In_Out => (State, Device_State), + (Input => (Config_State), + In_Out => (State, Device_State), Proof_In => (Init_State)), - Pre => Is_Initialized; + Pre => Is_Initialized, + Annotate => + (GNATprove, Intentional, + "global input ""GMA.Config_State"" of ""Move_Cursor"" not read", + "Reading of Config_State depends on the platform configuration."); ---------------------------------------------------------------------------- @@ -191,8 +208,6 @@ Proof_In => (Init_State)), Pre => Is_Initialized and HW.Config.Dynamic_MMIO; - pragma Warnings (GNATprove, Off, "no check message justified by this", - Reason => "see Annotate aspects."); procedure Map_Linear_FB (Linear_FB : out Word64; FB : in Framebuffer_Type) with Global => -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I4d79f59a8cb693d73d6da666525f091021efb4fd Gerrit-Change-Number: 27154 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Reto Buerki <reet(a)codelabs.ch> Gerrit-MessageType: merged

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Change in libgfxinit[master]: gfx_test: Refactor to allow Restrictions (No_Elaboration_Code)
by Nico Huber (Code Review) 02 Sep '19

02 Sep '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/libgfxinit/+/27146 ) Change subject: gfx_test: Refactor to allow Restrictions (No_Elaboration_Code) ...................................................................... gfx_test: Refactor to allow Restrictions (No_Elaboration_Code) Move the `Ada.Numerics.Discrete_Random.Generator` into the Main() procedure. Change-Id: I63c72501fd7d49574042fc5a459d6751a776a1f1 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/libgfxinit/+/27146 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M gfxtest/hw-gfx-gma-gfx_test.adb 1 file changed, 31 insertions(+), 25 deletions(-) Approvals: Nico Huber: Verified Angel Pons: Looks good to me, approved diff --git a/gfxtest/hw-gfx-gma-gfx_test.adb b/gfxtest/hw-gfx-gma-gfx_test.adb index 736b93d..fc1868f 100644 --- a/gfxtest/hw-gfx-gma-gfx_test.adb +++ b/gfxtest/hw-gfx-gma-gfx_test.adb @@ -20,8 +20,8 @@ Seed : constant := 12345; package Rand_P is new Ada.Numerics.Discrete_Random (Natural); - Gen : Rand_P.Generator; - function Rand return Int32 is (Int32 (Rand_P.Random (Gen))); + function Rand (Gen : Rand_P.Generator) + return Int32 is (Int32 (Rand_P.Random (Gen))); Start_X : constant := 0; Start_Y : constant := 0; @@ -341,7 +341,7 @@ Pipes : GMA.Pipe_Configs; - procedure Prepare_Configs (Rotation : Rotation_Type) + procedure Prepare_Configs (Rotation : Rotation_Type; Gen : Rand_P.Generator) is use type HW.GFX.GMA.Port_Type; @@ -366,7 +366,7 @@ end if; end if; Prepare_Cursors (Cursors (Pipe), Offset); - Pipes (Pipe).Cursor := Cursors (Pipe) (Cursor_Size'Val (Rand mod 3)); + Pipes (Pipe).Cursor := Cursors (Pipe) (Cursor_Size'Val (Rand (Gen) mod 3)); end loop; GMA.Dump_Configs (Pipes); @@ -427,18 +427,14 @@ Color : Pipe_Index; Size : Cursor_Size; end record; - function Cursor_Rand return Int32 is (Rand mod 51 - 25); - Cursor_Infos : array (Pipe_Index) of Cursor_Info := - (others => - (Color => Pipe_Index'Val (Rand mod 3), - Size => Cursor_Size'Val (Rand mod 3), - X_Velo => 3 * Cursor_Rand, - Y_Velo => 3 * Cursor_Rand, - others => Cursor_Rand)); + function Cursor_Rand (Gen : Rand_P.Generator) + return Int32 is (Rand (Gen) mod 51 - 25); + Cursor_Infos : array (Pipe_Index) of Cursor_Info; procedure Move_Cursors (Pipes : in out GMA.Pipe_Configs; - Time_MS : in Natural) + Time_MS : in Natural; + Gen : in Rand_P.Generator) is procedure Select_New_Cursor (P : in Pipe_Index; @@ -448,12 +444,12 @@ Old_C : constant Cursor_Type := C; begin -- change either size or color - if Rand mod 2 = 0 then + if Rand (Gen) mod 2 = 0 then CI.Color := Pipe_Index'Val - ((Pipe_Index'Pos (CI.Color) + 1 + Rand mod 2) mod 3); + ((Pipe_Index'Pos (CI.Color) + 1 + Rand (Gen) mod 2) mod 3); else CI.Size := Cursor_Size'Val - ((Cursor_Size'Pos (CI.Size) + 1 + Rand mod 2) mod 3); + ((Cursor_Size'Pos (CI.Size) + 1 + Rand (Gen) mod 2) mod 3); end if; C := Cursors (CI.Color) (CI.Size); C.Center_X := Old_C.Center_X; @@ -482,8 +478,8 @@ Update : Boolean := False; begin if Cnt mod 16 = 0 then - CI.X_Acc := Cursor_Rand; - CI.Y_Acc := Cursor_Rand; + CI.X_Acc := Cursor_Rand (Gen); + CI.Y_Acc := Cursor_Rand (Gen); end if; CI.X_Velo := CI.X_Velo + CI.X_Acc; CI.Y_Velo := CI.Y_Velo + CI.Y_Acc; @@ -537,6 +533,8 @@ Dev_Init, Initialized : Boolean; + Gen : Rand_P.Generator; + function iopl (level : Interfaces.C.int) return Interfaces.C.int; pragma Import (C, iopl, "iopl"); begin @@ -584,7 +582,7 @@ if Initialized then Backup_GTT; - Prepare_Configs (Rotation); + Prepare_Configs (Rotation, Gen); GMA.Update_Outputs (Pipes); @@ -600,6 +598,14 @@ end loop; end loop; + Cursor_Infos := + (others => + (Color => Pipe_Index'Val (Rand (Gen) mod 3), + Size => Cursor_Size'Val (Rand (Gen) mod 3), + X_Velo => 3 * Cursor_Rand (Gen), + Y_Velo => 3 * Cursor_Rand (Gen), + others => Cursor_Rand (Gen))); + if Delay_MS < Primary_Delay_MS + Secondary_Delay_MS then Script_Cursors (Pipes, Delay_MS); else -- getting bored? @@ -609,10 +615,10 @@ New_Pipes : GMA.Pipe_Configs := Pipes; function Rand_Div (Num : Position_Type) return Position_Type is - (case Rand mod 4 is - when 3 => Rand mod Num / 3, - when 2 => Rand mod Num / 2, - when 1 => Rand mod Num, + (case Rand (Gen) mod 4 is + when 3 => Rand (Gen) mod Num / 3, + when 2 => Rand (Gen) mod Num / 2, + when 1 => Rand (Gen) mod Num, when others => 0); begin Rand_P.Reset (Gen, Seed); @@ -645,10 +651,10 @@ end loop; GMA.Dump_Configs (New_Pipes); GMA.Update_Outputs (New_Pipes); - Move_Cursors (New_Pipes, Secondary_Delay_MS); + Move_Cursors (New_Pipes, Secondary_Delay_MS, Gen); Delay_MS := Delay_MS - Secondary_Delay_MS; end loop; - Move_Cursors (New_Pipes, Delay_MS); + Move_Cursors (New_Pipes, Delay_MS, Gen); end; end if; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I63c72501fd7d49574042fc5a459d6751a776a1f1 Gerrit-Change-Number: 27146 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/skylake: enable GMM in devicetree
by Maxim Polyakov (Code Review) 02 Sep '19

02 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35168 ) Change subject: soc/intel/skylake: enable GMM in devicetree ...................................................................... soc/intel/skylake: enable GMM in devicetree Enables Gaussian Mixture Model (GMM) only if the corresponding pci device is enabled in the device tree Change-Id: I21409adf85b70bccc30dd8e12a03ad7921544b3c Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/include/soc/pci_devs.h 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/35168/1 diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 064f71e..c54de3a 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -441,6 +441,10 @@ dev->enabled = 0; params->XdciEnable = dev->enabled; + /* Enable or disable Gaussian Mixture Model in devicetree */ + dev = pcidev_path_on_root(SA_DEVFN_GMM); + params->GmmEnable = dev->enabled; + /* * Send VR specific mailbox commands: * 000b - no VR specific command sent diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 0e8bb68..e7f860d 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -42,6 +42,9 @@ #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) #define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) +#define SA_DEV_SLOT_GMM 0x08 +#define SA_DEVFN_GMM PCI_DEVFN(SA_DEV_SLOT_GMM, 0) +#define SA_DEV_GMM PCI_DEV(0, SA_DEV_SLOT_IGD, 0) /* PCH Devices */ #define PCH_DEV_SLOT_ISH 0x13 -- To view, visit https://review.coreboot.org/c/coreboot/+/35168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21409adf85b70bccc30dd8e12a03ad7921544b3c Gerrit-Change-Number: 35168 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/timer: Make TSC frequency calculation dynamically
by Patrick Georgi (Code Review) 02 Sep '19

02 Sep '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35148 ) Change subject: soc/intel/common/timer: Make TSC frequency calculation dynamically ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/35148/9//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35148/9//COMMIT_MSG@16 PS9, Line 16: On SKL/KBL/CML CPUID.15h.ecx = nominal core crystal clock = 0 Hz so how are they handled now? -- To view, visit https://review.coreboot.org/c/coreboot/+/35148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Gerrit-Change-Number: 35148 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Comment-Date: Mon, 02 Sep 2019 06:45:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/facebook/watson: Select no UART on SuperIO
by Patrick Rudolph (Code Review) 02 Sep '19

02 Sep '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35151 ) Change subject: mb/facebook/watson: Select no UART on SuperIO ...................................................................... mb/facebook/watson: Select no UART on SuperIO Select NO_UART_ON_SUPERIO as the SoC internal UART is used. The current code is working, so this is just a cosmetic fix to remove some unused options from Kconfig. Change-Id: I206557c397da74b572e669feb1e38f0c8473d0d9 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/facebook/watson/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/35151/1 diff --git a/src/mainboard/facebook/watson/Kconfig b/src/mainboard/facebook/watson/Kconfig index 6c2f954..43b4784 100644 --- a/src/mainboard/facebook/watson/Kconfig +++ b/src/mainboard/facebook/watson/Kconfig @@ -11,6 +11,7 @@ select MAINBOARD_USES_IFD_GBE_REGION select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 + select NO_UART_ON_SUPERIO config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/35151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I206557c397da74b572e669feb1e38f0c8473d0d9 Gerrit-Change-Number: 35151 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mediatek/mt8183: Remove unnecessary parentheses
by Yu-Ping Wu (Code Review) 02 Sep '19

02 Sep '19

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35142 ) Change subject: mediatek/mt8183: Remove unnecessary parentheses ...................................................................... mediatek/mt8183: Remove unnecessary parentheses Parentheses are unnecessary for conditions like '(a == b) || (c == d)'. Extra spaces are also removed. Change-Id: I0c554bf1577b40286f7a51a8fc5804bdbb7c8bd1 Signed-off-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/rtc.c 3 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/35142/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index cdba2af..cb462e9 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -63,7 +63,7 @@ (sw_impedance[dq_term][0] << 5) | (sw_impedance[dq_term][1] << 0)); clrsetbits_le32(&ch[0].ao.shu[0].drving[1], - (0x1f << 25)|(0x1f << 20) | (1 << 31), + (0x1f << 25) | (0x1f << 20) | (1 << 31), (sw_impedance[dq_term][0] << 25) | (sw_impedance[dq_term][1] << 20) | (!dq_term << 31)); clrsetbits_le32(&ch[0].ao.shu[0].drving[2], (0x1f << 5) | (0x1f << 0), diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 05f793e..e8ee818 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -1378,7 +1378,7 @@ static void dramc_set_dqdqs_dly(u8 chn, u8 rank, enum CAL_TYPE type, s32 dly) { - if ((type == RX_WIN_RD_DQC) || (type == RX_WIN_TEST_ENG)) + if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) dramc_set_rx_dly(chn, rank, dly); else dramc_set_tx_dly_factor(chn, rank, type, dly); @@ -1553,7 +1553,7 @@ dramc_dbg("[channel %d] [rank %d] type:%d, vref_enable:%d\n", chn, rank, type, vref_scan_enable); - if ((type == TX_WIN_DQ_ONLY) || (type == TX_WIN_DQ_DQM)) { + if (type == TX_WIN_DQ_ONLY || type == TX_WIN_DQ_DQM) { for (size_t i = 0; i < 2; i++) { write32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[0], 0); clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[1], @@ -1592,7 +1592,7 @@ if (vref_scan_enable) dramc_set_vref(chn, rank, type, vref_dly.vref); - if ((type == RX_WIN_RD_DQC) || (type == RX_WIN_TEST_ENG)) { + if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) { dramc_set_rx_dly_factor(chn, rank, RX_DQM, FIRST_DQ_DELAY); dramc_set_rx_dly_factor(chn, rank, @@ -1666,7 +1666,7 @@ if (vref_scan_enable) dramc_set_vref(chn, rank, type, vref_dly.vref); - if ((type == RX_WIN_RD_DQC) || (type == RX_WIN_TEST_ENG)) + if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) dramc_set_rx_best_dly(chn, rank, vref_dly.perbit_dly); else dramc_set_tx_best_dly(chn, rank, vref_dly.perbit_dly, diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index af30d1f..f8d81f8 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -177,7 +177,7 @@ /* select 26M as target clock */ val = rtc_get_frequency_meter(middle, PMIC_FQMTR_CON0_FQM26M_CK, 0); - if ((val >= RTC_FQMTR_LOW_BASE) && (val <= RTC_FQMTR_HIGH_BASE)) + if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE) break; if (val > RTC_FQMTR_HIGH_BASE) right = middle; @@ -185,7 +185,7 @@ left = middle; } - if ((val >= RTC_FQMTR_LOW_BASE) && (val <= RTC_FQMTR_HIGH_BASE)) + if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE) return middle; val = rtc_get_frequency_meter(left, PMIC_FQMTR_CON0_FQM26M_CK, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/35142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c554bf1577b40286f7a51a8fc5804bdbb7c8bd1 Gerrit-Change-Number: 35142 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/drallion: add memory sku id
by EricR Lai (Code Review) 02 Sep '19

02 Sep '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35133 ) Change subject: mb/google/drallion: add memory sku id ...................................................................... mb/google/drallion: add memory sku id Drallion will use soldered down memory and use GPP_F12 to GPP_F16 indicates mem_id. BUG=b:139397313 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ib5ada54fd2b8f358b59de8089e5405cf3e34825a --- M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h A src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/35133/1 diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc index 0400d33..8e070d2 100644 --- a/src/mainboard/google/drallion/variants/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -20,3 +20,5 @@ ramstage-y += gpio.c romstage-y += gpio.c verstage-y += gpio.c + +romstage-y += memory.c diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h index f7e0403..20cfbb8 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h @@ -25,6 +25,13 @@ /* Recovery mode */ #define GPIO_REC_MODE GPP_E8 +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F12 +#define GPIO_MEM_CONFIG_1 GPP_F13 +#define GPIO_MEM_CONFIG_2 GPP_F14 +#define GPIO_MEM_CONFIG_3 GPP_F15 +#define GPIO_MEM_CONFIG_4 GPP_F16 + const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h index d878623..ca54580 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h @@ -22,4 +22,7 @@ #define VARIANT_SKU_ID_SIGNED_EC 4 #define VARIANT_SKU_NAME_SIGNED_EC "sku4" +/* Return memory SKU for the variant */ +int variant_memory_sku(void); + #endif diff --git a/src/mainboard/google/drallion/variants/drallion/memory.c b/src/mainboard/google/drallion/variants/drallion/memory.c new file mode 100644 index 0000000..2a1d8d9 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/memory.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variant/variant.h> +#include <gpio.h> +#include <variant/gpio.h> + +int variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + GPIO_MEM_CONFIG_4, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5ada54fd2b8f358b59de8089e5405cf3e34825a Gerrit-Change-Number: 35133 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Enable HDA for drallion platform
by Selma Bensaid (Code Review) 02 Sep '19

02 Sep '19

Hello Aamir Bohra, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35079 to review the following change. Change subject: Enable HDA for drallion platform ...................................................................... Enable HDA for drallion platform Enable PchHdaDspEnable, PchHdaIDispCodecDisconnect and PchHdaAudioLinkHda for drallion variants. This is needed with FSP 1263. Signed-off-by: Selma BENSAID <selma.bensaid(a)intel.com> Change-Id: I13d3dd832c6fbdc2aad5ba578695edb8470806e8 --- M src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb 3 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/35079/1 diff --git a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb index fe3b6c9..8470a2c 100644 --- a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb @@ -50,6 +50,12 @@ # Enable DDC for DDI port B register "DdiPortBDdc" = "1" + # HDA a + register "PchHdaDspEnable" = "1" + # Disable iDisplay codec enumeration + register "PchHdaIDispCodecDisconnect" = "1" + register "PchHdaAudioLinkHda" = "1" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 575b610..8e54625 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -50,6 +50,12 @@ # Enable DDC for DDI port B register "DdiPortBDdc" = "1" + # HDA a + register "PchHdaDspEnable" = "1" + # Disable iDisplay codec enumeration + register "PchHdaIDispCodecDisconnect" = "1" + register "PchHdaAudioLinkHda" = "1" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | diff --git a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb index d3aab62..530d6f4 100644 --- a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb @@ -56,6 +56,12 @@ register "LanWakeFromDeepSx" = "0" register "WolEnableOverride" = "0" + # HDA a + register "PchHdaDspEnable" = "1" + # Disable iDisplay codec enumeration + register "PchHdaIDispCodecDisconnect" = "1" + register "PchHdaAudioLinkHda" = "1" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | -- To view, visit https://review.coreboot.org/c/coreboot/+/35079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13d3dd832c6fbdc2aad5ba578695edb8470806e8 Gerrit-Change-Number: 35079 Gerrit-PatchSet: 1 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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