EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35133 )
Change subject: mb/google/drallion: add memory sku id ......................................................................
mb/google/drallion: add memory sku id
Drallion will use soldered down memory and use GPP_F12 to GPP_F16 indicates mem_id.
BUG=b:139397313 BRANCH=N/A TEST=N/A
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ib5ada54fd2b8f358b59de8089e5405cf3e34825a --- M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h A src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/35133/1
diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc index 0400d33..8e070d2 100644 --- a/src/mainboard/google/drallion/variants/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -20,3 +20,5 @@ ramstage-y += gpio.c romstage-y += gpio.c verstage-y += gpio.c + +romstage-y += memory.c diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h index f7e0403..20cfbb8 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h @@ -25,6 +25,13 @@ /* Recovery mode */ #define GPIO_REC_MODE GPP_E8
+/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F12 +#define GPIO_MEM_CONFIG_1 GPP_F13 +#define GPIO_MEM_CONFIG_2 GPP_F14 +#define GPIO_MEM_CONFIG_3 GPP_F15 +#define GPIO_MEM_CONFIG_4 GPP_F16 + const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num);
diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h index d878623..ca54580 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h @@ -22,4 +22,7 @@ #define VARIANT_SKU_ID_SIGNED_EC 4 #define VARIANT_SKU_NAME_SIGNED_EC "sku4"
+/* Return memory SKU for the variant */ +int variant_memory_sku(void); + #endif diff --git a/src/mainboard/google/drallion/variants/drallion/memory.c b/src/mainboard/google/drallion/variants/drallion/memory.c new file mode 100644 index 0000000..2a1d8d9 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/memory.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variant/variant.h> +#include <gpio.h> +#include <variant/gpio.h> + +int variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + GPIO_MEM_CONFIG_4, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +}
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35133 )
Change subject: mb/google/drallion: add memory sku id ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35133/1/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35133/1/src/mainboard/google/dralli... PS1, Line 4: 2017 2019
Hello Thejaswani Putta, Mathew King, Selma Bensaid, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35133
to look at the new patch set (#3).
Change subject: mb/google/drallion: add memory sku id ......................................................................
mb/google/drallion: add memory sku id
Drallion will use soldered down memory and use GPP_F12 to GPP_F16 indicates mem_id.
BUG=b:139397313 BRANCH=N/A TEST=N/A
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ib5ada54fd2b8f358b59de8089e5405cf3e34825a --- M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h A src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 43 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/35133/3
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35133 )
Change subject: mb/google/drallion: add memory sku id ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35133/1/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/memory.c:
https://review.coreboot.org/c/coreboot/+/35133/1/src/mainboard/google/dralli... PS1, Line 4: 2017
2019
Done
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35133 )
Change subject: mb/google/drallion: add memory sku id ......................................................................
Patch Set 5: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/35133 )
Change subject: mb/google/drallion: add memory sku id ......................................................................
mb/google/drallion: add memory sku id
Drallion will use soldered down memory and use GPP_F12 to GPP_F16 indicates mem_id.
BUG=b:139397313 BRANCH=N/A TEST=N/A
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Ib5ada54fd2b8f358b59de8089e5405cf3e34825a Reviewed-on: https://review.coreboot.org/c/coreboot/+/35133 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Mathew King mathewk@chromium.org --- M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h A src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 43 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Mathew King: Looks good to me, approved
diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc index 0400d33..8e070d2 100644 --- a/src/mainboard/google/drallion/variants/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -20,3 +20,5 @@ ramstage-y += gpio.c romstage-y += gpio.c verstage-y += gpio.c + +romstage-y += memory.c diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h index f7e0403..20cfbb8 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h @@ -25,6 +25,13 @@ /* Recovery mode */ #define GPIO_REC_MODE GPP_E8
+/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F12 +#define GPIO_MEM_CONFIG_1 GPP_F13 +#define GPIO_MEM_CONFIG_2 GPP_F14 +#define GPIO_MEM_CONFIG_3 GPP_F15 +#define GPIO_MEM_CONFIG_4 GPP_F16 + const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num);
diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h index d878623..ca54580 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h @@ -22,4 +22,7 @@ #define VARIANT_SKU_ID_SIGNED_EC 4 #define VARIANT_SKU_NAME_SIGNED_EC "sku4"
+/* Return memory SKU for the variant */ +int variant_memory_sku(void); + #endif diff --git a/src/mainboard/google/drallion/variants/drallion/memory.c b/src/mainboard/google/drallion/variants/drallion/memory.c new file mode 100644 index 0000000..e1755b4 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/memory.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variant/variant.h> +#include <gpio.h> +#include <variant/gpio.h> + +int variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + GPIO_MEM_CONFIG_4, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +}
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EricR Lai (Code Review) -
Mathew King (Code Review)
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Patrick Georgi (Code Review)