coreboot-gerrit September 2019

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Change in coreboot[master]: Add Razer Blade Stealth (2016) H2U
by Mimoja (Code Review) 03 Sep '19

03 Sep '19

Hello Alexander Couzens, Christoph Pomaska, Angel Pons, Jonathan Neuschäfer, Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34475 to look at the new patch set (#34). Change subject: Add Razer Blade Stealth (2016) H2U ...................................................................... Add Razer Blade Stealth (2016) H2U The Razer Blade Stealth H2U is a KabyLake System using: - Intel KBL 7500U - ITE8528E SuperIO - Intel 600P Series NVMe SSD - Either four MT52L1G32D4PG (16GB) or MT52L512MB32D4PG (8GB) of soldered memory in dualchannel mode - (Optional) Touchscreen - HDMI 2.0a via DP-1: Paradetech PS175 Even tho it has a 16MB chip equipped (W25Q128.V) only the first 8MB are used and mapped. The rest should be left empty (0xFF) The flash is not secured in any way and can be read via flashrom. It should be the source for this ports IFD and ME blobs. Working: - USB-A Ports left and right - Speakers - Touchscreen (USB) - Onboard Keyboard in Linux - NVMe SSD - SeaBIOS, Tianocore and Grub Payloads - Webcam - Powersaving Modes - Battery state and LID switch, but sometimes a bit slow to update. - Touchpad (I2C-HID) - Headphones Not going to implement: - Thunderbolt (Requires EC out of band signaling) - HDMI (Currently requires plugged connection at boot) Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> --- A src/mainboard/razer/Kconfig A src/mainboard/razer/Kconfig.name A src/mainboard/razer/blade_stealth_kbl/Kconfig A src/mainboard/razer/blade_stealth_kbl/Kconfig.name A src/mainboard/razer/blade_stealth_kbl/Makefile.inc A src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl A src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl A src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl A src/mainboard/razer/blade_stealth_kbl/acpi/mainboard.asl A src/mainboard/razer/blade_stealth_kbl/acpi/superio.asl A src/mainboard/razer/blade_stealth_kbl/acpi_tables.c A src/mainboard/razer/blade_stealth_kbl/board_info.txt A src/mainboard/razer/blade_stealth_kbl/devicetree.cb A src/mainboard/razer/blade_stealth_kbl/dsdt.asl A src/mainboard/razer/blade_stealth_kbl/gma-mainboard.ads A src/mainboard/razer/blade_stealth_kbl/gpio.h A src/mainboard/razer/blade_stealth_kbl/hda_verb.c A src/mainboard/razer/blade_stealth_kbl/mainboard.c A src/mainboard/razer/blade_stealth_kbl/ramstage.c A src/mainboard/razer/blade_stealth_kbl/romstage.c A src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc A src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex A src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex A src/mainboard/razer/blade_stealth_kbl/spd/spd.h A src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c 25 files changed, 1,321 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/34475/34 -- To view, visit https://review.coreboot.org/c/coreboot/+/34475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Gerrit-Change-Number: 34475 Gerrit-PatchSet: 34 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Add Razer Blade Stealth (2016) H2U
by Mimoja (Code Review) 03 Sep '19

03 Sep '19

Mimoja has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34475 ) Change subject: Add Razer Blade Stealth (2016) H2U ...................................................................... Patch Set 33: (9 comments) https://review.coreboot.org/c/coreboot/+/34475/33//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/34475/33//COMMIT_MSG@13 PS33, Line 13: memory in dualchannel mode > I'd say these lines are too long for a commit message, mind splitting them? Done https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/Kconf… File src/mainboard/razer/Kconfig.name: https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/Kconf… PS33, Line 2: Razer > please make it uppercase "RAZER" for consistency Done https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_kbl/Kconfig: https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… PS33, Line 33: : : config MAINBOARD_VENDOR : string : default "RAZER" > Shouldn't need to redefine this Done https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… PS33, Line 59: config CPU_MICROCODE_CBFS_LEN : hex : default 0x18000 : : config CPU_MICROCODE_CBFS_LOC : hex : default 0xFFE115A0 > Is it needed to specify the microcode length and location? Done https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… PS33, Line 22: # For now no way to choose the correct the available RAM : config BOARD_RAZER_BLADE_STEALTH_KBL_16GB : bool "16GB RAM (4x MT52L1G32D4PG)" : default n : : config VGA_BIOS_ID : string : default "8086,5916" : : config IRQ_SLOT_COUNT : int : default 18 : : config MAINBOARD_VENDOR : string : default "RAZER" : : config MAINBOARD_FAMILY : string : default "BLADE_STEALTH" : : config MAINBOARD_PART_NUMBER : string : default "H2U" : : config MAINBOARD_VERSION : string : default "1.0" : : config MAINBOARD_DIR : string : default "razer/blade_stealth_kbl" : : config MAX_CPUS : int : default 4 : : config CPU_MICROCODE_CBFS_LEN : hex : default 0x18000 : : config CPU_MICROCODE_CBFS_LOC : hex : default 0xFFE115A0 : : config CBFS_SIZE : hex : default 0x5c0000 > These are usually not indented Ack https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_kbl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… PS33, Line 39: register "SataPortsDevSlp[0]" = "0" : register "SataPortsDevSlp[2]" = "0" : register "SataSpeedLimit" = "2" > I don't think you need to set these with SATA ports disabled Done https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… PS33, Line 199: [ > Is this used? Done https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… PS33, Line 216: d > Is this used? Without it the display is not found. Not sure if this "best practice", but i can guess that this was an "okay" way by razer here. https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_kbl/mainboard.c: https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… PS33, Line 47: MAX_SERIAL_LENGTH); > Minor: fits on the previous line Done -- To view, visit https://review.coreboot.org/c/coreboot/+/34475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Gerrit-Change-Number: 34475 Gerrit-PatchSet: 33 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 02 Sep 2019 22:26:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/timer: Make TSC frequency calculation dynamically
by Furquan Shaikh (Code Review) 02 Sep '19

02 Sep '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35148 ) Change subject: soc/intel/common/timer: Make TSC frequency calculation dynamically ...................................................................... Patch Set 12: (3 comments) https://review.coreboot.org/c/coreboot/+/35148/11/src/soc/intel/common/bloc… File src/soc/intel/common/block/timer/timer.c: https://review.coreboot.org/c/coreboot/+/35148/11/src/soc/intel/common/bloc… PS11, Line 41: ; Set it to 0 here in case this function is called for a processor model other than CPU_MODEL_INTEL_ATOM_DENVERTON. https://review.coreboot.org/c/coreboot/+/35148/11/src/soc/intel/common/bloc… PS11, Line 41: int long to match it with the return type https://review.coreboot.org/c/coreboot/+/35148/11/src/soc/intel/common/bloc… PS11, Line 73: int long -- To view, visit https://review.coreboot.org/c/coreboot/+/35148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Gerrit-Change-Number: 35148 Gerrit-PatchSet: 12 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Mon, 02 Sep 2019 20:36:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/timer: Make TSC frequency calculation dynamically
by Patrick Georgi (Code Review) 02 Sep '19

02 Sep '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35148 ) Change subject: soc/intel/common/timer: Make TSC frequency calculation dynamically ...................................................................... soc/intel/common/timer: Make TSC frequency calculation dynamically tsc_freq_mhz() had a static table of Intel CPU families and crystal clock, but it is possible to calculate the crystal clock speed dynamically, and this is preferred over hardcoded table. On SKL/KBL/CML CPUID.15h.ecx = nominal core crystal clock = 0 Hz hence we had to use static table to calculate crystal clock. Recommendation is to make use of CPUID.16h where crystal clock frequency was not reported by CPUID.15h to calculate the crystal clock. BUG=b:139798422, b:129839774 TEST=Able to build and boot KBL/CML/ICL. Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35148 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: V Sowmya <v.sowmya(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- D src/arch/x86/include/arch/intel-family.h M src/soc/intel/common/block/timer/timer.c 2 files changed, 76 insertions(+), 117 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved V Sowmya: Looks good to me, approved diff --git a/src/arch/x86/include/arch/intel-family.h b/src/arch/x86/include/arch/intel-family.h deleted file mode 100644 index 43eb0e6..0000000 --- a/src/arch/x86/include/arch/intel-family.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ARCH_INTEL_FAMILY_H -#define ARCH_INTEL_FAMILY_H - -#define CPU_MODEL_INTEL_CORE_YONAH 0x0E - -#define CPU_MODEL_INTEL_CORE2_MEROM 0x0F -#define CPU_MODEL_INTEL_CORE2_MEROM_L 0x16 -#define CPU_MODEL_INTEL_CORE2_PENRYN 0x17 -#define CPU_MODEL_INTEL_CORE2_DUNNINGTON 0x1D - -#define CPU_MODEL_INTEL_NEHALEM 0x1E -/* Auburndale / Havendale */ -#define CPU_MODEL_INTEL_NEHALEM_G 0x1F -#define CPU_MODEL_INTEL_NEHALEM_EP 0x1A -#define CPU_MODEL_INTEL_NEHALEM_EX 0x2E - -#define CPU_MODEL_INTEL_WESTMERE 0x25 -#define CPU_MODEL_INTEL_WESTMERE_EP 0x2C -#define CPU_MODEL_INTEL_WESTMERE_EX 0x2F - -#define CPU_MODEL_INTEL_SANDYBRIDGE 0x2A -#define CPU_MODEL_INTEL_SANDYBRIDGE_X 0x2D -#define CPU_MODEL_INTEL_IVYBRIDGE 0x3A -#define CPU_MODEL_INTEL_IVYBRIDGE_X 0x3E - -#define CPU_MODEL_INTEL_HASWELL_CORE 0x3C -#define CPU_MODEL_INTEL_HASWELL_X 0x3F -#define CPU_MODEL_INTEL_HASWELL_ULT 0x45 -#define CPU_MODEL_INTEL_HASWELL_GT3E 0x46 - -#define CPU_MODEL_INTEL_BROADWELL_CORE 0x3D -#define CPU_MODEL_INTEL_BROADWELL_GT3E 0x47 -#define CPU_MODEL_INTEL_BROADWELL_X 0x4F -#define CPU_MODEL_INTEL_BROADWELL_XEON_D 0x56 - -#define CPU_MODEL_INTEL_SKYLAKE_MOBILE 0x4E -#define CPU_MODEL_INTEL_SKYLAKE_DESKTOP 0x5E -#define CPU_MODEL_INTEL_SKYLAKE_X 0x55 -#define CPU_MODEL_INTEL_KABYLAKE_MOBILE 0x8E -#define CPU_MODEL_INTEL_KABYLAKE_DESKTOP 0x9E -#define CPU_MODEL_INTEL_CANNONLAKE_MOBILE 0x66 -#define CPU_MODEL_INTEL_ICELAKE_MOBILE 0x7E - -/* "Small Core" Processors (Atom) */ - -#define CPU_MODEL_INTEL_ATOM_PINEVIEW 0x1C -#define CPU_MODEL_INTEL_ATOM_LINCROFT 0x26 -#define CPU_MODEL_INTEL_ATOM_PENWELL 0x27 -#define CPU_MODEL_INTEL_ATOM_CLOVERVIEW 0x35 -#define CPU_MODEL_INTEL_ATOM_CEDARVIEW 0x36 -/* BayTrail/BYT / Valleyview */ -#define CPU_MODEL_INTEL_ATOM_SILVERMONT1 0x37 -/* Avaton/Rangely */ -#define CPU_MODEL_INTEL_ATOM_SILVERMONT2 0x4D -/* CherryTrail / Braswell */ -#define CPU_MODEL_INTEL_ATOM_AIRMONT 0x4C -/* Tangier */ -#define CPU_MODEL_INTEL_ATOM_MERRIFIELD 0x4A -/* Anniedale */ -#define CPU_MODEL_INTEL_ATOM_MOOREFIELD 0x5A -#define CPU_MODEL_INTEL_ATOM_GOLDMONT 0x5C -/* Goldmont Microserver */ -#define CPU_MODEL_INTEL_ATOM_DENVERTON 0x5F -#define CPU_MODEL_INTEL_ATOM_GEMINI_LAKE 0x7A - -/* Xeon Phi */ - -/* Knights Landing */ -#define CPU_MODEL_INTEL_XEON_PHI_KNL 0x57 -/* Knights Mill */ -#define CPU_MODEL_INTEL_XEON_PHI_KNM 0x85 - -#endif /* ARCH_INTEL_FAMILY_H */ diff --git a/src/soc/intel/common/block/timer/timer.c b/src/soc/intel/common/block/timer/timer.c index e60ac4d..8fde541 100644 --- a/src/soc/intel/common/block/timer/timer.c +++ b/src/soc/intel/common/block/timer/timer.c @@ -14,12 +14,14 @@ */ #include <arch/cpu.h> -#include <arch/intel-family.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> #include <intelblocks/msr.h> +/* Goldmont Microserver */ +#define CPU_MODEL_INTEL_ATOM_DENVERTON 0x5F + static int get_processor_model(void) { struct cpuinfo_x86 c; @@ -29,8 +31,31 @@ return c.x86_model; } +static unsigned int get_max_cpuid_func(void) +{ + return cpuid_eax(0); +} + +static unsigned long get_hardcoded_crystal_freq(void) +{ + unsigned int core_crystal_nominal_freq_khz; + + /* + * Denverton SoCs don't report crystal clock, and also don't support + * CPUID.0x16, so hardcode the 25MHz crystal clock. + */ + switch (get_processor_model()) { + case CPU_MODEL_INTEL_ATOM_DENVERTON: + core_crystal_nominal_freq_khz = 25000; + break; + } + + return core_crystal_nominal_freq_khz; +} + /* - * Nominal TSC frequency = "core crystal clock frequency" * EBX/EAX + * Nominal TSC frequency = "core crystal clock frequency" * + * CPUID_15h.EBX/CPUID_15h.EAX * * Time Stamp Counter * CPUID Initial EAX value = 0x15 @@ -42,41 +67,61 @@ * core crystal clock in Hz. * EDX Bit 31-0 : Reserved = 0 * - * Refer to Intel SDM Jan 2019 Vol 3B Section 18.7.3 */ -unsigned long tsc_freq_mhz(void) +static unsigned long calculate_tsc_freq_from_core_crystal(void) { unsigned int core_crystal_nominal_freq_khz; - struct cpuid_result cpuidr; + struct cpuid_result cpuidr_15h; - /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ - cpuidr = cpuid(0x15); - - if (!cpuidr.ebx || !cpuidr.eax) + if (get_max_cpuid_func() < 0x15) return 0; - core_crystal_nominal_freq_khz = cpuidr.ecx / 1000; + /* CPUID 15H TSC/Crystal ratio, plus optionally Crystal Hz */ + cpuidr_15h = cpuid(0x15); - if (!core_crystal_nominal_freq_khz) { - switch (get_processor_model()) { - case CPU_MODEL_INTEL_SKYLAKE_MOBILE: - case CPU_MODEL_INTEL_SKYLAKE_DESKTOP: - case CPU_MODEL_INTEL_KABYLAKE_MOBILE: - case CPU_MODEL_INTEL_KABYLAKE_DESKTOP: - case CPU_MODEL_INTEL_CANNONLAKE_MOBILE: - case CPU_MODEL_INTEL_ICELAKE_MOBILE: - core_crystal_nominal_freq_khz = 24000; - break; - case CPU_MODEL_INTEL_ATOM_DENVERTON: - core_crystal_nominal_freq_khz = 25000; - break; - case CPU_MODEL_INTEL_ATOM_GOLDMONT: - case CPU_MODEL_INTEL_ATOM_GEMINI_LAKE: - core_crystal_nominal_freq_khz = 19200; - break; - } - } + if (!cpuidr_15h.ebx || !cpuidr_15h.eax) + return 0; - return (core_crystal_nominal_freq_khz * cpuidr.ebx / cpuidr.eax) / - 1000; + core_crystal_nominal_freq_khz = cpuidr_15h.ecx / 1000; + + if (!core_crystal_nominal_freq_khz) + core_crystal_nominal_freq_khz = get_hardcoded_crystal_freq(); + + return (core_crystal_nominal_freq_khz * cpuidr_15h.ebx / + cpuidr_15h.eax) / 1000; +} + +/* + * Processor Frequency Information + * CPUID Initial EAX value = 0x16 + * EAX Bit 31-0 : An unsigned integer which has the processor base frequency + * information + * EBX Bit 31-0 : An unsigned integer which has maximum frequency information + * ECX Bit 31-0 : An unsigned integer which has bus frequency information + * EDX Bit 31-0 : Reserved = 0 + * + * Refer to Intel SDM Jan 2019 Vol 3B Section 18.7.3 + */ +static unsigned long get_freq_from_cpuid16h(void) +{ + if (get_max_cpuid_func() < 0x16) + return 0; + + return cpuid_eax(0x16); +} + +unsigned long tsc_freq_mhz(void) +{ + unsigned long tsc_freq; + + tsc_freq = calculate_tsc_freq_from_core_crystal(); + + if (tsc_freq) + return tsc_freq; + + /* + * Some Intel SoCs like Skylake, Kabylake and Cometlake don't report + * the crystal clock, in that case return bus frequency using CPUID.16h + */ + return get_freq_from_cpuid16h(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Gerrit-Change-Number: 35148 Gerrit-PatchSet: 12 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/skylake: prevent null pointer dereferences
by Angel Pons (Code Review) 02 Sep '19

02 Sep '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35173 ) Change subject: soc/skylake: prevent null pointer dereferences ...................................................................... soc/skylake: prevent null pointer dereferences Change-Id: Ide10223e7fc37a6c4bfa408234ef3efe1846236a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip_fsp20.c 2 files changed, 19 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/35173/1 diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index a7d5872..812572a 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -153,10 +153,7 @@ /* Enable ISH if device is on */ dev = pcidev_path_on_root(PCH_DEVFN_ISH); - if (dev) - params->IshEnable = dev->enabled; - else - params->IshEnable = 0; + params->IshEnable = (dev) ? dev->enabled : 0; params->EnableAzalia = config->EnableAzalia; params->IoBufferOwnership = config->IoBufferOwnership; @@ -210,23 +207,24 @@ * do the changes and then lock it back in coreboot * */ - if (config->HeciEnabled == 0) - params->PsfUnlock = 1; - else - params->PsfUnlock = 0; + params->PsfUnlock = !config->HeciEnabled; for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) fill_vr_domain_config(params, i, &config->domain_vr_config[i]); /* Show SPI controller if enabled in devicetree.cb */ dev = pcidev_path_on_root(PCH_DEVFN_SPI); - params->ShowSpiController = dev->enabled; + params->ShowSpiController = (dev) ? dev->enabled : 0; /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); - if (!xdci_can_enable()) - dev->enabled = 0; - params->XdciEnable = dev->enabled; + if (dev) { + if (!xdci_can_enable()) + dev->enabled = 0; + params->XdciEnable = dev->enabled; + } else { + params->XdciEnable = 0; + } params->SendVrMbxCmd = config->SendVrMbxCmd; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 064f71e..d594bbb 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -354,10 +354,7 @@ /* If ISH is enabled, enable ISH elements */ dev = pcidev_path_on_root(PCH_DEVFN_ISH); - if (dev) - params->PchIshEnable = dev->enabled; - else - params->PchIshEnable = 0; + params->PchIshEnable = (dev) ? dev->enabled : 0; params->PchHdaEnable = config->EnableAzalia; params->PchHdaIoBufferOwnership = config->IoBufferOwnership; @@ -433,13 +430,17 @@ /* Show SPI controller if enabled in devicetree.cb */ dev = pcidev_path_on_root(PCH_DEVFN_SPI); - params->ShowSpiController = dev->enabled; + params->ShowSpiController = (dev) ? dev->enabled : 0; /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); - if (!xdci_can_enable()) - dev->enabled = 0; - params->XdciEnable = dev->enabled; + if (dev) { + if (!xdci_can_enable()) + dev->enabled = 0; + params->XdciEnable = dev->enabled; + } else { + params->XdciEnable = 0; + } /* * Send VR specific mailbox commands: -- To view, visit https://review.coreboot.org/c/coreboot/+/35173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide10223e7fc37a6c4bfa408234ef3efe1846236a Gerrit-Change-Number: 35173 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/x4x/raminit: Move dummy reads after JEDEC init
by Arthur Heymans (Code Review) 02 Sep '19

02 Sep '19

Hello Patrick Rudolph, Felix Held, Angel Pons, Paul Menzel, build bot (Jenkins), Damien Zammit, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/20979 to look at the new patch set (#10). Change subject: nb/intel/x4x/raminit: Move dummy reads after JEDEC init ...................................................................... nb/intel/x4x/raminit: Move dummy reads after JEDEC init Vendor only does dummy reads right after JEDEC init is finished and dram init was marked as finished. Dummy reads also make much more sense after JEDEC init as a way to send a few JEDEC commands, presumably as a way to make sure it is ready. TESTED on ga-g41m-es2l (still boots fine) Change-Id: I8069f9c08ad5e5268ddbe3711d58bc42522f938c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit_ddr23.c 1 file changed, 9 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/20979/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/20979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8069f9c08ad5e5268ddbe3711d58bc42522f938c Gerrit-Change-Number: 20979 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: nb/intel/x4x/raminit: Move dummy reads after JEDEC init
by Felix Held (Code Review) 02 Sep '19

02 Sep '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/20979 ) Change subject: nb/intel/x4x/raminit: Move dummy reads after JEDEC init ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/20979/9/src/northbridge/intel/x4x/… File src/northbridge/intel/x4x/raminit_ddr23.c: https://review.coreboot.org/c/coreboot/+/20979/9/src/northbridge/intel/x4x/… PS9, Line 2163: test_address(ch, r) | 0x800000 | (bank << 12) probably some parenthesis are missing around this statement, so that not only the first element gets type casted, but the whole expression -- To view, visit https://review.coreboot.org/c/coreboot/+/20979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8069f9c08ad5e5268ddbe3711d58bc42522f938c Gerrit-Change-Number: 20979 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 02 Sep 2019 18:12:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/timer: Make TSC frequency calculation dynamically
by HAOUAS Elyes (Code Review) 02 Sep '19

02 Sep '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35148 ) Change subject: soc/intel/common/timer: Make TSC frequency calculation dynamically ...................................................................... Patch Set 11: why "soc/" ? can this be also used for the other intel's CPU ? (model_1067x, model_6fx, model_f6x, f4x,..) -- To view, visit https://review.coreboot.org/c/coreboot/+/35148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Gerrit-Change-Number: 35148 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Mon, 02 Sep 2019 17:42:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/timer: Make TSC frequency calculation dynamically
by V Sowmya (Code Review) 02 Sep '19

02 Sep '19

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35148 ) Change subject: soc/intel/common/timer: Make TSC frequency calculation dynamically ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Gerrit-Change-Number: 35148 Gerrit-PatchSet: 11 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Mon, 02 Sep 2019 17:18:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/x4x/raminit: Move dummy reads after JEDEC init
by Arthur Heymans (Code Review) 02 Sep '19

02 Sep '19

Hello Patrick Rudolph, Felix Held, Angel Pons, Paul Menzel, build bot (Jenkins), Damien Zammit, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/20979 to look at the new patch set (#9). Change subject: nb/intel/x4x/raminit: Move dummy reads after JEDEC init ...................................................................... nb/intel/x4x/raminit: Move dummy reads after JEDEC init Vendor only does dummy reads right after JEDEC init is finished and dram init was marked as finished. Dummy reads also make much more sense after JEDEC init as a way to send a few JEDEC commands, presumably as a way to make sure it is ready. TESTED on ga-g41m-es2l (still boots fine) Change-Id: I8069f9c08ad5e5268ddbe3711d58bc42522f938c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit_ddr23.c 1 file changed, 9 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/20979/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/20979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8069f9c08ad5e5268ddbe3711d58bc42522f938c Gerrit-Change-Number: 20979 Gerrit-PatchSet: 9 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit September 2019