coreboot-gerrit September 2019

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Change in coreboot[master]: DO NOT COMMIT: Enable 64bit compilation for all AGESA boards
by Stefan Reinauer (Code Review) 03 Sep '19

03 Sep '19

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/10594 ) Change subject: DO NOT COMMIT: Enable 64bit compilation for all AGESA boards ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/10594 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d3908557904f6dd27154e2a4b842c94974df81a Gerrit-Change-Number: 10594 Gerrit-PatchSet: 17 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: Do not commit: unify fsp 1.0
by Stefan Reinauer (Code Review) 03 Sep '19

03 Sep '19

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/14629 ) Change subject: Do not commit: unify fsp 1.0 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/14629 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ed2766880d8a65c10bf20baddf4978cd16ef1be Gerrit-Change-Number: 14629 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marcin Wojciechowski <marcin.wojciechowski(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: src/vendorcode/amd/cimx: Unify all filenames
by Stefan Reinauer (Code Review) 03 Sep '19

03 Sep '19

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/10602 ) Change subject: src/vendorcode/amd/cimx: Unify all filenames ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/10602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia890930661ae33281f2be99b896d1a576eed1d5c Gerrit-Change-Number: 10602 Gerrit-PatchSet: 2 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: DO NOT SUBMIT: run 64 bit builds on all x86 boards
by Stefan Reinauer (Code Review) 03 Sep '19

03 Sep '19

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/11111 ) Change subject: DO NOT SUBMIT: run 64 bit builds on all x86 boards ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/11111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3f30ead6bd4a70967de0dd66544cf301b7b592a Gerrit-Change-Number: 11111 Gerrit-PatchSet: 2 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Scott Duplichan <scott(a)notabs.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: Enable warning about executable stack trampolines
by Stefan Reinauer (Code Review) 03 Sep '19

03 Sep '19

Stefan Reinauer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29262 ) Change subject: Enable warning about executable stack trampolines ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29262 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ea439eb1a8a8f20b29e72523807a6dff58c23db Gerrit-Change-Number: 29262 Gerrit-PatchSet: 2 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/hatch/var/kindred: Update DRAM IDs for 8G and 16G 3200
by David Wu (Code Review) 03 Sep '19

03 Sep '19

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35205 ) Change subject: mb/google/hatch/var/kindred: Update DRAM IDs for 8G and 16G 3200 ...................................................................... mb/google/hatch/var/kindred: Update DRAM IDs for 8G and 16G 3200 Update DRAM IDs to support 8G and 16G 3200 spds BUG=b:132920013 b:131132486 TEST=FW_NAME=kindred emerge-hatch coreboot chromeos-bootimage Change-Id: I8e55b5e24ee2cefe90472a331e829b073bf0f92a Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/kindred/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/35205/1 diff --git a/src/mainboard/google/hatch/variants/kindred/Makefile.inc b/src/mainboard/google/hatch/variants/kindred/Makefile.inc index 78f3812..8b7e3d1 100644 --- a/src/mainboard/google/hatch/variants/kindred/Makefile.inc +++ b/src/mainboard/google/hatch/variants/kindred/Makefile.inc @@ -18,6 +18,8 @@ SPD_SOURCES += 8G_2666 # 0b011 SPD_SOURCES += 16G_2400 # 0b100 SPD_SOURCES += 16G_2666 # 0b101 +SPD_SOURCES += 8G_3200 # 0b110 +SPD_SOURCES += 16G_3200 # 0b111 bootblock-y += gpio.c ramstage-y += gpio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/35205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e55b5e24ee2cefe90472a331e829b073bf0f92a Gerrit-Change-Number: 35205 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Add Razer Blade Stealth (2016) H2U
by Angel Pons (Code Review) 03 Sep '19

03 Sep '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34475 ) Change subject: Add Razer Blade Stealth (2016) H2U ...................................................................... Patch Set 35: Code-Review+2 (6 comments) Juuust minor nits. https://review.coreboot.org/c/coreboot/+/34475/35//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/34475/35//COMMIT_MSG@18 PS35, Line 18: tho though https://review.coreboot.org/c/coreboot/+/34475/35//COMMIT_MSG@18 PS35, Line 18: Even tho it has a 16MB chip equipped (W25Q128.V) only the first 8MB are used and mapped. The rest should be left empty (0xFF) These lines are still too long https://review.coreboot.org/c/coreboot/+/34475/35/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl: https://review.coreboot.org/c/coreboot/+/34475/35/src/mainboard/razer/blade… PS35, Line 62: St > The indentation looks broken here (8 spaces here vs. […] Should be tabs everywhere btw https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_kbl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… PS33, Line 216: d > Without it the display is not found. […] Weird... If it works, I wouldn't bother Ack https://review.coreboot.org/c/coreboot/+/34475/35/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_kbl/hda_verb.c: https://review.coreboot.org/c/coreboot/+/34475/35/src/mainboard/razer/blade… PS35, Line 24: // The empty comment lines on this file could be removed https://review.coreboot.org/c/coreboot/+/34475/35/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_kbl/mainboard.c: https://review.coreboot.org/c/coreboot/+/34475/35/src/mainboard/razer/blade… PS35, Line 38: if (rdev_readat(&cbfs_region, serial_number, 0, serial_len) [bikeshedding-grade] seeing this line being split makes me suffer. maybe rename "serial_len" to "len", if you want? -- To view, visit https://review.coreboot.org/c/coreboot/+/34475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Gerrit-Change-Number: 34475 Gerrit-PatchSet: 35 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 03 Sep 2019 21:31:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Mimoja <coreboot(a)mimoja.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-MessageType: comment

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Change in coreboot[master]: Add Razer Blade Stealth (2016) H2U
by Jonathan Neuschäfer (Code Review) 03 Sep '19

03 Sep '19

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34475 ) Change subject: Add Razer Blade Stealth (2016) H2U ...................................................................... Patch Set 35: Code-Review+1 (10 comments) Some minor comments/questions. Otherwise, it LGTM but I don't have the expertise to give a +2. https://review.coreboot.org/c/coreboot/+/34475/35//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/34475/35//COMMIT_MSG@19 PS35, Line 19: ports port's https://review.coreboot.org/c/coreboot/+/34475/35//COMMIT_MSG@33 PS35, Line 33: : Not going to implement: Does that mean never, or not in this commit, or something in between? https://review.coreboot.org/c/coreboot/+/34475/35/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl: https://review.coreboot.org/c/coreboot/+/34475/35/src/mainboard/razer/blade… PS35, Line 62: St The indentation looks broken here (8 spaces here vs. two tabs in surrounding lines) https://review.coreboot.org/c/coreboot/+/34475/35/src/mainboard/razer/blade… PS35, Line 70: S dito https://review.coreboot.org/c/coreboot/+/34475/35/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/34475/35/src/mainboard/razer/blade… PS35, Line 27: Name dito, for most of the file. https://review.coreboot.org/c/coreboot/+/34475/35/src/mainboard/razer/blade… PS35, Line 75: // Store Lids -> \Lids should be working... Can you explain this comment in more detail, please? What works, what doesn't? https://review.coreboot.org/c/coreboot/+/34475/35/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_kbl/board_info.txt: https://review.coreboot.org/c/coreboot/+/34475/35/src/mainboard/razer/blade… PS35, Line 1: razer This is inconsistent with the string in Kconfig (RAZER vs. razer); not sure if intended. https://review.coreboot.org/c/coreboot/+/34475/35/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_kbl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/34475/35/src/mainboard/razer/blade… PS35, Line 274: subsystemid 0x1a58 0x6752 There is a way to set the subsystem ID once and for all PCI devices, which makes sense *if* the vendor firmware also sets it for all devices (I don't know if it does). The trick is to write `subsystemid 0x1a58 0x6752 inherit` into the `device domain 0` block. Example: https://review.coreboot.org/cgit/coreboot.git/tree/src/mainboard/msi/ms9652… https://review.coreboot.org/c/coreboot/+/34475/35/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_kbl/hda_verb.c: https://review.coreboot.org/c/coreboot/+/34475/35/src/mainboard/razer/blade… PS35, Line 25: // The indentation is weird here (tab+space) https://review.coreboot.org/c/coreboot/+/34475/35/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc: https://review.coreboot.org/c/coreboot/+/34475/35/src/mainboard/razer/blade… PS35, Line 21: b0001 I think this should rather be index 0 (0b0000) and index 1 (0b0001) -- To view, visit https://review.coreboot.org/c/coreboot/+/34475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Gerrit-Change-Number: 34475 Gerrit-PatchSet: 35 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 03 Sep 2019 19:05:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [UNTESTED] skylake: do not rely on P2SB data to generate DRHD
by Angel Pons (Code Review) 03 Sep '19

03 Sep '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35108 ) Change subject: [UNTESTED] skylake: do not rely on P2SB data to generate DRHD ...................................................................... [UNTESTED] skylake: do not rely on P2SB data to generate DRHD The P2SB PCI device can be "hidden", which causes all sorts of nightmares and bugs. Moreover, FSP tends to hide it, so finding a good solution to this problem is impossible with FSP into the mix. Since the values for IBDF and HBDF were already hardcoded as FSP parameters, write them with coreboot code and use these values directly to generate the DRHD, so as to avoid using the P2SB when it might be already hidden. Note that the possibility of fireworks happening has not been ruled out. Change-Id: I7eb20182380b953a1842083e7a3c67919d6971b9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/include/soc/systemagent.h M src/soc/intel/skylake/romstage/romstage_fsp20.c 5 files changed, 29 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/35108/1 diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index aa51cbe..9c5b674 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -30,7 +30,6 @@ #include <ec/google/chromeec/ec.h> #include <intelblocks/cpulib.h> #include <intelblocks/lpc_lib.h> -#include <intelblocks/p2sb.h> #include <intelblocks/sgx.h> #include <intelblocks/uart.h> #include <intelblocks/systemagent.h> @@ -575,30 +574,19 @@ acpi_dmar_rmrr_fixup(tmp, current); } - struct device *const p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB); const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff; const bool vtvc0en = MCHBAR32(VTVC0BAR) & 1; /* General VTBAR has to be set and in 32-bit space. */ - if (p2sb_dev && vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { + if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { const unsigned long tmp = current; - /* P2SB may already be hidden. There's no clear rule, when. */ - const u8 p2sb_hidden = - pci_read_config8(p2sb_dev, PCH_P2SB_E0 + 1); - pci_write_config8(p2sb_dev, PCH_P2SB_E0 + 1, 0); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - const u16 ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF); - const u16 hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF); - - pci_write_config8(p2sb_dev, PCH_P2SB_E0 + 1, p2sb_hidden); - - current += acpi_create_dmar_drhd(current, - DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, - 2, ibdf >> 8, PCI_SLOT(ibdf), PCI_FUNC(ibdf)); - current += acpi_create_dmar_ds_msi_hpet(current, - 0, hbdf >> 8, PCI_SLOT(hbdf), PCI_FUNC(hbdf)); + current += acpi_create_dmar_ds_ioapic(current, 2, V_P2SB_IBDF_BUS, + V_P2SB_IBDF_DEV, V_P2SB_IBDF_FUN); + current += acpi_create_dmar_ds_msi_hpet(current, 0, V_P2SB_HBDF_BUS, + V_P2SB_HBDF_DEV, V_P2SB_HBDF_FUN); acpi_dmar_drhd_fixup(tmp, current); } diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index c95a8d8..cc43415 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -35,6 +35,7 @@ #include <soc/pm.h> #include <soc/pmc.h> #include <soc/smbus.h> +#include <soc/systemagent.h> #include "../chip.h" @@ -50,6 +51,12 @@ fast_spi_early_init(SPI_BASE_ADDRESS); p2sb_enable_bar(); p2sb_configure_hpet(); + + // Write the IOAPIC Bus:Dev.Fun value to P2SB IBDF register + pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_IBDF, V_DEFAULT_IBDF); + + // Write the HPET Bus:Dev.Fun value to P2SB HBDF register + pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF, V_DEFAULT_HBDF); } static void soc_config_acpibase(void) diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 064f71e..fa39607 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -484,10 +484,8 @@ params->X2ApicOptOut = 0; tconfig->VtdDisable = 0; - params->PchIoApicBdfValid = 1; - params->PchIoApicBusNumber = 250; - params->PchIoApicDeviceNumber = 31; - params->PchIoApicFunctionNumber = 0; + // We set that in coreboot already + params->PchIoApicBdfValid = 0; } soc_irq_settings(params); diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h index d7dec65..42b4eec 100644 --- a/src/soc/intel/skylake/include/soc/systemagent.h +++ b/src/soc/intel/skylake/include/soc/systemagent.h @@ -61,4 +61,16 @@ VTVC0_BASE_SIZE, "VTVC0BAR" }; + +// Hardcoded default values for PCI Bus:Dev.Fun for IOAPIC and HPET +#define V_P2SB_IBDF_BUS 250 +#define V_P2SB_IBDF_DEV 31 +#define V_P2SB_IBDF_FUN 0 +#define V_DEFAULT_IBDF ((V_P2SB_IBDF_BUS << 8) | PCI_DEVFN(V_P2SB_IBDF_DEV, V_P2SB_IBDF_FUN)) + +#define V_P2SB_HBDF_BUS 250 +#define V_P2SB_HBDF_DEV 15 +#define V_P2SB_HBDF_FUN 0 +#define V_DEFAULT_HBDF ((V_P2SB_HBDF_BUS << 8) | PCI_DEVFN(V_P2SB_HBDF_DEV, V_P2SB_HBDF_FUN)) + #endif diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 8b5cd18..00cb6fe 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -288,10 +288,8 @@ cpu_flex_override(m_cfg); if (!config->ignore_vtd) { - m_cfg->PchHpetBdfValid = 1; - m_cfg->PchHpetBusNumber = 250; - m_cfg->PchHpetDeviceNumber = 15; - m_cfg->PchHpetFunctionNumber = 0; + // We set that in coreboot already + m_cfg->PchHpetBdfValid = 0; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/35108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7eb20182380b953a1842083e7a3c67919d6971b9 Gerrit-Change-Number: 35108 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Add Razer Blade Stealth (2016) H2U
by Mimoja (Code Review) 03 Sep '19

03 Sep '19

Hello Alexander Couzens, Christoph Pomaska, Angel Pons, Jonathan Neuschäfer, Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34475 to look at the new patch set (#35). Change subject: Add Razer Blade Stealth (2016) H2U ...................................................................... Add Razer Blade Stealth (2016) H2U The Razer Blade Stealth H2U is a KabyLake System using: - Intel KBL 7500U - ITE8528E SuperIO - Intel 600P Series NVMe SSD - Either four MT52L1G32D4PG (16GB) or MT52L512MB32D4PG (8GB) of soldered memory in dualchannel mode - (Optional) Touchscreen - HDMI 2.0a via DP-1: Paradetech PS175 Even tho it has a 16MB chip equipped (W25Q128.V) only the first 8MB are used and mapped. The rest should be left empty (0xFF) The flash is not secured in any way and can be read via flashrom. It should be the source for this ports IFD and ME blobs. Working: - USB-A Ports left and right - Speakers - Touchscreen (USB) - Onboard Keyboard in Linux - NVMe SSD - SeaBIOS, Tianocore and Grub Payloads - Webcam - Powersaving Modes - Battery state and LID switch, sometimes slow to update. - Touchpad (I2C-HID) - Headphones Not going to implement: - Thunderbolt (Requires EC out of band signaling) - HDMI (Currently requires plugged connection at boot) Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> --- A src/mainboard/razer/Kconfig A src/mainboard/razer/Kconfig.name A src/mainboard/razer/blade_stealth_kbl/Kconfig A src/mainboard/razer/blade_stealth_kbl/Kconfig.name A src/mainboard/razer/blade_stealth_kbl/Makefile.inc A src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl A src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl A src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl A src/mainboard/razer/blade_stealth_kbl/acpi/mainboard.asl A src/mainboard/razer/blade_stealth_kbl/acpi/superio.asl A src/mainboard/razer/blade_stealth_kbl/acpi_tables.c A src/mainboard/razer/blade_stealth_kbl/board_info.txt A src/mainboard/razer/blade_stealth_kbl/devicetree.cb A src/mainboard/razer/blade_stealth_kbl/dsdt.asl A src/mainboard/razer/blade_stealth_kbl/gma-mainboard.ads A src/mainboard/razer/blade_stealth_kbl/gpio.h A src/mainboard/razer/blade_stealth_kbl/hda_verb.c A src/mainboard/razer/blade_stealth_kbl/mainboard.c A src/mainboard/razer/blade_stealth_kbl/ramstage.c A src/mainboard/razer/blade_stealth_kbl/romstage.c A src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc A src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex A src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex A src/mainboard/razer/blade_stealth_kbl/spd/spd.h A src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c 25 files changed, 1,321 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/34475/35 -- To view, visit https://review.coreboot.org/c/coreboot/+/34475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Gerrit-Change-Number: 34475 Gerrit-PatchSet: 35 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit September 2019