coreboot-gerrit September 2019

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Change in ...coreboot[master]: mainboard/amd: Add padmelon board code
by Richard Spiegel (Code Review) 04 Sep '19

04 Sep '19

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33993 Change subject: mainboard/amd: Add padmelon board code ...................................................................... mainboard/amd: Add padmelon board code With almost everything in place, it's time to add padmelon board. There are 2 versions, one using a fanned version of 00670F00 and one using merlinfalcon (00660F01, also fanned), both SOC FP4 sockets. This code was intended for merlinfalcon version, but as there are some legal issues (documentation) blocking its merge to coreboot, it'll be released for 00670F00, being replaced later with merlinfalcon when the binaries can be merged to coreboot (PSP, video and AGESA). Even both use fanned versions of SOC, the actual fan control is done through a SIO, fintek f81803a. BUG=b:none. TEST=Both versions tested and boot to Linux using SeaBIOS. Change-Id: I5a366ddeb4cfebd177a8744f6edb87aecd4787dd Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- A src/mainboard/amd/padmelon/BiosCallOuts.c A src/mainboard/amd/padmelon/BiosCallOuts.h A src/mainboard/amd/padmelon/Kconfig A src/mainboard/amd/padmelon/Kconfig.name A src/mainboard/amd/padmelon/Makefile.inc A src/mainboard/amd/padmelon/OemCustomize.c A src/mainboard/amd/padmelon/acpi/gpe.asl A src/mainboard/amd/padmelon/acpi/mainboard.asl A src/mainboard/amd/padmelon/acpi/routing.asl A src/mainboard/amd/padmelon/acpi/sleep.asl A src/mainboard/amd/padmelon/acpi/superio.asl A src/mainboard/amd/padmelon/acpi/usb_oc.asl A src/mainboard/amd/padmelon/acpi_tables.c A src/mainboard/amd/padmelon/board_info.txt A src/mainboard/amd/padmelon/bootblock/OemCustomize.c A src/mainboard/amd/padmelon/bootblock/bootblock.c A src/mainboard/amd/padmelon/devicetree.cb A src/mainboard/amd/padmelon/dsdt.asl A src/mainboard/amd/padmelon/fan_init.c A src/mainboard/amd/padmelon/gpio.c A src/mainboard/amd/padmelon/gpio.h A src/mainboard/amd/padmelon/irq_tables.c A src/mainboard/amd/padmelon/mainboard.c A src/mainboard/amd/padmelon/mptable.c A src/mainboard/amd/padmelon/romstage.c 25 files changed, 1,962 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/33993/1 diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.c b/src/mainboard/amd/padmelon/BiosCallOuts.c new file mode 100644 index 0000000..522a63f --- /dev/null +++ b/src/mainboard/amd/padmelon/BiosCallOuts.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/agesawrapper.h> +#include <amdblocks/BiosCallOuts.h> +#include <soc/southbridge.h> +#include <stdlib.h> +#include <string.h> + +void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env) +{ + +} diff --git a/src/mainboard/amd/padmelon/BiosCallOuts.h b/src/mainboard/amd/padmelon/BiosCallOuts.h new file mode 100644 index 0000000..8c2a047 --- /dev/null +++ b/src/mainboard/amd/padmelon/BiosCallOuts.h @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define FAN_INPUT_INTERNAL_DIODE 0 +#define FAN_INPUT_TEMP0 1 +#define FAN_INPUT_TEMP1 2 +#define FAN_INPUT_TEMP2 3 +#define FAN_INPUT_TEMP3 4 +#define FAN_INPUT_TEMP0_FILTER 5 +#define FAN_INPUT_ZERO 6 +#define FAN_INPUT_DISABLED 7 + +#define FAN_AUTOMODE (1 << 0) +#define FAN_LINEARMODE (1 << 1) +#define FAN_STEPMODE ~(1 << 1) +#define FAN_POLARITY_HIGH (1 << 2) +#define FAN_POLARITY_LOW ~(1 << 2) + +/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ +#define FREQ_28KHZ 0x0 +#define FREQ_25KHZ 0x1 +#define FREQ_23KHZ 0x2 +#define FREQ_21KHZ 0x3 +#define FREQ_29KHZ 0x4 +#define FREQ_18KHZ 0x5 +#define FREQ_100HZ 0xF7 +#define FREQ_87HZ 0xF8 +#define FREQ_58HZ 0xF9 +#define FREQ_44HZ 0xFA +#define FREQ_35HZ 0xFB +#define FREQ_29HZ 0xFC +#define FREQ_22HZ 0xFD +#define FREQ_14HZ 0xFE +#define FREQ_11HZ 0xFF diff --git a/src/mainboard/amd/padmelon/Kconfig b/src/mainboard/amd/padmelon/Kconfig new file mode 100644 index 0000000..df4f9f1 --- /dev/null +++ b/src/mainboard/amd/padmelon/Kconfig @@ -0,0 +1,76 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2018 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_AMD_PADMELON + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y +# select SOC_AMD_MERLINFALCON # missing binaries + select SOC_AMD_STONEYRIDGE_FP4 # alternative version + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_I2C_GENERIC + select DRIVERS_PS2_KEYBOARD + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select GFXUMA + select STONEYRIDGE_LEGACY_FREE + select ONBOARD_VGA_IS_PRIMARY + select BOOTBLOCK_CONSOLE + select SUPERIO_FINTEK_F81803A + select SUPERIO_FINTEK_COMMON_PRE_RAM + select SUPERIO_FINTEK_F81803A_FAN_CONTROL + select VGA_BIOS + +config VGA_BIOS_FILE + string + default "3rdparty/blobs/soc/amd/merlinfalcon/VBIOS.bin" + +config MAINBOARD_DIR + string + default amd/padmelon + +config MAINBOARD_PART_NUMBER + string + default "Padmelon" + +config MAX_CPUS + int + default 4 + +config IRQ_SLOT_COUNT + int + default 11 + +config HWM_IO_WINDOW + hex + default 0x0100 + help + Select a bit within LPC_IO_PORT_DECODE_ENABLE that will enable + access to IO port HWM_PORT, which is programmed at bootblock. + +config HWM_PORT + hex + default 0x0225 + help + Oddly enough, HWM base address must be and odd address. Hardware + monitor used addresses are HWM_PORT for index and HWM_PORT + 1 + for data. + +# Don't use AMD's Secure OS +config USE_PSPSECUREOS + def_bool n + +endif # BOARD_AMD_PADMELON diff --git a/src/mainboard/amd/padmelon/Kconfig.name b/src/mainboard/amd/padmelon/Kconfig.name new file mode 100644 index 0000000..fb88c39 --- /dev/null +++ b/src/mainboard/amd/padmelon/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_AMD_PADMELON + bool "Padmelon" diff --git a/src/mainboard/amd/padmelon/Makefile.inc b/src/mainboard/amd/padmelon/Makefile.inc new file mode 100644 index 0000000..aabc221 --- /dev/null +++ b/src/mainboard/amd/padmelon/Makefile.inc @@ -0,0 +1,32 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/OemCustomize.c +bootblock-y += gpio.c + +romstage-y += BiosCallOuts.c +romstage-y += bootblock/OemCustomize.c +romstage-y += OemCustomize.c + +ramstage-y += BiosCallOuts.c +ramstage-y += gpio.c +ramstage-y += OemCustomize.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F81803A_FAN_CONTROL) += fan_init.c + +CPPFLAGS_common += -I$(src)/vendorcode/amd/pi/00670F00 +CPPFLAGS_common += -I$(src)/vendorcode/amd/pi/00670F00/Proc/Fch/Common +CPPFLAGS_common += -I$(src)/vendorcode/amd/pi/00670F00/Proc/Common +CPPFLAGS_common += -I$(src)/vendorcode/amd/pi/00670F00/binaryPI diff --git a/src/mainboard/amd/padmelon/OemCustomize.c b/src/mainboard/amd/padmelon/OemCustomize.c new file mode 100644 index 0000000..bb92733 --- /dev/null +++ b/src/mainboard/amd/padmelon/OemCustomize.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <chip.h> +#include <amdblocks/agesawrapper.h> + +#define DIMMS_PER_CHANNEL 1 +#if DIMMS_PER_CHANNEL > MAX_DIMMS_PER_CH +#error "Too many DIMM sockets defined for the mainboard" +#endif + +static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = { + DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, CHANNEL_A, 1), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, CHANNEL_B, 1), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, MAX_DRAM_CH), + MOTHER_BOARD_LAYERS(LAYERS_6), + MEMCLK_DIS_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00), + MEMCLK_DIS_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x02, 0x08, 0x04, + 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00), + CKE_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x05, 0x0A, 0x00, 0x00), + ODT_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x00, 0x02, 0x00), + ODT_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x04, 0x02, 0x08), + CS_TRI_MAP(ANY_SOCKET, CHANNEL_A, 0x01, 0x02, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00), + CS_TRI_MAP(ANY_SOCKET, CHANNEL_B, 0x01, 0x02, 0x04, 0x08, 0x00, + 0x00, 0x00, 0x00), + PSO_END +}; + +void OemPostParams(AMD_POST_PARAMS *PostParams) +{ + PostParams->MemConfig.PlatformMemoryConfiguration = + (PSO_ENTRY *)DDR4PlatformMemoryConfiguration; + PostParams->MemConfig.CfgUmaAbove4G = TRUE; +} diff --git a/src/mainboard/amd/padmelon/acpi/gpe.asl b/src/mainboard/amd/padmelon/acpi/gpe.asl new file mode 100644 index 0000000..03bbc38 --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/gpe.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L03\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event - Power Button */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + \_SB.SIO0.CPSI() /* clear psin state in sio */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.EHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/amd/padmelon/acpi/mainboard.asl b/src/mainboard/amd/padmelon/acpi/mainboard.asl new file mode 100644 index 0000000..db5731f --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/mainboard.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ diff --git a/src/mainboard/amd/padmelon/acpi/routing.asl b/src/mainboard/amd/padmelon/acpi/routing.asl new file mode 100644 index 0000000..37b9613 --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/routing.asl @@ -0,0 +1,251 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ + Package(){0x0001FFFF, 0, INTG, 0 }, + Package(){0x0001FFFF, 1, INTH, 0 }, + + + /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ + Package(){0x0002FFFF, 0, INTH, 0 }, + Package(){0x0002FFFF, 1, INTA, 0 }, + Package(){0x0002FFFF, 2, INTB, 0 }, + Package(){0x0002FFFF, 3, INTC, 0 }, + + Package(){0x0003FFFF, 0, INTH, 0 }, + Package(){0x0003FFFF, 1, INTA, 0 }, + Package(){0x0003FFFF, 2, INTB, 0 }, + Package(){0x0003FFFF, 3, INTC, 0 }, + + Package(){0x0008FFFF, 0, INTG, 0 }, + Package(){0x0008FFFF, 1, INTH, 0 }, + Package(){0x0008FFFF, 2, INTE, 0 }, + Package(){0x0008FFFF, 3, INTF, 0 }, + + /* Bus 0, Dev 9, Func 2 - HDAudio */ + Package(){0x0009FFFF, 0, INTG, 0 }, + Package(){0x0009FFFF, 1, INTH, 0 }, + Package(){0x0009FFFF, 2, INTE, 0 }, + Package(){0x0009FFFF, 3, INTF, 0 }, + + /* FCH devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18 Func 0 - USB: EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 16 Func 0 - USB: xHCI */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, +}) + +Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 30 }, + Package(){0x0001FFFF, 1, 0, 31 }, + Package(){0x0001FFFF, 2, 0, 28 }, + Package(){0x0001FFFF, 3, 0, 29 }, + + /* Bus 0, Dev 2 - PCIe Bridges */ + Package(){0x0002FFFF, 0, 0, 47 }, + Package(){0x0002FFFF, 1, 0, 48 }, + Package(){0x0002FFFF, 2, 0, 49 }, + Package(){0x0002FFFF, 3, 0, 50 }, + + Package(){0x0003FFFF, 0, 0, 39 }, + Package(){0x0003FFFF, 1, 0, 40 }, + Package(){0x0003FFFF, 2, 0, 41 }, + Package(){0x0003FFFF, 3, 0, 42 }, + + Package(){0x0008FFFF, 0, 0, 38 }, + Package(){0x0008FFFF, 1, 0, 39 }, + Package(){0x0008FFFF, 2, 0, 36 }, + Package(){0x0008FFFF, 3, 0, 37 }, + + /* Bus 0, Dev 9, Func 2 - HDAudio */ + Package(){0x0009FFFF, 0, 0, 46 }, + Package(){0x0009FFFF, 1, 0, 47 }, + Package(){0x0009FFFF, 2, 0, 44 }, + Package(){0x0009FFFF, 3, 0, 45 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F2:HDAudio;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 18, 19, 22 Func 0 - USB: OHCI */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 18}, + Package(){0x0010FFFF, 1, 0, 17}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, +}) + +Name(PS4, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 24 }, + Package(){0x0000FFFF, 1, 0, 25 }, + Package(){0x0000FFFF, 2, 0, 26 }, + Package(){0x0000FFFF, 3, 0, 27 }, +}) + +/* GPP 1 */ +Name(PS5, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS5, Package(){ + Package(){0x0000FFFF, 0, 0, 32 }, + Package(){0x0000FFFF, 1, 0, 33 }, + Package(){0x0000FFFF, 2, 0, 34 }, + Package(){0x0000FFFF, 3, 0, 35 }, +}) + +/* GPP 2 */ +Name(PS6, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS6, Package(){ + Package(){0x0000FFFF, 0, 0, 40 }, + Package(){0x0000FFFF, 1, 0, 41 }, + Package(){0x0000FFFF, 2, 0, 42 }, + Package(){0x0000FFFF, 3, 0, 43 }, +}) + +/* GPP 3 */ +Name(PS7, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS7, Package(){ + Package(){0x0000FFFF, 0, 0, 48 }, + Package(){0x0000FFFF, 1, 0, 49 }, + Package(){0x0000FFFF, 2, 0, 50 }, + Package(){0x0000FFFF, 3, 0, 51 }, +}) + +/* GPP 4 */ +Name(PS8, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APS8, Package(){ + Package(){0x0000FFFF, 0, 0, 27 }, + Package(){0x0000FFFF, 1, 0, 24 }, + Package(){0x0000FFFF, 2, 0, 25 }, + Package(){0x0000FFFF, 3, 0, 26 }, +}) + +Name(PS9, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APS9, Package(){ + Package(){0x0000FFFF, 0, 0, 35 }, + Package(){0x0000FFFF, 1, 0, 32 }, + Package(){0x0000FFFF, 2, 0, 33 }, + Package(){0x0000FFFF, 3, 0, 34 }, +}) + +/* GFX 2 */ +Name(PSA, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APSA, Package(){ + Package(){0x0000FFFF, 0, 0, 51 }, + Package(){0x0000FFFF, 1, 0, 48 }, + Package(){0x0000FFFF, 2, 0, 49 }, + Package(){0x0000FFFF, 3, 0, 50 }, +}) + +/* GFX 3 */ +Name(PSB, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APSB, Package(){ + Package(){0x0000FFFF, 0, 0, 26 }, + Package(){0x0000FFFF, 1, 0, 27 }, + Package(){0x0000FFFF, 2, 0, 24 }, + Package(){0x0000FFFF, 3, 0, 25 }, +}) + +/* GFX 4 */ +Name(PSC, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APSC, Package(){ + Package(){0x0000FFFF, 0, 0, 34 }, + Package(){0x0000FFFF, 1, 0, 35 }, + Package(){0x0000FFFF, 2, 0, 32 }, + Package(){0x0000FFFF, 3, 0, 33 }, +}) diff --git a/src/mainboard/amd/padmelon/acpi/sleep.asl b/src/mainboard/amd/padmelon/acpi/sleep.asl new file mode 100644 index 0000000..58f0752 --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/sleep.asl @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear wake status structure. */ + Store(0, PEWD) + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/padmelon/acpi/superio.asl b/src/mainboard/amd/padmelon/acpi/superio.asl new file mode 100644 index 0000000..9befcce --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/superio.asl @@ -0,0 +1,183 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz <christophg+cb(a)grenz-bonn.de> + * Copyright (C) 2013 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the W83627DHG SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices and controlling power + * saving mode on logical devices or the whole chip. + * + * LDN State + * 0x1 UARTA Implemented, partially tested + * 0x2 UARTB UART only, partially tested + * 0x4 HWM Resources, PM only + * 0x5 KBC Implemented, untested + * 0x6 GPIO6 Not implemented + * 0x7 WDT0&PLED Not implemented + * 0x9 GPIO2-5 Not implemented + * 0xa ACPI/PME/ERP Not implemented + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/o address of the first PnP configuration register + * F81803A_SHOW_UARTA If defined, UARTA will be exposed. + * F81803A_SHOW_UARTB If defined, UARTB will be exposed. + * F81803A_SHOW_KBC If defined, the KBC will be exposed. + * F81803A_SHOW_PS2M If defined, PS/2 mouse support will be exposed. + * F81803A_SHOW_HWMON If defined, the hardware monitor will be exposed. + * F81803A_SHOW_PME If defined, the PME/EARP/ACPI will be exposed. + */ +#undef SUPERIO_DEV +#define SUPERIO_DEV SIO0 +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME F81803A +#define SUPERIO_PNP_BASE 0x4E +#include <superio/acpi/pnp.asl> + +Device(SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("Fintek F81803A Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* Mutex for accesses to the configuration ports */ + Mutex(CRMX, 1) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8 + } + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + + offset(0xFB), + APC5, 8, /* PME ACPI Control Register 5 */ + } + + /* PMx-- registers to get the addresses of the ACPI Registers */ + IndexField(PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) + { + Offset(0x60), /* AcpiPmEvBlk */ + P1EB, 16, /* AcpiPmEvtBlk */ + P1CB, 16, /* AcpiPm1CntBlk */ + Offset(0xEE), + UPWS, 3, + } + + /* AcpiPmEvtBlk registers*/ + OperationRegion(P1E0, SystemIO, P1EB, 0x04) + Field(P1E0, ByteAcc, Nolock, Preserve) + { + Offset(0x02), /* Pm1Enable */ + , 14, + PEWD, 1, /* bit 1: PciExpWakeDis*/ + } + + + /* AcpiPm1CntBlk registers*/ + OperationRegion(P1C0, SystemIO, P1CB, 0x04) + Field(P1C0, ByteAcc, Nolock, Preserve) + { + Offset(0x00), /* PmControl */ + , 10, + P1ST, 3, /* Bits SlpTyp */ + P1SE, 1, /* SlpTypEn*/ + } + + OperationRegion(APCx, SystemIO, APC5, 0x01) + Field(APCx, ByteAcc, Nolock, Preserve) /* bits in PME ACPI CONTROL Reg 5*/ + { + Offset(0x00), /*Control Reg 5 */ + , 7, + PSIN, 1, /* PSIN_FLAG */ + } + + /* routine to clear PSIN_FLAG in ACPI_CONTROL_REG_5 of SIO */ + Method(CPSI, 0, Serialized) + { + /* DBG0("SIO CPSI")*/ + ENTER_CONFIG_MODE(10) + Store(1, PSIN) + EXIT_CONFIG_MODE() + } + + Method(_CRS) + { + /* Announce the used i/o ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #undef PNP_EXIT_SPECIAL_REG + #undef PNP_EXIT_SPECIAL_VAL + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x87 + #define PNP_EXIT_MAGIC_1ST 0xaa + #include <superio/acpi/pnp_config.asl> + +#ifdef F81803A_SHOW_UARTA + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 1 + #define SUPERIO_UART_PM_REG UAPW + #define SUPERIO_UART_PM_VAL 0 + #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef F81803A_SHOW_UARTB + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #define SUPERIO_UART_PM_REG UBPW + #define SUPERIO_UART_PM_VAL 0 + #define SUPERIO_UART_PM_LDN PNP_NO_LDN_CHANGE + #include <superio/acpi/pnp_uart.asl> +#endif + +} diff --git a/src/mainboard/amd/padmelon/acpi/usb_oc.asl b/src/mainboard/amd/padmelon/acpi/usb_oc.asl new file mode 100644 index 0000000..9566bc4 --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi/usb_oc.asl @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) + +/* USB Overcurrent GPEs */ +/* TODO: Update for Gardenia */ diff --git a/src/mainboard/amd/padmelon/acpi_tables.c b/src/mainboard/amd/padmelon/acpi_tables.c new file mode 100644 index 0000000..8d4d1cf --- /dev/null +++ b/src/mainboard/amd/padmelon/acpi_tables.c @@ -0,0 +1,14 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Blank file required by build system assumptions of this file being present. + */ diff --git a/src/mainboard/amd/padmelon/board_info.txt b/src/mainboard/amd/padmelon/board_info.txt new file mode 100644 index 0000000..b351b8e --- /dev/null +++ b/src/mainboard/amd/padmelon/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/amd/padmelon/bootblock/OemCustomize.c b/src/mainboard/amd/padmelon/bootblock/OemCustomize.c new file mode 100644 index 0000000..5d82988 --- /dev/null +++ b/src/mainboard/amd/padmelon/bootblock/OemCustomize.c @@ -0,0 +1,192 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/agesawrapper.h> + +#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE + +static const PCIe_PORT_DESCRIPTOR PortList[] = { + /* + * Init Port descriptor (PCIe port, Lanes 8-15, + * PCI Device Number 3, ...) + */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 15), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, + 3, 1, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x02, 0) + }, + + /* + * Initialize Port descriptor (PCIe port, Lane 7, + * PCI Device Number 2, ...) + */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, + 2, 5, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x03, 0) + }, + /* + * Initialize Port descriptor (PCIe port, Lane 6, + * PCI Device Number 2, ...) + */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, + 2, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x04, 0) + }, + /* + * Initialize Port descriptor (PCIe port, Lane 5, + * PCI Device Number 2, ...) + */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db, + 2, 3, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x04, 0) + }, + /* + * Initialize Port descriptor (PCIe port, Lane4, + * PCI Device Number 2, ...) + */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, + 2, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x06, 0) + }, + /* + * Initialize Port descriptor (PCIe port, Lanes 0-3, + * PCI Device Number 2, ...) + */ + { + /* + * Descriptor flags !!!IMPORTANT!!! Terminate last element + * of array + */ + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER_V2(PortDisabled, ChannelTypeExt6db, + 2, 1, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0x07, 0) + }, + +}; + + +static const PCIe_DDI_DESCRIPTOR DdiList[] = { + /* DP0 */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 16, 19), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) + }, + /* DP1 */ + { + 0, /*DESCRIPTOR_TERMINATE_LIST, */ + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 20, 23), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) + }, + /* DP2 */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3) + }, +}; + +static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = (void *)PortList, + .DdiLinkList = (void *)DdiList +}; + +static const UINT32 AzaliaCodecAlc286Table[] = { + 0x00172051, 0x001721C7, 0x00172222, 0x00172310, + 0x0017FF00, 0x0017FF00, 0x0017FF00, 0x0017FF00, + 0x01271C50, 0x01271D01, 0x01271EA6, 0x01271FB7, + 0x01371C00, 0x01371D00, 0x01371E00, 0x01371F40, + 0x01471C10, 0x01471D01, 0x01471E17, 0x01471F90, + 0x01771CF0, 0x01771D11, 0x01771E11, 0x01771F41, + 0x01871C40, 0x01871D10, 0x01871EA1, 0x01871F04, + 0x01971CF0, 0x01971D11, 0x01971E11, 0x01971F41, + 0x01A71CF0, 0x01A71D11, 0x01A71E11, 0x01A71F41, + 0x01D71C2D, 0x01D71DA5, 0x01D71E67, 0x01D71F40, + 0x01E71C30, 0x01E71D11, 0x01E71E45, 0x01E71F04, + 0x02171C20, 0x02171D10, 0x02171E21, 0x02171F04, + 0x02050071, 0x02040014, 0x02050010, 0x02040C22, + 0x0205004F, 0x0204B029, 0x0205002B, 0x02040C50, + 0x0205002D, 0x02041020, 0x02050020, 0x02040000, + 0x02050019, 0x02040817, 0x02050035, 0x02041AA5, + 0x02050063, 0x02042906, 0x02050063, 0x02042906, + 0xffffffff +}; + +static CONST CODEC_VERB_TABLE_LIST CodecTableList[] = { + { 0x10ec0286, AzaliaCodecAlc286Table}, + { 0x10ec0288, AzaliaCodecAlc286Table}, + { 0x10ec0888, AzaliaCodecAlc286Table}, + { 0x0FFFFFFFF, (void *)0x0FFFFFFFF} +}; + +/*---------------------------------------------------------------------------*/ +/** + * OemCustomizeInitEarly + * + * Description: + * This is the stub function will call the host environment through the + * binary block interface (call-out port) to provide a user hook opportunity. + * + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly + * + * @retval VOID + * + **/ +/*---------------------------------------------------------------------------*/ +VOID OemCustomizeInitEarly(AMD_EARLY_PARAMS *InitEarly) +{ + InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex; + InitEarly->PlatformConfig.AzaliaCodecVerbTable = + (uint64_t)(uintptr_t)CodecTableList; + InitEarly->PlatformConfig.AzaliaSsid = 0x157A1022ul; +} diff --git a/src/mainboard/amd/padmelon/bootblock/bootblock.c b/src/mainboard/amd/padmelon/bootblock/bootblock.c new file mode 100644 index 0000000..3ef34d3 --- /dev/null +++ b/src/mainboard/amd/padmelon/bootblock/bootblock.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017-2018 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/southbridge.h> +#include <amdblocks/lpc.h> +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f81803a/f81803a.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <soc/pci_devs.h> + +#include "../gpio.h" + +#define SERIAL_DEV PNP_DEV(0x4e, F81803A_SP1) + +/* Enable UAT control pins, assuming base address 0x03f8 */ +static void full_serial(void) +{ + u32 temp; + u8 reg; + temp = pci_read_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE); + temp |= DECODE_ENABLE_SERIAL_PORT0; + pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, temp); + reg = inb(0x3fb); + reg |= 3; + outb(reg, 0x3fb); + reg = inb(0x3fc); + reg |= 3; + outb(reg, 0x3fc); +} + +void bootblock_mainboard_early_init(void) +{ + sb_clk_output_48Mhz(2); + /* + * UART enabled by default at reset, just need control pins such as + * RTS, CTS, etc... + */ + full_serial(); +} + +void bootblock_mainboard_init(void) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + + gpios = early_gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); +} diff --git a/src/mainboard/amd/padmelon/devicetree.cb b/src/mainboard/amd/padmelon/devicetree.cb new file mode 100644 index 0000000..c6df430 --- /dev/null +++ b/src/mainboard/amd/padmelon/devicetree.cb @@ -0,0 +1,80 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip soc/amd/stoneyridge + + register "spd_addr_lookup" = " + { + { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 + }" + + register "uma_mode" = "UMAMODE_AUTO_LEGACY" + #register "uma_size" = "512 * MiB" + + device cpu_cluster 0 on + device lapic 10 on end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9874 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # No x4 PCIe slot + device pci 2.2 on end # Half mPCIe slot + device pci 2.3 on end # NC + device pci 2.4 on end # RTL8111F + device pci 3.0 on end # PCIe Host Bridge + device pci 8.0 on end # PSP + device pci 9.0 on end # HDA + device pci 9.2 on end # HDA + device pci 10.0 on end # USB + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + end # SM + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81803a + register "conf_key_mode" = "0x77" + device pnp 4e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.4 off end # HWM + device pnp 4e.5 off end # KBC + device pnp 4e.6 off end # GPIO + device pnp 4e.7 off end # WDT + device pnp 4e.a on end # PME + end # f81803a + end # LPC + device pci 14.7 on end # SD + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #domain +end #soc/amd/stoneyridge diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl new file mode 100644 index 0000000..e4d89b1 --- /dev/null +++ b/src/mainboard/amd/padmelon/dsdt.asl @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* as needed */ + + /* global NVS and variables */ + #include <globalnvs.asl> + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* IRQ Routing mapping for this platform (in \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + /* Describe the SOC */ + #include <soc.asl> + + /* Describe the Fintek F81803A SIO */ + #include <superio/fintek/f81803a/acpi/superio.asl> + + } /* End \_SB scope */ + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/amd/padmelon/fan_init.c b/src/mainboard/amd/padmelon/fan_init.c new file mode 100644 index 0000000..0675dc4 --- /dev/null +++ b/src/mainboard/amd/padmelon/fan_init.c @@ -0,0 +1,151 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Richard Spiegel <richard.spiegel(a)silverbackltd.com> + * Copyright (C) 2019 Silverback ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <bootstate.h> +#include <device/pci_ops.h> +#include <amdblocks/lpc.h> +#include <superio/fintek/common/fan_control.h> +#include <soc/southbridge.h> +#include <soc/pci_devs.h> + +#define CPU_FAN 1 +#define SYSTEM_FAN 2 + +/* Boundaries in celcius, sections in percent */ +u8 cpu_boudaries[] = { + 80, + 65, + 50, + 35 +}; + +u8 system_boudaries[] = { + 70, + 55, + 40, + 25 +}; + +u8 cpu_section[] = { + 100, + 85, + 70, + 55, + 40 +}; + +u8 system_section[] = { + 100, + 85, + 70, + 55, + 40 +}; + +static int check_status(const char *name, int status) +{ + if (status != HWM_STATUS_SUCCESS) + printk(BIOS_DEBUG, "%s returned %d\n", name, status); + if (status < HWM_STATUS_SUCCESS) + return status; + return HWM_STATUS_SUCCESS; /* positive values are warnings only */ +} + +static void set_fan(uint8_t fan, external_sensor sensor, temp_sensor_type stype, + fan_temp_source temp_source, fan_type ftype, + fan_mode fmode, fan_pwm_freq fan_freq, + fan_rate_up rate_up, fan_rate_down rate_down, + u8 *boundaries, u8 *sections) +{ + int s; + printk(BIOS_DEBUG, "Set sensor type\n"); + if (sensor != IGNORE_SENSOR) { + s = set_sensor_type(CONFIG_HWM_PORT, sensor, stype); + if (check_status("set_sensor_type", s) < HWM_STATUS_SUCCESS) + return; + } + + printk(BIOS_DEBUG, "Set temperature source\n"); + s = set_fan_temperature_source(CONFIG_HWM_PORT, fan, temp_source); + if (check_status("set_fan_temperature_source", s) < HWM_STATUS_SUCCESS) + return; + + printk(BIOS_DEBUG, "Set fan type mode\n"); + s = set_fan_type_mode(CONFIG_HWM_PORT, fan, ftype, fmode); + if (check_status("fan_type_mode", s) < HWM_STATUS_SUCCESS) + return; + + printk(BIOS_DEBUG, "Set PWM frequency\n"); + s = set_pwm_frequency(CONFIG_HWM_PORT, fan, fan_freq); + if (check_status("set_pwm_frequency", s) < HWM_STATUS_SUCCESS) + return; + + printk(BIOS_DEBUG, "Set fan speed change rate\n"); + s = set_fan_speed_change_rate(CONFIG_HWM_PORT, fan, rate_up, rate_down); + if (check_status("set_fan_speed_change_rate", s) < HWM_STATUS_SUCCESS) + return; + + printk(BIOS_DEBUG, "Set sections\n"); + s = set_sections(CONFIG_HWM_PORT, fan, boundaries, sections); + printk(BIOS_DEBUG, "set_sections returned %d\n", s); + if (check_status("set_sections", s) < HWM_STATUS_SUCCESS) + return; + + printk(BIOS_DEBUG, "Fan %d completed\n", fan); +} + +/* Todo - move this code to SIO */ +static void init_hwm(void) +{ + outb(0x87, 0x4e); + outb(0x87, 0x4e); + outb(0x7, 0x4e); + outb(4, 0x4f); + outb(0x60, 0x4e); + outb(2, 0x4f); + outb(0x61, 0x4e); + outb(0x20, 0x4f); + outb(0x30, 0x4e); + outb(1, 0x4f); + outb(0xaa, 0x4e); +} + +static void init_fan_control(void *unused) +{ + uint32_t reg, t; + + init_hwm(); + /* Open a LPC window to access the hardware monitor */ + reg = pci_read_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE); + t = reg | CONFIG_HWM_IO_WINDOW; + pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, t); + + set_fan(CPU_FAN, IGNORE_SENSOR, TEMP_SENSOR_DEFAULT, + FAN_TEMP_TSI, FAN_TYPE_PWM_PUSH_PULL, FAN_MODE_DEFAULT, + FAN_PWM_FREQ_23500, FAN_UP_RATE_10HZ, FAN_DOWN_RATE_10HZ, + cpu_boudaries, cpu_section); + + set_fan(SYSTEM_FAN, EXTERNAL_SENSOR2, TEMP_SENSOR_BJT, + FAN_TEMP_EXTERNAL_2, FAN_TYPE_DAC_POWER, FAN_MODE_DEFAULT, + FAN_PWM_FREQ_23500, FAN_UP_RATE_10HZ, FAN_DOWN_RATE_10HZ, + system_boudaries, system_section); + + /* restore register */ + pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, reg); +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, init_fan_control, NULL); diff --git a/src/mainboard/amd/padmelon/gpio.c b/src/mainboard/amd/padmelon/gpio.c new file mode 100644 index 0000000..88d2925 --- /dev/null +++ b/src/mainboard/amd/padmelon/gpio.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/agesawrapper.h> +#include <amdblocks/BiosCallOuts.h> +#include <soc/southbridge.h> +#include <stdlib.h> +#include <soc/gpio.h> + +#include "gpio.h" + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* NFC PU */ + PAD_GPO(GPIO_64, HIGH), + /* PCIe presence detect */ + PAD_GPO(GPIO_64, HIGH), + /* MUX for Power Express Eval */ + PAD_GPI(GPIO_116, PULL_DOWN), + /* SD power */ + PAD_GPO(GPIO_64, HIGH), +}; + +const struct soc_amd_gpio gpio_set_stage_ram[] = { + /* BT radio disable */ + PAD_GPO(GPIO_14, HIGH), + /* NFC wake */ + PAD_GPO(GPIO_65, HIGH), + /* Webcam */ + PAD_GPO(GPIO_66, HIGH), + /* GPS sleep */ + PAD_GPO(GPIO_70, HIGH), +}; + +const struct soc_amd_gpio *early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_reset); + return gpio_set_stage_reset; +} + +const struct soc_amd_gpio *gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_ram); + return gpio_set_stage_ram; +} diff --git a/src/mainboard/amd/padmelon/gpio.h b/src/mainboard/amd/padmelon/gpio.h new file mode 100644 index 0000000..1d3a8a2 --- /dev/null +++ b/src/mainboard/amd/padmelon/gpio.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +const struct soc_amd_gpio *early_gpio_table(size_t *size); +const struct soc_amd_gpio *gpio_table(size_t *size); + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/amd/padmelon/irq_tables.c b/src/mainboard/amd/padmelon/irq_tables.c new file mode 100644 index 0000000..31cfbc1 --- /dev/null +++ b/src/mainboard/amd/padmelon/irq_tables.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) + pirq->checksum = sum; + + printk(BIOS_INFO, "%s done.\n", __func__); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/amd/padmelon/mainboard.c b/src/mainboard/amd/padmelon/mainboard.c new file mode 100644 index 0000000..11cf6b0 --- /dev/null +++ b/src/mainboard/amd/padmelon/mainboard.c @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/acpi.h> +#include <amdblocks/agesawrapper.h> +#include <amdblocks/amd_pci_util.h> +#include <soc/pci_devs.h> +#include <soc/southbridge.h> + +#include "gpio.h" + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + */ +const u8 mainboard_picr_data[] = { + [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, + [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, + [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, + [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, + [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, + [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, + [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, +}; + +const u8 mainboard_intr_data[] = { + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, + [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, + [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, + [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, + [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, + [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +/* + * This table defines the index into the picr/intr_data tables for each + * device. Any enabled device and slot that uses hardware interrupts should + * have an entry in this table to define its index into the FCH PCI_INTR + * register 0xC00/0xC01. This index will define the interrupt that it should + * use. Putting PIRQ_A into the PIN A index for a device will tell that + * device to use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + { GFX_DEVFN, { PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { HDA0_DEVFN, { PIRQ_NC, PIRQ_HDA, PIRQ_NC, PIRQ_NC } }, + { PCIE0_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE1_DEVFN, { PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A } }, + { PCIE2_DEVFN, { PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B } }, + { PCIE3_DEVFN, { PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C } }, + { PCIE4_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PSP_DEVFN, { PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { HDA1_DEVFN, { PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { SD_DEVFN, { PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { SMBUS_DEVFN, { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { SATA_DEVFN, { PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { EHCI1_DEVFN, { PIRQ_EHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, + { XHCI_DEVFN, { PIRQ_XHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +static void mainboard_init(void *chip_info) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + gpios = gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); +} + +/************************************************* + * enable the dedicated function in padmelon board. + *************************************************/ +static void padmelon_enable(struct device *dev) +{ + printk(BIOS_INFO, "Mainboard " + CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = padmelon_enable, +}; diff --git a/src/mainboard/amd/padmelon/mptable.c b/src/mainboard/amd/padmelon/mptable.c new file mode 100644 index 0000000..63f17f2 --- /dev/null +++ b/src/mainboard/amd/padmelon/mptable.c @@ -0,0 +1,165 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <string.h> +#include <stdint.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> +#include <soc/southbridge.h> +#include <amdblocks/amd_pci_util.h> + +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + bus_isa = 0x02; + my_smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), \ + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \ + (intr), (apicid), (pin)) + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, \ + MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \ + (((dev)<<2)|(int_sign)), ioapic_id, (pin)) + + /* Internal VGA */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); + + /* SMBUS */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0. */ + PCI_INT(bus_pci, 0x5, 0x0, 0x14); + PCI_INT(bus_pci, 0x5, 0x1, 0x15); + PCI_INT(bus_pci, 0x5, 0x2, 0x16); + PCI_INT(bus_pci, 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_pci, 0x6, 0x0, 0x15); + PCI_INT(bus_pci, 0x6, 0x1, 0x16); + PCI_INT(bus_pci, 0x6, 0x2, 0x17); + PCI_INT(bus_pci, 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_pci, 0x7, 0x0, 0x16); + PCI_INT(bus_pci, 0x7, 0x1, 0x17); + PCI_INT(bus_pci, 0x7, 0x2, 0x14); + PCI_INT(bus_pci, 0x7, 0x3, 0x15); + } + + /* PCIe Lan*/ + PCI_INT(0x0, 0x06, 0x0, 0x13); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/amd/padmelon/romstage.c b/src/mainboard/amd/padmelon/romstage.c new file mode 100644 index 0000000..644c7cc --- /dev/null +++ b/src/mainboard/amd/padmelon/romstage.c @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ -- To view, visit https://review.coreboot.org/c/coreboot/+/33993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a366ddeb4cfebd177a8744f6edb87aecd4787dd Gerrit-Change-Number: 33993 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-MessageType: newchange

8 61

Change in coreboot[master]: Documentation/soc/intel/fsp: Add link for external FSP2.1 spec
by Subrata Banik (Code Review) 04 Sep '19

04 Sep '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35238 ) Change subject: Documentation/soc/intel/fsp: Add link for external FSP2.1 spec ...................................................................... Documentation/soc/intel/fsp: Add link for external FSP2.1 spec Change-Id: I5d1abd6252bda2be09285cd878a483f055abcd7b Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M Documentation/soc/intel/fsp/index.md 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/35238/1 diff --git a/Documentation/soc/intel/fsp/index.md b/Documentation/soc/intel/fsp/index.md index 6269445..9f307e6 100644 --- a/Documentation/soc/intel/fsp/index.md +++ b/Documentation/soc/intel/fsp/index.md @@ -45,6 +45,8 @@ * [FSP Specification 2.0](https://www.intel.com/content/dam/www/public/us/en/documents/technical… +* [FSP Specification 2.1](https://cdrdv2.intel.com/v1/dl/getContent/609253) + ## Additional Features in FSP 2.1 specification - [PPI](ppi/ppi.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/35238 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d1abd6252bda2be09285cd878a483f055abcd7b Gerrit-Change-Number: 35238 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: mediatek/mt8183: postpone dcxo low power mode setting
by Weiyi Lu (Code Review) 04 Sep '19

04 Sep '19

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34777 to review the following change. Change subject: mediatek/mt8183: postpone dcxo low power mode setting ...................................................................... mediatek/mt8183: postpone dcxo low power mode setting Consider the association between MD and DCXO, this patch is a fix for eb5e47d("mediatek/mt8183: update dcxo output buffer setting") [1] We should not disable XO_CEL and block the bblpm request when MD is still ON. [1] https://review.coreboot.org/c/coreboot/+/32323 BRANCH=none TEST=Boots correctly on Krane. Change-Id: I047ebed615e874977ca211aafd52b5551c71b764 Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> --- M src/soc/mediatek/mt8183/include/soc/rtc.h M src/soc/mediatek/mt8183/rtc.c M src/soc/mediatek/mt8183/soc.c 3 files changed, 14 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/34777/1 diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index 5a61208..aa4cc43 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -147,6 +147,7 @@ /* PMIC DCXO Register Definition */ enum { PMIC_RG_DCXO_CW00 = 0x0788, + PMIC_RG_DCXO_CW00_CLR = 0x078C, PMIC_RG_DCXO_CW02 = 0x0790, PMIC_RG_DCXO_CW07 = 0x079A, PMIC_RG_DCXO_CW09 = 0x079E, @@ -218,5 +219,6 @@ void rtc_osc_init(void); int rtc_init(u8 recover); void rtc_boot(void); +void dcxo_disable_unused(void); #endif /* SOC_MEDIATEK_MT8183_RTC_H */ diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index af30d1f..464fff3 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -411,10 +411,9 @@ rtc_write(PMIC_RG_DCXO_CW16, 0x9855); /* 26M enable control */ - /* Enable clock buffer XO_SOC */ - rtc_write(PMIC_RG_DCXO_CW00, 0x4005); + /* Enable clock buffer XO_SOC, XO_CEL */ + rtc_write(PMIC_RG_DCXO_CW00, 0x4805); rtc_write(PMIC_RG_DCXO_CW11, 0x8000); - rtc_write(PMIC_RG_DCXO_CW23, 0x0053); /* Load thermal coefficient */ rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7); @@ -432,6 +431,14 @@ mdelay(5); } +void dcxo_disable_unused(void) +{ + /* Disable clock buffer XO_CEL */ + rtc_write(PMIC_RG_DCXO_CW00_CLR, 0x0800); + /* Mask bblpm */ + rtc_write(PMIC_RG_DCXO_CW23, 0x0053); +} + /* the rtc boot flow entry */ void rtc_boot(void) { diff --git a/src/soc/mediatek/mt8183/soc.c b/src/soc/mediatek/mt8183/soc.c index c9c2147..f190480 100644 --- a/src/soc/mediatek/mt8183/soc.c +++ b/src/soc/mediatek/mt8183/soc.c @@ -17,6 +17,7 @@ #include <soc/emi.h> #include <soc/md_ctrl.h> #include <soc/mmu_operations.h> +#include <soc/rtc.h> #include <soc/sspm.h> #include <symbols.h> @@ -29,6 +30,7 @@ { mtk_mmu_disable_l2c_sram(); mtk_md_early_init(); + dcxo_disable_unused(); sspm_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/34777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I047ebed615e874977ca211aafd52b5551c71b764 Gerrit-Change-Number: 34777 Gerrit-PatchSet: 1 Gerrit-Owner: Weiyi Lu <weiyi.lu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/coding_style.md: Update line length limit
by Angel Pons (Code Review) 04 Sep '19

04 Sep '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35215 ) Change subject: Documentation/coding_style.md: Update line length limit ...................................................................... Documentation/coding_style.md: Update line length limit Line length limit was bumped to 96 characters, but the coding style did not reflect such a change. Change-Id: Ifdbb8bc04e49e1fbe9b0c8a642ae814d5a60004a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M Documentation/coding_style.md 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/35215/1 diff --git a/Documentation/coding_style.md b/Documentation/coding_style.md index 048b8e6..ac0de4e 100644 --- a/Documentation/coding_style.md +++ b/Documentation/coding_style.md @@ -80,11 +80,11 @@ Coding style is all about readability and maintainability using commonly available tools. -The limit on the length of lines is 80 columns and this is a strongly +The limit on the length of lines is 96 columns and this is a strongly preferred limit. -Statements longer than 80 columns will be broken into sensible chunks, -unless exceeding 80 columns significantly increases readability and does +Statements longer than 96 columns will be broken into sensible chunks, +unless exceeding 96 columns significantly increases readability and does not hide information. Descendants are always substantially shorter than the parent and are placed substantially to the right. The same applies to function headers with a long argument list. However, never break -- To view, visit https://review.coreboot.org/c/coreboot/+/35215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdbb8bc04e49e1fbe9b0c8a642ae814d5a60004a Gerrit-Change-Number: 35215 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1344
by Ronak Kanabar (Code Review) 04 Sep '19

04 Sep '19

Ronak Kanabar has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/35244 ) Change subject: src/vendorcode/intel: Update Cometlake FSP headers as per FSP v1344 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/35244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice0a9dbdb885ec6fdc0e95144c45d2b312490d29 Gerrit-Change-Number: 35244 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: inteltool: add Lewisburg C62x chipset family PCI IDs
by Maxim Polyakov (Code Review) 04 Sep '19

04 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34941 ) Change subject: inteltool: add Lewisburg C62x chipset family PCI IDs ...................................................................... inteltool: add Lewisburg C62x chipset family PCI IDs These changes are in accordance with the documentation: [*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, Document Number: 336067-007US, May 2019 https://www3.intel.com/content/dam/www/public/us/en/documents/ datasheets/c620-series-chipset-datasheet.pdf Change-Id: I7a1ae0cc4c5d4b02599dfafd30f4a87b3ce74b74 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h 2 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/34941/1 diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 76b1abe..15ad815 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -260,6 +260,13 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM175, "HM175" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QM175, "QM175" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CM238, "CM238" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_C621, "Lewisburg C621" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_C622, "Lewisburg C622" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_C624, "Lewisburg C624" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_C625, "Lewisburg C625" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_C626, "Lewisburg C626" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_C627, "Lewisburg C627" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_C628, "Lewisburg C628" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H310, "H310" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H370, "H370" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z390, "Z390" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 483c930..a0108ee 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -170,6 +170,14 @@ #define PCI_DEVICE_ID_INTEL_QM175 0xa153 #define PCI_DEVICE_ID_INTEL_CM238 0xa154 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_C621 0xa1c1 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_C622 0xa1c2 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_C624 0xa1c3 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_C625 0xa1c4 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_C626 0xa1c5 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_C627 0xa1c6 +#define PCI_DEVICE_ID_INTEL_LEWISBURG_C628 0xa1c7 + #define PCI_DEVICE_ID_INTEL_H310 0xa303 #define PCI_DEVICE_ID_INTEL_H370 0xa304 #define PCI_DEVICE_ID_INTEL_Z390 0xa305 -- To view, visit https://review.coreboot.org/c/coreboot/+/34941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a1ae0cc4c5d4b02599dfafd30f4a87b3ce74b74 Gerrit-Change-Number: 34941 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mediatek/mt8183: Use different DRAM frequencies for EMCP DDR
by Yu-Ping Wu (Code Review) 04 Sep '19

04 Sep '19

Yu-Ping Wu has uploaded a new patch set (#16) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34990 ) Change subject: mediatek/mt8183: Use different DRAM frequencies for EMCP DDR ...................................................................... mediatek/mt8183: Use different DRAM frequencies for EMCP DDR Devices using EMCP may run in a high DRAM frequency (e.g., 3600Mbps) while discrete DRAM can only run at 3200Mbps. This patch enables 3600Mbps for EMCP DDR for better system performance. BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/emi.c 1 file changed, 21 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/34990/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/34990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656 Gerrit-Change-Number: 34990 Gerrit-PatchSet: 16 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: SJ Huang <sj.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mediatek/mt8183: Enable DRAM frequency 3600Mbps for EMCP DDR
by Yu-Ping Wu (Code Review) 04 Sep '19

04 Sep '19

Yu-Ping Wu has uploaded a new patch set (#15) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34990 ) Change subject: mediatek/mt8183: Enable DRAM frequency 3600Mbps for EMCP DDR ...................................................................... mediatek/mt8183: Enable DRAM frequency 3600Mbps for EMCP DDR Devices using EMCP may run in a high DRAM frequency (e.g., 3600Mbps) while discrete DRAM can only run at 3200Mbps. This patch enables 3600Mbps for EMCP DDR for better system performance. BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/emi.c 1 file changed, 21 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/34990/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/34990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656 Gerrit-Change-Number: 34990 Gerrit-PatchSet: 15 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: SJ Huang <sj.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mediatek/mt8183: Set DRAM voltage for each DRAM frequency
by Yu-Ping Wu (Code Review) 04 Sep '19

04 Sep '19

Yu-Ping Wu has uploaded a new patch set (#7) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/35017 ) Change subject: mediatek/mt8183: Set DRAM voltage for each DRAM frequency ...................................................................... mediatek/mt8183: Set DRAM voltage for each DRAM frequency Adjust voltage for each DRAM frequency. BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h 2 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/35017/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/35017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Gerrit-Change-Number: 35017 Gerrit-PatchSet: 7 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: security/tpm/tss/tcg-2.0: Use tlcl_get_hash_size_from_algo() for has...
by Frans Hendriks (Code Review) 04 Sep '19

04 Sep '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33251 Change subject: security/tpm/tss/tcg-2.0: Use tlcl_get_hash_size_from_algo() for hash size ...................................................................... security/tpm/tss/tcg-2.0: Use tlcl_get_hash_size_from_algo() for hash size mashal_TPMT_HA() uses size of SHA-256 hash. Use tlcll_get_hash_size_from_algo(0) to determince the hash size. BUG=N/A TEST=Build binary and verified logging on Facebook FBG-1701 Change-Id: I739260e13e9cd10a61d52e13e8741b12ec868d7f Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/security/tpm/tss.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/tcg-2.0/tss_structures.h 4 files changed, 52 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/33251/1 diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index 548a39a..2ff9eed 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -70,6 +70,14 @@ * custom tpm standards like cr50 */ void *tpm_process_command(TPM_CC command, void *command_body); +/* + * Return size of digest. + * + * @param[in] HashAlgo Hash algorithm + * + * @return size of digest + */ +uint16_t tlcl_get_hash_size_from_algo(TPMI_ALG_HASH hashAlgo); #endif diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index e579bff..24d7726 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -361,3 +361,33 @@ return TPM_SUCCESS; } +/** + Return size of digest. + + @param[in] HashAlgo Hash algorithm + + @return size of digest +**/ + +uint16_t tlcl_get_hash_size_from_algo(TPMI_ALG_HASH hashAlgo) +{ + uint16_t value; + + switch (hashAlgo) { + case TPM_ALG_ERROR: + value = 1; + break; + case TPM_ALG_SHA1: + value = SHA1_DIGEST_SIZE; + break; + case TPM_ALG_SHA256: + value = SHA256_DIGEST_SIZE; + break; + default: + printk(BIOS_SPEW, "%s: unknown hash algorithm %d\n", __func__, + hashAlgo); + value = 0; + }; + + return value; +} diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 21da73a..a74eb09 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -12,6 +12,7 @@ #include "tss_marshaling.h" #include <security/tpm/tss/vendor/cr50/cr50.h> +#include <security/tpm/tss.h> static uint16_t tpm_tag CAR_GLOBAL; /* Depends on the command type. */ @@ -82,7 +83,7 @@ rc |= marshal_TPMI_ALG_HASH(ob, tpmtha->hashAlg); rc |= obuf_write(ob, tpmtha->digest.sha256, - sizeof(tpmtha->digest.sha256)); + tlcl_get_hash_size_from_algo(tpmtha->hashAlg)); return rc; } diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 991cbcf..dcd4468 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -36,12 +36,24 @@ typedef TPM_HANDLE TPM_RH; /* Some hardcoded algorithm values. */ +/* Table 7 - TPM_ALG_ID Constants */ +#define TPM_ALG_ERROR ((TPM_ALG_ID)0x0000) #define TPM_ALG_HMAC ((TPM_ALG_ID)0x0005) #define TPM_ALG_NULL ((TPM_ALG_ID)0x0010) #define TPM_ALG_SHA1 ((TPM_ALG_ID)0x0004) #define TPM_ALG_SHA256 ((TPM_ALG_ID)0x000b) +#define TPM_ALG_SHA384 ((TPM_ALG_ID)0x000C) +#define TPM_ALG_SHA512 ((TPM_ALG_ID)0x000D) +#define TPM_ALG_SM3_256 ((TPM_ALG_ID)0x0012) +/* Annex A Algorithm Constants */ + +/* Table 205 - Defines for SHA1 Hash Values */ +#define SHA1_DIGEST_SIZE 20 +/* Table 206 - Defines for SHA256 Hash Values */ #define SHA256_DIGEST_SIZE 32 +/* Table 208 - Defines for SHA512 Hash Values */ +#define SHA512_DIGEST_SIZE 64 /* Some hardcoded hierarchies. */ #define TPM_RH_NULL 0x40000007 -- To view, visit https://review.coreboot.org/c/coreboot/+/33251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I739260e13e9cd10a61d52e13e8741b12ec868d7f Gerrit-Change-Number: 33251 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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