coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

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1442 discussions

Change in coreboot[master]: arch/ppc64: move misc.c to qemu-power8 as timer.c
by Marty E. Plummer (Code Review) 02 Sep '19

02 Sep '19

Marty E. Plummer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35082 ) Change subject: arch/ppc64: move misc.c to qemu-power8 as timer.c ...................................................................... arch/ppc64: move misc.c to qemu-power8 as timer.c Its entirely no-op and is getting in the way of real hardware timers for power9/talos ii. Change-Id: I2d21d4ac3d1a7d3f099ed6ec4faf10079b1ee1d1 Signed-off-by: Marty E. Plummer <hanetzer(a)startmail.com> --- M src/arch/ppc64/Makefile.inc M src/mainboard/emulation/qemu-power8/Makefile.inc R src/mainboard/emulation/qemu-power8/timer.c 3 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/35082/1 diff --git a/src/arch/ppc64/Makefile.inc b/src/arch/ppc64/Makefile.inc index 03b455a..bb9c63dd 100644 --- a/src/arch/ppc64/Makefile.inc +++ b/src/arch/ppc64/Makefile.inc @@ -85,7 +85,6 @@ ramstage-y += rom_media.c ramstage-y += stages.c -ramstage-y += misc.c ramstage-y += boot.c ramstage-y += tables.c ramstage-y += \ diff --git a/src/mainboard/emulation/qemu-power8/Makefile.inc b/src/mainboard/emulation/qemu-power8/Makefile.inc index db005bb..5c6c56e 100644 --- a/src/mainboard/emulation/qemu-power8/Makefile.inc +++ b/src/mainboard/emulation/qemu-power8/Makefile.inc @@ -17,6 +17,7 @@ romstage-y += cbmem.c ramstage-y += cbmem.c romstage-y += romstage.c +ramstage-y += timer.c romstage-y += uart.c ramstage-y += uart.c diff --git a/src/arch/ppc64/misc.c b/src/mainboard/emulation/qemu-power8/timer.c similarity index 100% rename from src/arch/ppc64/misc.c rename to src/mainboard/emulation/qemu-power8/timer.c -- To view, visit https://review.coreboot.org/c/coreboot/+/35082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d21d4ac3d1a7d3f099ed6ec4faf10079b1ee1d1 Gerrit-Change-Number: 35082 Gerrit-PatchSet: 1 Gerrit-Owner: Marty E. Plummer <hanetzer(a)startmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/var/helios: Increase touchscreen reset delay to 120ms
by Philip Chen (Code Review) 02 Sep '19

02 Sep '19

Philip Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35158 ) Change subject: mb/google/hatch/var/helios: Increase touchscreen reset delay to 120ms ...................................................................... mb/google/hatch/var/helios: Increase touchscreen reset delay to 120ms As per GT7375P programming guide rev0.4, we want to enforece a delay of 120ms after the reset is completed before HID_I2C starts. BUG=b:140276418 Signed-off-by: Philip Chen <philipchen(a)google.com> Change-Id: Id69a9db996bcd9001ef850c50898fbd55327b4df --- M src/mainboard/google/hatch/variants/helios/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/35158/1 diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index f97f120..71e4856 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -100,7 +100,7 @@ register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "10" + register "generic.reset_delay_ms" = "120" register "generic.reset_off_delay_ms" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" -- To view, visit https://review.coreboot.org/c/coreboot/+/35158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id69a9db996bcd9001ef850c50898fbd55327b4df Gerrit-Change-Number: 35158 Gerrit-PatchSet: 1 Gerrit-Owner: Philip Chen <philipchen(a)google.com> Gerrit-MessageType: newchange

5 8

Change in em100[master]: firmware.c: Check pointer returned by malloc
by Patrick Georgi (Code Review) 02 Sep '19

02 Sep '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/35066 ) Change subject: firmware.c: Check pointer returned by malloc ...................................................................... firmware.c: Check pointer returned by malloc Change-Id: Iecf92a9acc54a4ab0a94867e5db265e1db943d53 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Found-by: Coverity Scan #220610 --- M firmware.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/66/35066/1 diff --git a/firmware.c b/firmware.c index b3abafe..d15eb69 100644 --- a/firmware.c +++ b/firmware.c @@ -191,6 +191,10 @@ fseek(f, 0, SEEK_SET); fw = malloc(fsize); + if (!fw) { + printf("ERROR: out of memory.\n"); + return 0; + } if (fread(fw, fsize, 1, f) != 1) { perror(filename); fclose(f); -- To view, visit https://review.coreboot.org/c/em100/+/35066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Iecf92a9acc54a4ab0a94867e5db265e1db943d53 Gerrit-Change-Number: 35066 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: payloads/external/LinuxBoot: Add curl flag
by Marcello Sylvester Bauer (Code Review) 02 Sep '19

02 Sep '19

Marcello Sylvester Bauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35169 ) Change subject: payloads/external/LinuxBoot: Add curl flag ...................................................................... payloads/external/LinuxBoot: Add curl flag add --show-error curl flag to see the error message, even on silent mode. Signed-off-by: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Change-Id: I4ad40718caab60413ffe9c1503a9870cb875dd43 --- M payloads/external/LinuxBoot/targets/linux.mk 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/35169/1 diff --git a/payloads/external/LinuxBoot/targets/linux.mk b/payloads/external/LinuxBoot/targets/linux.mk index e32ad1e..b7b3a0d 100644 --- a/payloads/external/LinuxBoot/targets/linux.mk +++ b/payloads/external/LinuxBoot/targets/linux.mk @@ -33,7 +33,7 @@ ifeq ($(CONFIG_LINUXBOOT_KERNEL_CUSTOM),y) kernel_version:=$(CONFIG_LINUXBOOT_KERNEL_CUSTOM_VERSION) else - kernel_version:=$(shell curl -s -k https://www.kernel.org/feeds/kdist.xml | \ + kernel_version:=$(shell curl -sS -k https://www.kernel.org/feeds/kdist.xml | \ sed -n -e 's@.*<guid isPermaLink="false">$.*$</guid>.*@\1@p' | \ awk -F ',' '/$(TAG-y)/{ print $$3 }' | \ head -n 1) @@ -67,7 +67,7 @@ if [[ ! -f $(tarball_dir)/$(kernel_tarball).xz && ! -f $(tarball_dir)/$(kernel_tarball).xz ]]; then \ echo " WWW $(kernel_tarball).xz"; \ cd $(tarball_dir); \ - curl -OLs "$(kernel_mirror_path)/$(kernel_tarball).xz"; \ + curl -OLSs "$(kernel_mirror_path)/$(kernel_tarball).xz"; \ cd $(pwd); \ fi endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ad40718caab60413ffe9c1503a9870cb875dd43 Gerrit-Change-Number: 35169 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/ocp/monolake: use RW_VPD to configure FSP UPD
by Name of user not set (Code Review) 02 Sep '19

02 Sep '19

jonzhang(a)fb.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34636 ) Change subject: mb/ocp/monolake: use RW_VPD to configure FSP UPD ...................................................................... mb/ocp/monolake: use RW_VPD to configure FSP UPD Summary: This patch adds: * A framework to use VPD binary blob 2.0 data to configure FSP UPD. * A library to configure HyperThreading FSP UPD variable. The framework is added in romstage to customize FSP UPD settings. If RW_VPD and binary blob are not found, or if there is no "HyperThreading" setting in the binary blob, original configuration is used. Test Plan: * Build an OCP MonoLake coreboot image, run following command to initialize RW_VPD and insert HyperThreading key: vpd -f build/coreboot.rom -O -i RW_VPD -s 'HyperThreading=0' * Flash the image to MonoLake, boot and observe following message in boot log: Detected 16 CPU threads If RW_VPD partition does not exist, or if HyperThreading key/value pair does not exist, the boot log has: Detected 32 CPU threads Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Id66c3a7a0992037f59685c0c9250f90aefc3f105 Change-Id: I799d27734fe4b67cd1f40cae710151a01562b1b2 --- M src/mainboard/ocp/monolake/Makefile.inc M src/mainboard/ocp/monolake/romstage.c A src/mainboard/ocp/monolake/vpd_fsp.c A src/mainboard/ocp/monolake/vpd_fsp.h 4 files changed, 125 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/34636/1 diff --git a/src/mainboard/ocp/monolake/Makefile.inc b/src/mainboard/ocp/monolake/Makefile.inc index 1606476..ce674e4 100644 --- a/src/mainboard/ocp/monolake/Makefile.inc +++ b/src/mainboard/ocp/monolake/Makefile.inc @@ -13,4 +13,5 @@ ## GNU General Public License for more details. ## +romstage-y += vpd_fsp.c ramstage-y += irqroute.c diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c index f3ec7e3..4add5f1 100644 --- a/src/mainboard/ocp/monolake/romstage.c +++ b/src/mainboard/ocp/monolake/romstage.c @@ -23,6 +23,9 @@ #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/lpc.h> +#include <fmap.h> + +#include "vpd_fsp.h" /** * /brief mainboard call for setup that needs to be done before fsp init @@ -57,9 +60,61 @@ 0x0c0ca1); } +/* + * This function uses a key/value pair to configure UPD. + */ +static int board_configure_upd( + const uint8_t *key, int32_t key_len, + const uint8_t *value, int32_t value_len, + void *UpdData) +{ + set_upd_hyper_threading(key, key_len, value, value_len, UpdData); + + return VPD_OK; +} + /** - * /brief customize fsp parameters here if needed + * /brief customize fsp parameters, use data stored in VPD binary blob + * to configure FSP UPD variables. */ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) { + struct region_device rdev; + void *rw_vpd_addr = NULL; + size_t rw_vpd_size = -1; + int32_t consumed; + UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; + + /* + * If RW_VPD VPD partition exists, search key/value pairs + * to see if there are relevant FSP UPD variable setting(s). + * If so, use such setting(s) to customize FSP behavior. + */ + if (CONFIG(VPD)) { + if (!fmap_locate_area_as_rdev("RW_VPD", &rdev)) { + rdev_chain(&rdev, &rdev, GOOGLE_VPD_2_0_OFFSET, + region_device_sz(&rdev) - GOOGLE_VPD_2_0_OFFSET); + rw_vpd_addr = rdev_mmap_full(&rdev); + if (rw_vpd_addr != NULL) { + rw_vpd_size = region_device_sz(&rdev); + /* Skip the VPD info header */ + rw_vpd_addr += sizeof(struct google_vpd_info); + rw_vpd_size -= sizeof(struct google_vpd_info); + /* + * decodeVpdString() is called iteratively to process + * key/value pairs in RW_VPD iteratively. In such + * processing, callback function board_configure_upd() + * is called to process a pair and update FSP UPD + * variable. + */ + for (consumed = 0; consumed < rw_vpd_size; ) { + if (decodeVpdString(rw_vpd_size, rw_vpd_addr, &consumed, + board_configure_upd, (void *)UpdData) == VPD_FAIL) + break; + } + printk(FSP_INFO_LEVEL, + "Found and Processed VPD binary blob in RW_VPD.\n"); + } + } + }; } diff --git a/src/mainboard/ocp/monolake/vpd_fsp.c b/src/mainboard/ocp/monolake/vpd_fsp.c new file mode 100644 index 0000000..ee5c9ca --- /dev/null +++ b/src/mainboard/ocp/monolake/vpd_fsp.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 The coreboot Authors. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * This file is part of the coreboot project. + */ +#include <string.h> +#include <drivers/vpd/vpd_fsp.h> +#include "vpd_fsp.h" + +/* + * For "HyperThreading" UPD variable, given a key/value + * pair, use the value to set the variable if there is match. + */ +void set_upd_hyper_threading(const uint8_t *key, + const int32_t key_len, const uint8_t *value, const int32_t value_len, + UPD_DATA_REGION *UpdData) +{ + uint8_t val; + if (set_upd_bool(FSP_VAR_HYPERTHREADING, key, key_len, value, + value_len, &val) == true) { + UpdData->HyperThreading = val; + } +} diff --git a/src/mainboard/ocp/monolake/vpd_fsp.h b/src/mainboard/ocp/monolake/vpd_fsp.h new file mode 100644 index 0000000..1e0965a --- /dev/null +++ b/src/mainboard/ocp/monolake/vpd_fsp.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 The coreboot Authors. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MB_OCP_MONOLAKE_VPD_FSP__ +#define __MB_OCP_MONOLAKE_VPD_FSP__ + +#include <drivers/vpd/lib_vpd.h> +#include <drivers/vpd/vpd_fsp.h> +#include <drivers/vpd/vpd_tables.h> +#include <inttypes.h> +#include <fsp.h> + +/* Define the strings for UPD variables that could be customized */ +#define FSP_VAR_HYPERTHREADING "HyperThreading" + +/* + * For "HyperThreading" UPD variable, given a key/value + * pair, use the value to set the variable if there is match. + */ +void set_upd_hyper_threading(const uint8_t *key, + const int32_t key_len, const uint8_t *value, const int32_t value_len, + UPD_DATA_REGION *UpdData); +#endif /* __MB_OCP_MONOLAKE_VPD_FSP__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I799d27734fe4b67cd1f40cae710151a01562b1b2 Gerrit-Change-Number: 34636 Gerrit-PatchSet: 1 Gerrit-Owner: jonzhang(a)fb.com Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/vpd: Set bool type variable matching with key/value pair
by Name of user not set (Code Review) 02 Sep '19

02 Sep '19

jonzhang(a)fb.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34634 ) Change subject: drivers/vpd: Set bool type variable matching with key/value pair ...................................................................... drivers/vpd: Set bool type variable matching with key/value pair Summary: Give a key/value pair in VPD binary blob, and name of a bool type variable, set the variable value if there is a match. Several checks are in place: * The key/value length needs to be correct. * The key name needs to match. * THe value is either '1' or '0'. Test Plan: * Build an OCP MonoLake coreboot image, flash and run. Reviewers: dhendrix, hpe, anpetrov Subscribers: Tasks: Tags: Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Iebdba59419a555147fc40391cf17cc6879d9e1b2 --- M src/drivers/vpd/Makefile.inc A src/drivers/vpd/vpd_fsp.c A src/drivers/vpd/vpd_fsp.h 3 files changed, 77 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/34634/1 diff --git a/src/drivers/vpd/Makefile.inc b/src/drivers/vpd/Makefile.inc index 17019b5..368024b 100644 --- a/src/drivers/vpd/Makefile.inc +++ b/src/drivers/vpd/Makefile.inc @@ -1,2 +1,2 @@ -romstage-$(CONFIG_VPD) += vpd_decode.c +romstage-$(CONFIG_VPD) += vpd_decode.c vpd_fsp.c ramstage-$(CONFIG_VPD) += vpd.c vpd_decode.c diff --git a/src/drivers/vpd/vpd_fsp.c b/src/drivers/vpd/vpd_fsp.c new file mode 100644 index 0000000..adff8e9 --- /dev/null +++ b/src/drivers/vpd/vpd_fsp.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 The coreboot Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + */ +#include <string.h> +#include "vpd_fsp.h" + +/* + * Process UPD variable of boolean type. + * Match the variable name with key name in the key/value pair, + * use the value to set *val. + * During the process, necessary checking is done, such as making + * sure the value length is 1, and value is either '1' or '0'. + */ +bool set_upd_bool(const char *upd_var, + const uint8_t *key, const int32_t key_len, + const uint8_t *value, const int32_t value_len, + uint8_t *val) +{ + int i; + /* Check key length and value length */ + if (key_len != strlen(upd_var) || value_len != 1) + return false; + + /* Matching key with variable name */ + for (i = 0; i < key_len; i++) { + if (key[i] != upd_var[i]) + return false; + } + + /* Make sure the value is either '1' or '0' */ + if (*value == '1') { + *val = 1; + return true; + } else if (*value == '0') { + *val = 0; + return true; + } else + return false; +} diff --git a/src/drivers/vpd/vpd_fsp.h b/src/drivers/vpd/vpd_fsp.h new file mode 100644 index 0000000..c59f249 --- /dev/null +++ b/src/drivers/vpd/vpd_fsp.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 The coreboot Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + */ + +#ifndef __VPD_FSP__ +#define __VPD_FSP__ + +#include <inttypes.h> + +#define GOOGLE_VPD_2_0_OFFSET 0x600 + +/* + * Process UPD variable of boolean type. + * + * Match the variable name with key name in the key/value pair, + * use the value to set *val. + * During the process, necessary checking is done, such as making + * sure the value length is 1, and value is either '1' or '0'. + * + * If there is a match and checking is successful, set *val + * accordingly, and return true; otherwise return false. + */ +bool set_upd_bool(const char *upd_var, + const uint8_t *key, const int32_t key_len, + const uint8_t *value, const int32_t value_len, + uint8_t *val); +#endif /* __VPD_FSP__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebdba59419a555147fc40391cf17cc6879d9e1b2 Gerrit-Change-Number: 34634 Gerrit-PatchSet: 1 Gerrit-Owner: jonzhang(a)fb.com Gerrit-MessageType: newchange

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Change in coreboot[master]: mediatek/mt8183: Set DRAM voltage for each DRAM frequency
by Yu-Ping Wu (Code Review) 02 Sep '19

02 Sep '19

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35017 ) Change subject: mediatek/mt8183: Set DRAM voltage for each DRAM frequency ...................................................................... Patch Set 6: (3 comments) https://review.coreboot.org/c/coreboot/+/35017/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35017/2//COMMIT_MSG@7 PS2, Line 7: vlotage > voltage Done https://review.coreboot.org/c/coreboot/+/35017/2//COMMIT_MSG@7 PS2, Line 7: vlotage > voltage Done https://review.coreboot.org/c/coreboot/+/35017/5/src/soc/mediatek/mt8183/em… File src/soc/mediatek/mt8183/emi.c: https://review.coreboot.org/c/coreboot/+/35017/5/src/soc/mediatek/mt8183/em… PS5, Line 47: voltage_LP4X Use lower case variable names. -- To view, visit https://review.coreboot.org/c/coreboot/+/35017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Gerrit-Change-Number: 35017 Gerrit-PatchSet: 6 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 02 Sep 2019 06:32:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mediatek/mt8183: Set DRAM voltage for each DRAM frequency
by Yu-Ping Wu (Code Review) 02 Sep '19

02 Sep '19

Yu-Ping Wu has uploaded a new patch set (#6) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/35017 ) Change subject: mediatek/mt8183: Set DRAM voltage for each DRAM frequency ...................................................................... mediatek/mt8183: Set DRAM voltage for each DRAM frequency Adjust voltage for each DRAM frequency. BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h 2 files changed, 54 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/35017/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/35017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9539473ff708f9d0d39eb17bd3fdcb916265d33e Gerrit-Change-Number: 35017 Gerrit-PatchSet: 6 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mediatek/mt8183: Enable DRAM frequency 3600Mbps for EMCP DDR
by Yu-Ping Wu (Code Review) 02 Sep '19

02 Sep '19

Yu-Ping Wu has uploaded a new patch set (#14) to the change originally created by huayang duan. ( https://review.coreboot.org/c/coreboot/+/34990 ) Change subject: mediatek/mt8183: Enable DRAM frequency 3600Mbps for EMCP DDR ...................................................................... mediatek/mt8183: Enable DRAM frequency 3600Mbps for EMCP DDR Devices using EMCP may run in a high DRAM frequency (e.g., 3600Mbps) while discrete DRAM can only run at 3200Mbps. This patch enables 3600Mbps for EMCP DDR for better system performance. BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test pass on Kukui. Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/emi.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/34990/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/34990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656 Gerrit-Change-Number: 34990 Gerrit-PatchSet: 14 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: SJ Huang <sj.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vboot: remove fastboot support
by Joel Kitching (Code Review) 02 Sep '19

02 Sep '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35002 ) Change subject: vboot: remove fastboot support ...................................................................... vboot: remove fastboot support BUG=b:124141368, chromium:995172 TEST=make clean && make test-abuild BRANCH=none Change-Id: I06ea816ffb910163ec2c3c456b3c09408c806d0b Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/ec/google/chromeec/switches.c M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc 3 files changed, 3 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35002/1 diff --git a/src/ec/google/chromeec/switches.c b/src/ec/google/chromeec/switches.c index 7b3f4d4..3fd3808 100644 --- a/src/ec/google/chromeec/switches.c +++ b/src/ec/google/chromeec/switches.c @@ -34,10 +34,9 @@ (google_chromeec_get_switches() & EC_SWITCH_DEDICATED_RECOVERY)) return 1; - /* Check if the EC has posted the keyboard recovery/fastboot event. */ + /* Check if the EC has posted the keyboard recovery event. */ return !!(google_chromeec_get_events_b() & - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) | - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT))); + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } int get_recovery_mode_retrain_switch(void) @@ -68,6 +67,5 @@ /* Clear all host event bits requesting recovery mode. */ return google_chromeec_clear_events_b( EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) | - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT) | - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT)); + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT)); } diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index c5146c6..1e372d8 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -286,10 +286,6 @@ bool "Disable shutdown on closed lid" default n -config GBB_FLAG_FORCE_DEV_BOOT_FASTBOOT_FULL_CAP - bool "Allow fastboot even if dev_boot_fastboot_full_cap=0" - default n - config GBB_FLAG_FORCE_MANUAL_RECOVERY bool "Always assume manual recovery in recovery mode" default n diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index d554f10..3078e30 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -220,7 +220,6 @@ $(call bool-to-mask,$(CONFIG_GBB_FLAG_DEFAULT_DEV_BOOT_LEGACY),0x400) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC),0x800) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_DISABLE_LID_SHUTDOWN),0x1000) \ - $(call bool-to-mask,$(CONFIG_GBB_FLAG_FORCE_DEV_BOOT_FASTBOOT_FULL_CAP),0x2000) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_FORCE_MANUAL_RECOVERY),0x4000) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_DISABLE_FWMP),0x8000) \ ) -- To view, visit https://review.coreboot.org/c/coreboot/+/35002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06ea816ffb910163ec2c3c456b3c09408c806d0b Gerrit-Change-Number: 35002 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2019