coreboot-gerrit September 2019

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Change in ...coreboot[master]: mb/*: Use common IPMI KCS driver
by Patrick Rudolph (Code Review) 02 Sep '19

02 Sep '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33490 Change subject: mb/*: Use common IPMI KCS driver ...................................................................... mb/*: Use common IPMI KCS driver Remove duplicated code and instead use the IPMI KCS driver, which provides the same functionality. Change-Id: I419713c9bef02084cca1ff4cf11c33c2e3e8d3c1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/asus/kgpe-d16/Kconfig M src/mainboard/asus/kgpe-d16/devicetree.cb M src/mainboard/asus/kgpe-d16/dsdt.asl M src/mainboard/asus/kgpe-d16/mainboard.c M src/mainboard/ocp/monolake/Kconfig M src/mainboard/ocp/monolake/devicetree.cb M src/mainboard/ocp/monolake/dsdt.asl M src/mainboard/ocp/monolake/mainboard.c 8 files changed, 7 insertions(+), 171 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/33490/1 diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index 32c4dbc..64beaf0 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -33,6 +33,7 @@ select DRIVERS_ASPEED_AST2050 select MAINBOARD_FORCE_NATIVE_VGA_INIT select POWER_STATE_DEFAULT_ON_AFTER_FAILURE + select IPMI_KCS config MAINBOARD_DIR string diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb index 0ea4216..31bd3e3 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb @@ -217,7 +217,7 @@ chip drivers/pc80/tpm device pnp 4e.0 on end # TPM module end - chip drivers/generic/generic # BMC KCS + chip drivers/ipmi # BMC KCS device pnp ca2.0 on end end end diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl index ea52488..efb67a5 100644 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -53,9 +53,6 @@ #include <southbridge/amd/common/acpi/sleepstates.asl> - /* IPMI KCS enable */ - Name (KCSE, 0x1) - /* The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. * @@ -489,13 +486,6 @@ Name (_HID, EisaId ("PNP0A05")) Name (_ADR, 0x00140003) - OperationRegion (BMRG, SystemIO, 0xca2, 0x02) /* BMC KCS registers */ - Field (BMRG, AnyAcc, NoLock, Preserve) - { - BMRI, 8, /* Index */ - BMRD, 8, /* Data */ - } - /* Real Time Clock Device */ Device(RTC0) { Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ @@ -617,27 +607,6 @@ }) } } - - Device (KCS1) { /* IPMI KCS */ - Name (_HID, EISAID ("IPI0001")) /* ASpeed BMC */ - Method (_STA, 0, NotSerialized) { - If (KCSE) { /* Detection enabled */ - If (LNotEqual (BMRD, 0xff)) { - Return (0x0f) /* Device present */ - } - Return (Zero) - } - Return (Zero) - } - Method (_CRS, 0) { - Return (ResourceTemplate() { - IO(Decode16, 0x0ca2, 0x0ca2, 0x01, 0x02) - }) - } - Method (_IFT, 0, NotSerialized) { /* Interface type */ - Return (One) /* KCS interface */ - } - } } /* High Precision Event Timer */ diff --git a/src/mainboard/asus/kgpe-d16/mainboard.c b/src/mainboard/asus/kgpe-d16/mainboard.c index 14bb986..a03953b 100644 --- a/src/mainboard/asus/kgpe-d16/mainboard.c +++ b/src/mainboard/asus/kgpe-d16/mainboard.c @@ -47,7 +47,6 @@ * enable the dedicated function in kgpe-d16 board. * This function is called earlier than sr5650_enable. *************************************************/ -#define BMC_KCS_BASE 0xca2 static void mainboard_enable(struct device *dev) { @@ -69,13 +68,6 @@ set_pcie_dereset(); /* get_ide_dma66(); */ - - /* Enable access to the BMC IPMI via KCS */ - struct device *lpc_sio_dev = dev_find_slot_pnp(BMC_KCS_BASE, 0); - struct resource *res = new_resource(lpc_sio_dev, BMC_KCS_BASE); - res->base = BMC_KCS_BASE; - res->size = 1; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } /* override the default SATA PHY setup */ diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig index 037c322..7af4ae9 100644 --- a/src/mainboard/ocp/monolake/Kconfig +++ b/src/mainboard/ocp/monolake/Kconfig @@ -13,6 +13,7 @@ select MAINBOARD_USES_IFD_GBE_REGION select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 + select IPMI_KCS config INTEGRATED_UART def_bool n diff --git a/src/mainboard/ocp/monolake/devicetree.cb b/src/mainboard/ocp/monolake/devicetree.cb index 2d91b73..5b990db 100644 --- a/src/mainboard/ocp/monolake/devicetree.cb +++ b/src/mainboard/ocp/monolake/devicetree.cb @@ -11,8 +11,10 @@ chip drivers/pc80/tpm device pnp 0c31.0 on end end - chip drivers/generic/generic # BMC KCS - device pnp ca2.0 on end + chip drivers/ipmi # BMC KCS + device pnp ca2.0 on + register "bmc_i2c_address" = "0x20" + end end end # LPC Bridge device pci 1f.2 on end # SATA Controller diff --git a/src/mainboard/ocp/monolake/dsdt.asl b/src/mainboard/ocp/monolake/dsdt.asl index 72b1c3c..1248703 100644 --- a/src/mainboard/ocp/monolake/dsdt.asl +++ b/src/mainboard/ocp/monolake/dsdt.asl @@ -27,9 +27,6 @@ { #include "acpi/platform.asl" - Name (IDTP, 0x0CA2) - Name (ICDP, 0x0CA6) - Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) @@ -293,97 +290,5 @@ } } - Scope (_SB.PCI0.LPC0) - { - Device (SPMI) - { - Name (_HID, EisaId ("IPI0001")) - Name (_STR, Unicode ("IPMI_KCS")) - Name (_UID, 0x00) - OperationRegion (IPST, SystemIO, ICDP, 0x01) - Field (IPST, ByteAcc, NoLock, Preserve) - { - STAS, 8 - } - Method (_STA, 0, NotSerialized) { - Return (0x0f) - } - Name (ICRS, ResourceTemplate () - { - IO (Decode16, - 0x0000, - 0x0000, - 0x00, - 0x00, - _Y01) - IO (Decode16, - 0x0000, - 0x0000, - 0x00, - 0x00, - _Y02) - - }) - Method (_CRS, 0, NotSerialized) - { - CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MIN, IPDB) - CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MAX, IPDH) - CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._LEN, IPDL) - CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MIN, IPCB) - CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MAX, IPCH) - CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._LEN, IPCL) - - IPDB = IDTP - IPDH = IDTP - IPDL = 0x01 - - IPCB = ICDP - IPCH = ICDP - IPCL = 0x01 - - Return (ICRS) - } - Method (_IFT, 0, NotSerialized) { - Return (0x01) - } - Method(_SRV, 0, NotSerialized) { - Return (0x0200) - } - } - - Device (SYSR) - { - Name (_HID, EisaId ("PNP0C02")) - - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - IO (Decode16, - 0x0CA2, - 0x0CA2, - 0x01, - 0x01, - ) - IO (Decode16, - 0x0CA6, - 0x0CA6, - 0x01, - 0x01, - ) - IO (Decode16, - 0x0CA8, - 0x0CA8, - 0x01, - 0x01, - ) - IO (Decode16, - 0x0CAC, - 0x0CAC, - 0x01, - 0x01, - ) - }) - } - } - #include "acpi/mainboard.asl" } diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c index bbfeeaf..4395436 100644 --- a/src/mainboard/ocp/monolake/mainboard.c +++ b/src/mainboard/ocp/monolake/mainboard.c @@ -20,46 +20,12 @@ #include <x86emu/x86emu.h> #endif -#define BMC_KCS_BASE 0xca2 -#define INTERFACE_IS_IO 0x1 - -#if CONFIG(GENERATE_SMBIOS_TABLES) -static int mainboard_smbios_data(struct device *dev, int *handle, - unsigned long *current) -{ - int len = 0; - - // add IPMI Device Information - len += smbios_write_type38( - current, handle, - SMBIOS_BMC_INTERFACE_KCS, - 0x20, // IPMI Version - 0x20, // I2C address - 0xff, // no NV storage - BMC_KCS_BASE | INTERFACE_IS_IO, // IO port interface address - 0x40, - 0); // no IRQ - - return len; -} -#endif - /* * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ static void mainboard_enable(struct device *dev) { -#if CONFIG(GENERATE_SMBIOS_TABLES) - dev->ops->get_smbios_data = mainboard_smbios_data; -#endif - - /* Enable access to the BMC IPMI via KCS */ - struct device *lpc_sio_dev = dev_find_slot_pnp(BMC_KCS_BASE, 0); - struct resource *res = new_resource(lpc_sio_dev, BMC_KCS_BASE); - res->base = BMC_KCS_BASE; - res->size = 1; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I419713c9bef02084cca1ff4cf11c33c2e3e8d3c1 Gerrit-Change-Number: 33490 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: drivers/ipmi/ipmi_kcs_ops: Advertise correct register spacing
by Patrick Rudolph (Code Review) 02 Sep '19

02 Sep '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35152 ) Change subject: drivers/ipmi/ipmi_kcs_ops: Advertise correct register spacing ...................................................................... drivers/ipmi/ipmi_kcs_ops: Advertise correct register spacing Advertise the register spacing used by the BMC as set by the Kconfig. Needs test on FB Watson and OCP Weedge100s. Change-Id: Ib926d30f6a0e78fbf613a6f71f765c5f51eee77d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/ipmi/ipmi_kcs_ops.c 1 file changed, 28 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/35152/1 diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 21102bb..21f927e 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -126,10 +126,21 @@ u32 apic_interrupt = 0; acpi_addr_t addr = { .space_id = ACPI_ADDRESS_SPACE_IO, - .access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS, .addrl = dev->path.pnp.port, }; + switch (CONFIG_IPMI_KCS_REGISTER_SPACING) { + case 4: + addr.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + break; + case 16: + default: /* fallthrough */ + printk(BIOS_ERR, "IPMI: Unsupported register spacing for SPMI\n"); + case 1: /* fallthrough */ + addr.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + break; + } + current = ALIGN_UP(current, 8); printk(BIOS_DEBUG, "ACPI: * SPMI at %lx\n", current); spmi = (struct acpi_spmi *)current; @@ -214,6 +225,8 @@ struct drivers_ipmi_config *conf = NULL; u8 nv_storage = 0xff; u8 i2c_address = 0; + u8 register_spacing; + int len = 0; if (dev->chip_info) @@ -225,6 +238,20 @@ i2c_address = conf->bmc_i2c_address; } + switch (CONFIG_IPMI_KCS_REGISTER_SPACING) { + case 4: + register_spacing = 1 << 6; + break; + case 16: + register_spacing = 2 << 6; + break; + default: + printk(BIOS_ERR, "IPMI: Unsupported register spacing for SMBIOS\n"); + case 1: /* fallthrough */ + register_spacing = 0 << 6; + break; + } + // add IPMI Device Information len += smbios_write_type38( current, handle, -- To view, visit https://review.coreboot.org/c/coreboot/+/35152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib926d30f6a0e78fbf613a6f71f765c5f51eee77d Gerrit-Change-Number: 35152 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: security/intel: Add TXT infrastructure
by Patrick Rudolph (Code Review) 02 Sep '19

02 Sep '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34585 ) Change subject: security/intel: Add TXT infrastructure ...................................................................... security/intel: Add TXT infrastructure * Add Kconfig to enable TXT * Add possibility to add BIOS and SINIT ACMs * Set default BIOS ACM alignment * Increase FIT space if TXT is enabled The following commits depend on the basic Kconfig infrastructure. Intel TXT isn't supported until all following commits are merged. Change-Id: I5f0f956d2b7ba43d4e7e0062803c6d8ba569a052 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/security/intel/txt.md M src/cpu/intel/fit/Kconfig M src/security/Kconfig M src/security/Makefile.inc A src/security/intel/Kconfig A src/security/intel/Makefile.inc A src/security/intel/txt/Kconfig A src/security/intel/txt/Makefile.inc M src/soc/intel/cannonlake/Kconfig M src/soc/intel/skylake/Kconfig 10 files changed, 115 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/34585/1 diff --git a/Documentation/security/intel/txt.md b/Documentation/security/intel/txt.md index f67b639..f80a731 100644 --- a/Documentation/security/intel/txt.md +++ b/Documentation/security/intel/txt.md @@ -90,11 +90,11 @@ ## For developers ### Configuring Intel TXT in Kconfig -Enable ``TEE_INTEL_TXT`` and set the following: +Enable ``INTEL_TXT`` and set the following: -``TEE_INTEL_TXT_BIOSACM_FILE`` to the path of the BIOS ACM provided by Intel +``INTEL_TXT_BIOSACM_FILE`` to the path of the BIOS ACM provided by Intel -``TEE_INTEL_TXT_SINITACM_FILE`` to the path of the SINIT ACM provided by Intel +``INTEL_TXT_SINITACM_FILE`` to the path of the SINIT ACM provided by Intel ### Print TXT status as early as possible Add platform code to print the TXT status as early as possible, as the register is cleared on cold reset. diff --git a/src/cpu/intel/fit/Kconfig b/src/cpu/intel/fit/Kconfig index e48dca9..fa10802 100644 --- a/src/cpu/intel/fit/Kconfig +++ b/src/cpu/intel/fit/Kconfig @@ -5,6 +5,7 @@ config CPU_INTEL_NUM_FIT_ENTRIES int + default 16 if INTEL_TXT default 4 depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE help diff --git a/src/security/Kconfig b/src/security/Kconfig index 8a1531a..4e08bbd 100644 --- a/src/security/Kconfig +++ b/src/security/Kconfig @@ -15,3 +15,4 @@ source "src/security/vboot/Kconfig" source "src/security/tpm/Kconfig" source "src/security/memory/Kconfig" +source "src/security/intel/Kconfig" diff --git a/src/security/Makefile.inc b/src/security/Makefile.inc index f62413e..fd78438 100644 --- a/src/security/Makefile.inc +++ b/src/security/Makefile.inc @@ -1,3 +1,4 @@ subdirs-y += vboot subdirs-y += tpm subdirs-y += memory +subdirs-y += intel diff --git a/src/security/intel/Kconfig b/src/security/intel/Kconfig new file mode 100644 index 0000000..333e385 --- /dev/null +++ b/src/security/intel/Kconfig @@ -0,0 +1,20 @@ +## This file is part of the coreboot project. +## +## Copyright (C) 2019 9elements Agency GmbH +## Copyright (C) 2019 Facebook Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +menu "Intel" + +source "src/security/intel/txt/Kconfig" + +endmenu # Intel diff --git a/src/security/intel/Makefile.inc b/src/security/intel/Makefile.inc new file mode 100644 index 0000000..9388d3f --- /dev/null +++ b/src/security/intel/Makefile.inc @@ -0,0 +1 @@ +subdirs-y += txt diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig new file mode 100644 index 0000000..b6c5d19 --- /dev/null +++ b/src/security/intel/txt/Kconfig @@ -0,0 +1,55 @@ +## This file is part of the coreboot project. +## +## Copyright (C) 2019 9elements Agency GmbH +## Copyright (C) 2019 Facebook Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config INTEL_TXT + bool "Intel TXT support" + default n + select MRC_SETTINGS_PROTECT if CACHE_MRC_SETTINGS + select SOC_INTEL_COMMON_BLOCK_VMX if PLATFORM_USES_FSP2_0 + select AP_IN_SIPI_WAIT + depends on TSC_CONSTANT_RATE + depends on (TPM1 || TPM2) + depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE + depends on PLATFORM_HAS_DRAM_CLEAR + depends on SOC_INTEL_FSP_BROADWELL_DE || SOC_INTEL_COMMON_BLOCK_SA + +if INTEL_TXT + +config INTEL_TXT_BIOSACM_FILE + string "BIOS ACM file" + default "3rdparty/blobs/soc/intel/fsp_broadwell_de/biosacm.bin" if SOC_INTEL_FSP_BROADWELL_DE + default "3rdparty/blobs/soc/intel/skylake/biosacm.bin" if SOC_INTEL_COMMON_SKYLAKE_BASE + help + Intel TXT BIOS ACM file. This file can be obtained by privileged + access to intel resources. Or for some platforms found inside the + blob repository. + +config INTEL_TXT_SINITACM_FILE + string "SINIT ACM file" + default "3rdparty/blobs/soc/intel/fsp_broadwell_de/sinitacm.bin" if SOC_INTEL_FSP_BROADWELL_DE + default "3rdparty/blobs/soc/intel/skylake/sinitacm.bin" if SOC_INTEL_COMMON_SKYLAKE_BASE + help + Intel TXT SINIT ACM file. This file can be obtained by privileged + access to intel resources. Or for some platforms found inside the + blob repository. + +config INTEL_TXT_BIOSACM_ALIGNMENT + hex + default 0x20000 # 128KB + help + Exceptions are Ivy- and Sandybridge with 64KB and Purely with 256KB + alignment size. Please overwrite it SoC specific. + +endif diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc new file mode 100644 index 0000000..f123510 --- /dev/null +++ b/src/security/intel/txt/Makefile.inc @@ -0,0 +1,25 @@ +ifeq ($(CONFIG_INTEL_TXT),y) + +cbfs-files-y += txt_bios_acm.bin +txt_bios_acm.bin-file := $(CONFIG_INTEL_TXT_BIOSACM_FILE) +txt_bios_acm.bin-type := raw +txt_bios_acm.bin-align := $(CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT) + +cbfs-files-($(CONFIG_INTEL_FIT_BIOS_POLICY)) += txt_bios_policy.bin +txt_bios_policy.bin-file := $(objgenerated)/txt_bios_policy.bin +txt_bios_policy.bin-type := raw +txt_bios_policy.bin-align := 0x10 + +ifneq ($(CONFIG_INTEL_TXT_SINITACM_FILE),"") +cbfs-files-y += txt_sinit_acm.bin +txt_sinit_acm.bin-file := $(CONFIG_INTEL_TXT_SINITACM_FILE) +txt_sinit_acm.bin-type := raw +txt_sinit_acm.bin-align := 0x10 +txt_sinit_acm.bin-compression := lzma +endif + +INTERMEDIATE+=add_acm_fit +add_acm_fit: $(obj)/coreboot.pre $(IFITTOOL) + $(IFITTOOL) -r COREBOOT -a -n txt_bios_acm.bin -t 2 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< + +endif diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f859cd5..a63b829 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -319,4 +319,8 @@ hex default 0xe00 +config INTEL_TXT_BIOSACM_ALIGNMENT + hex + default 0x40000 # 256KB + endif diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f36d5ca..310619e 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -309,4 +309,8 @@ string default "sklkbl" +config INTEL_TXT_BIOSACM_ALIGNMENT + hex + default 0x40000 # 256KB + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f0f956d2b7ba43d4e7e0062803c6d8ba569a052 Gerrit-Change-Number: 34585 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: Add Razer Blade Stealth (2016) H2U
by Angel Pons (Code Review) 01 Sep '19

01 Sep '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34475 ) Change subject: Add Razer Blade Stealth (2016) H2U ...................................................................... Patch Set 33: Code-Review+2 (10 comments) Juuuust stupid details https://review.coreboot.org/c/coreboot/+/34475/33//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/34475/33//COMMIT_MSG@13 PS33, Line 13: memory in dualchannel mode I'd say these lines are too long for a commit message, mind splitting them? https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/Kconf… File src/mainboard/razer/Kconfig: https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/Kconf… PS33, Line 13: MAINBOARD_VENDOR defined here already https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/Kconf… File src/mainboard/razer/Kconfig.name: https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/Kconf… PS33, Line 2: Razer please make it uppercase "RAZER" for consistency https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_kbl/Kconfig: https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… PS33, Line 33: : : config MAINBOARD_VENDOR : string : default "RAZER" Shouldn't need to redefine this https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… PS33, Line 59: config CPU_MICROCODE_CBFS_LEN : hex : default 0x18000 : : config CPU_MICROCODE_CBFS_LOC : hex : default 0xFFE115A0 Is it needed to specify the microcode length and location? https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… PS33, Line 22: # For now no way to choose the correct the available RAM : config BOARD_RAZER_BLADE_STEALTH_KBL_16GB : bool "16GB RAM (4x MT52L1G32D4PG)" : default n : : config VGA_BIOS_ID : string : default "8086,5916" : : config IRQ_SLOT_COUNT : int : default 18 : : config MAINBOARD_VENDOR : string : default "RAZER" : : config MAINBOARD_FAMILY : string : default "BLADE_STEALTH" : : config MAINBOARD_PART_NUMBER : string : default "H2U" : : config MAINBOARD_VERSION : string : default "1.0" : : config MAINBOARD_DIR : string : default "razer/blade_stealth_kbl" : : config MAX_CPUS : int : default 4 : : config CPU_MICROCODE_CBFS_LEN : hex : default 0x18000 : : config CPU_MICROCODE_CBFS_LOC : hex : default 0xFFE115A0 : : config CBFS_SIZE : hex : default 0x5c0000 These are usually not indented https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_kbl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… PS33, Line 39: register "SataPortsDevSlp[0]" = "0" : register "SataPortsDevSlp[2]" = "0" : register "SataSpeedLimit" = "2" I don't think you need to set these with SATA ports disabled https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… PS33, Line 199: [ Is this used? https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… PS33, Line 216: d Is this used? https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_kbl/mainboard.c: https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… PS33, Line 47: MAX_SERIAL_LENGTH); Minor: fits on the previous line -- To view, visit https://review.coreboot.org/c/coreboot/+/34475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Gerrit-Change-Number: 34475 Gerrit-PatchSet: 33 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 01 Sep 2019 23:01:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Felix Held (Code Review) 01 Sep '19

01 Sep '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... Patch Set 82: (1 comment) https://review.coreboot.org/c/coreboot/+/32734/82/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb: https://review.coreboot.org/c/coreboot/+/32734/82/src/mainboard/supermicro/… PS82, Line 239: device pnp 2e.0 on please comment that this is only to pass the sio base address to the sio ssdt generator as i requested earlier -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 82 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 01 Sep 2019 22:54:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Add Razer Blade Stealth (2016) H2U
by Angel Pons (Code Review) 01 Sep '19

01 Sep '19

1 0

Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Philipp Deppenwiese (Code Review) 01 Sep '19

01 Sep '19

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... Patch Set 82: @Angel We will follow-up addressing the rest of the comments. It's not good to do everything in one patch. That is also a policy here. -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 82 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 01 Sep 2019 22:39:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Angel Pons (Code Review) 01 Sep '19

01 Sep '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... Patch Set 82: (9 comments) Now that this was merged, marked a few things that were not actually resolved yet, for ease of tracking. https://review.coreboot.org/c/coreboot/+/32734/74/Documentation/mainboard/s… File Documentation/mainboard/supermicro/x11ssh-tf.md: https://review.coreboot.org/c/coreboot/+/32734/74/Documentation/mainboard/s… PS74, Line 30: S5 resume > Done Not done https://review.coreboot.org/c/coreboot/+/32734/74/Documentation/mainboard/s… PS74, Line 37: 10GB > Done Not done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/Kconfig: https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 67: : config SUBSYSTEM_VENDOR_ID : hex : default 0x8086 > Done I see... Then, it should match the subsystem ID on the devicetree. https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/Kconfig.name: https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 1: BOARD_SUPERMICRO_X11SSH_PLUS_TF : bool "X11SSH+-TF" > Done Not done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/bootblock.c: https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 37: garbeled > Done Not done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb: https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 203: device domain 0 on > We will do it in a follow-up. Not done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 208: JPCIE1 > Done Not done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 216: JPCIE1 > Done Not done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 219: device pci 00.0 on end # Aspeed 2400 VGA > Done still curious about it -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 82 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 01 Sep 2019 22:33:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Angel Pons (Code Review) 01 Sep '19

01 Sep '19

1 0

Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Philipp Deppenwiese (Code Review) 01 Sep '19

01 Sep '19

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... mb/supermicro/x11ssh: Add Supermicro X11SSH-TF Add support for the X11SSH-TF which is based on Intel KBL. Working: * SeaBIOS payload * LinuxBoot payload * IPMI of BMC * PCIe, SATA, USB and M.2 ports * RS232 serial * Native graphics init Not working: * TianoCore doesn't work yet as the Aspeed NGI is text mode only. * Intel SGX, due to random crashes in soc/intel/common For more details have a look at the documentation. Please apply those patches as well for good user experience: Ica0c20255f661dd61edc3a7d15646b7447c4658e Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Signed-off-by: Felix Singer <felix.singer(a)9elements.com> Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32734 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/supermicro/x11ssh-tf.md A Documentation/mainboard/supermicro/x11ssh_flash.jpg A src/mainboard/supermicro/x11ssh/Kconfig A src/mainboard/supermicro/x11ssh/Kconfig.name A src/mainboard/supermicro/x11ssh/Makefile.inc A src/mainboard/supermicro/x11ssh/acpi/ec.asl A src/mainboard/supermicro/x11ssh/acpi/mainboard.asl A src/mainboard/supermicro/x11ssh/acpi/superio.asl A src/mainboard/supermicro/x11ssh/acpi_tables.c A src/mainboard/supermicro/x11ssh/board_info.txt A src/mainboard/supermicro/x11ssh/bootblock.c A src/mainboard/supermicro/x11ssh/cmos.layout A src/mainboard/supermicro/x11ssh/dsdt.asl A src/mainboard/supermicro/x11ssh/gpio.h A src/mainboard/supermicro/x11ssh/ramstage.c A src/mainboard/supermicro/x11ssh/romstage.c A src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt A src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb A src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd 20 files changed, 989 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 0f3105f..08689b7 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -111,6 +111,7 @@ ## Supermicro - [X10SLM+-F](supermicro/x10slm-f.md) +- [X11SSH-TF](supermicro/x11ssh-tf.md) ## UP diff --git a/Documentation/mainboard/supermicro/x11ssh-tf.md b/Documentation/mainboard/supermicro/x11ssh-tf.md new file mode 100644 index 0000000..a9dc838 --- /dev/null +++ b/Documentation/mainboard/supermicro/x11ssh-tf.md @@ -0,0 +1,74 @@ +# Supermicro X11SSH-TF + +This section details how to run coreboot on the [Supermicro X11SSH-TF]. + +## Required proprietary blobs + +* [Intel FSP2.0] +* Intel ME + +## Flashing coreboot + +The board can be flashed externally using *some* programmers. +The CH341 was found working, while Dediprog won't detect the chip. + +For more details have a look at the [flashing tutorial]. + +The flash IC can be found between the two PCIe slots near the southbridge: +![](x11ssh_flash.jpg) + +## BMC (IPMI) + +This board has an ASPEED [AST2400], which has BMC functionality. The +BMC firmware resides in a 32 MiB SOIC-16 chip in the corner of the +mainboard near the [AST2400]. This chip is an [MX25L25635F]. + +## Known issues + +- Intel SGX causes secondary APs to crash (disabled for now). +- Tianocore doesn't work with Aspeed NGI, as it's text mode only. +- After S5 resume coreboot detects more DIMMs than installed, causing FSP-M + to fail. + +## Tested and working + +- USB ports +- M.2 2280 NVMe slot +- 2x 10GB Ethernet +- SATA +- RS232 +- VGA on Aspeed +- Super I/O initialisation +- ECC DRAM detection +- PCIe slots +- TPM on TPM expansion header +- BMC (IPMI) + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Kaby Lake | ++------------------+--------------------------------------------------+ +| PCH | Intel C236 | ++------------------+--------------------------------------------------+ +| Super I/O | ASPEED AST2400 | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel SPS (server version of the ME) | ++------------------+--------------------------------------------------+ +| Coprocessor | ASPEED AST2400 | ++------------------+--------------------------------------------------+ +``` + +## Extra links + +- [Board manual] + +[AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376 +[Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1783.pdf +[flashrom]: https://flashrom.org/Flashrom +[MX25L25635F]: https://media.digikey.com/pdf/Data%20Sheets/Macronix/MX25L25635F.pdf +[N25Q128A]: https://www.micron.com/~/media/Documents/Products/Data%20Sheet/NOR%20Flash/… +[flashing tutorial]: ../../flash_tutorial/ext_power.md +[Intel FSP2.0]: ../../soc/intel/fsp/index.md +[Supermicro X11SSH-TF]: https://www.supermicro.com/en/products/motherboard/X11SSH-TF diff --git a/Documentation/mainboard/supermicro/x11ssh_flash.jpg b/Documentation/mainboard/supermicro/x11ssh_flash.jpg new file mode 100644 index 0000000..8ab07f2 --- /dev/null +++ b/Documentation/mainboard/supermicro/x11ssh_flash.jpg Binary files differ diff --git a/src/mainboard/supermicro/x11ssh/Kconfig b/src/mainboard/supermicro/x11ssh/Kconfig new file mode 100644 index 0000000..4f18a80 --- /dev/null +++ b/src/mainboard/supermicro/x11ssh/Kconfig @@ -0,0 +1,79 @@ +config BOARD_SUPERMICRO_BASEBOARD_X11SSH + def_bool n + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select SOC_INTEL_KABYLAKE + select SKYLAKE_SOC_PCH_H + select MAINBOARD_HAS_LPC_TPM + select DRIVERS_ASPEED_AST2050 + select SUPERIO_ASPEED_AST2400 + select GENERATE_SMBIOS_TABLES + select IPMI_KCS + +if BOARD_SUPERMICRO_BASEBOARD_X11SSH + +config VBOOT + select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/vboot-ro-rwab.fmd" if VBOOT_SLOTS_RW_AB + +config CBFS_SIZE + hex + default 0x009aa000 if !VBOOT + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "supermicro/x11ssh" + +config VARIANT_DIR + string + default "tf" if BOARD_SUPERMICRO_X11SSH_PLUS_TF + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config MAINBOARD_PART_NUMBER + string + default "X11SSH-TF" if BOARD_SUPERMICRO_X11SSH_PLUS_TF + +config MAX_CPUS + int + default 8 + +config SUBSYSTEM_VENDOR_ID + hex + default 0x8086 + +config CONSOLE_POST + bool + default y + +config POST_DEVICE + bool + default n + +config DIMM_SPD_SIZE + int + default 512 + +endif # BOARD_SUPERMICRO_BASEBOARD_X11SSH diff --git a/src/mainboard/supermicro/x11ssh/Kconfig.name b/src/mainboard/supermicro/x11ssh/Kconfig.name new file mode 100644 index 0000000..a9b351b --- /dev/null +++ b/src/mainboard/supermicro/x11ssh/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_SUPERMICRO_X11SSH_PLUS_TF + bool "X11SSH+-TF" + select BOARD_SUPERMICRO_BASEBOARD_X11SSH diff --git a/src/mainboard/supermicro/x11ssh/Makefile.inc b/src/mainboard/supermicro/x11ssh/Makefile.inc new file mode 100644 index 0000000..a6d789e --- /dev/null +++ b/src/mainboard/supermicro/x11ssh/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c + +ramstage-y += ramstage.c + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/supermicro/x11ssh/acpi/ec.asl b/src/mainboard/supermicro/x11ssh/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/supermicro/x11ssh/acpi/ec.asl diff --git a/src/mainboard/supermicro/x11ssh/acpi/mainboard.asl b/src/mainboard/supermicro/x11ssh/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/supermicro/x11ssh/acpi/mainboard.asl diff --git a/src/mainboard/supermicro/x11ssh/acpi/superio.asl b/src/mainboard/supermicro/x11ssh/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/supermicro/x11ssh/acpi/superio.asl diff --git a/src/mainboard/supermicro/x11ssh/acpi_tables.c b/src/mainboard/supermicro/x11ssh/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/supermicro/x11ssh/acpi_tables.c diff --git a/src/mainboard/supermicro/x11ssh/board_info.txt b/src/mainboard/supermicro/x11ssh/board_info.txt new file mode 100644 index 0000000..029d2a9 --- /dev/null +++ b/src/mainboard/supermicro/x11ssh/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Supermicro +Board name: X11SSH Baseboard +Category: server +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/supermicro/x11ssh/bootblock.c b/src/mainboard/supermicro/x11ssh/bootblock.c new file mode 100644 index 0000000..8bc8ab0 --- /dev/null +++ b/src/mainboard/supermicro/x11ssh/bootblock.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/gpio.h> +#include "gpio.h" +#include <superio/aspeed/common/aspeed.h> +#include <superio/aspeed/ast2400/ast2400.h> +#include <delay.h> +#include <console/uart.h> + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +static void early_config_superio(void) +{ + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); + if (CONFIG(CONSOLE_SERIAL)) { + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + /* The serial output is garbeled before this timeout. + * FIXME: Find out why and remove delay. + */ + mdelay(1000); + } +} + +void bootblock_mainboard_early_init(void) +{ + early_config_gpio(); + early_config_superio(); +} diff --git a/src/mainboard/supermicro/x11ssh/cmos.layout b/src/mainboard/supermicro/x11ssh/cmos.layout new file mode 100644 index 0000000..201ca33 --- /dev/null +++ b/src/mainboard/supermicro/x11ssh/cmos.layout @@ -0,0 +1,62 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name + +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level +448 128 r 0 vbnv + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/supermicro/x11ssh/dsdt.asl b/src/mainboard/supermicro/x11ssh/dsdt.asl new file mode 100644 index 0000000..ac929a6 --- /dev/null +++ b/src/mainboard/supermicro/x11ssh/dsdt.asl @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/supermicro/x11ssh/gpio.h b/src/mainboard/supermicro/x11ssh/gpio.h new file mode 100644 index 0000000..02fe90c --- /dev/null +++ b/src/mainboard/supermicro/x11ssh/gpio.h @@ -0,0 +1,248 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIOX11SSHTF_H +#define _GPIOX11SSHTF_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ +static const struct pad_config gpio_table[] = { +/* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x00000000), +/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000), +/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000), +/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000), +/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000), +/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000), +/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000), +/* PIRQA# */ _PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x00000000), +/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000), +/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000), +/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000), +/* PME# */ _PAD_CFG_STRUCT(GPP_A11, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x80080201, 0x00000000), +/* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000000), +/* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000000), +/* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x00000000), +/* CLKOUT_48 */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000000), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000000), +/* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000000), +/* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000000), +/* SPKR */ _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000000), +/* PCHHOT# */ _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000000), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C0, 0xffffffff, 0xffffff00), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C1, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000000), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C3, 0xffffffff, 0xffffff00), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C4, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000000), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), +/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C8, 0x84000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C10, 0x84000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C22, 0x42040102, 0x00003000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D2, 0x42020102, 0x00003000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D22, 0x04000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000000), +/* SATAXPCIE0 */ _PAD_CFG_STRUCT(GPP_E0, 0x44000502, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x82020102, 0x00003000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000000), +/* SATA_LED# */ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000000), +/* USB_OC0# */ _PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x00000000), +/* USB_OC1# */ _PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x00000000), +/* USB_OC2# */ _PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x00000000), +/* USB_OC3# */ _PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F5, 0x80100102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F9, 0x84000102, 0x00000000), +/* SATA_SCLOCK */ _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000000), +/* SATA_SLOAD */ _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000000), +/* SATA_SDATAOUT1 */ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000000), +/* SATA_SDATAOUT2 */ _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000000), +/* USB_OC4# */ _PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x00000000), +/* USB_OC5# */ _PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x04000200, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G3, 0x44000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G14, 0x84000102, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000000), +/* NMI# */ _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000000), +/* SMI# */ _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H1, 0x84000103, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000000), +/* SRCCLKREQ9# */ _PAD_CFG_STRUCT(GPP_H3, 0x44000602, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H4, 0x84000103, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000000), +/* SML2CLK */ _PAD_CFG_STRUCT(GPP_H10, 0x44000702, 0x00000000), +/* SML2DATA */ _PAD_CFG_STRUCT(GPP_H11, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000000), +/* SML3CLK */ _PAD_CFG_STRUCT(GPP_H13, 0x44000702, 0x00000000), +/* SML3DATA */ _PAD_CFG_STRUCT(GPP_H14, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000000), +/* SML4CLK */ _PAD_CFG_STRUCT(GPP_H16, 0x44000702, 0x00000000), +/* SML4DATA */ _PAD_CFG_STRUCT(GPP_H17, 0x44000702, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000000), +/* LAN_WAKE# */ _PAD_CFG_STRUCT(GPD2, 0x04000702, 0x00000000), +/* PWRBTN# */ _PAD_CFG_STRUCT(GPD3, 0x04000702, 0x00000000), +/* SLP_S3# */ _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000000), +/* SLP_S4# */ _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000000), +/* SLP_A# */ _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000000), +/* SUSCLK */ _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000000), +/* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000000), +/* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000000), +/* DDPD_HPD2 */ _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000000), +/* DDPE_HPD3 */ _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000000), +/* GPIO */ _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000000), +/* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000000), +/* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000000), +/* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000000), +/* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000000), +/* DDPD_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000000), +/* DDPD_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000000), +}; + + +/*** XXX TODO XXX */ +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { +/* LPC */ + +/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000), +/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000), +/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000), +/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000), +/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000), +/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000), +/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000), +/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000), +/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000), +}; + +#endif /* __ACPI__ */ +#endif /* _GPIOX11SSHTF_H */ diff --git a/src/mainboard/supermicro/x11ssh/ramstage.c b/src/mainboard/supermicro/x11ssh/ramstage.c new file mode 100644 index 0000000..2672f73 --- /dev/null +++ b/src/mainboard/supermicro/x11ssh/ramstage.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + params->CdClock = 3; + + /* This must be one, otherwise FSP crashes ... */ + params->PchHdaVcType = 0x1; +} diff --git a/src/mainboard/supermicro/x11ssh/romstage.c b/src/mainboard/supermicro/x11ssh/romstage.c new file mode 100644 index 0000000..cb1f105 --- /dev/null +++ b/src/mainboard/supermicro/x11ssh/romstage.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/api.h> +#include <soc/romstage.h> +#include <spd_bin.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + struct spd_block blk = { + .addr_map = { 0x50, 0x51, 0x52, 0x53, }, + }; + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; + mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; + mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + mem_cfg->UserBd = BOARD_TYPE_SERVER; + + mupd->FspmTestConfig.DmiVc1 = 1; +} diff --git a/src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt b/src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt new file mode 100644 index 0000000..f3eb3ef --- /dev/null +++ b/src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Supermicro +Board name: X11SSH-TF +Category: server +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb b/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb new file mode 100644 index 0000000..ce6bfa5 --- /dev/null +++ b/src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb @@ -0,0 +1,290 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x007c0a01" # Super IO SWC + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + register "gen3_dec" = "0x000c03e1" # UART3 + register "gen4_dec" = "0x000c02e1" # UART4 + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # FSP Configuration + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "SaGv" = "SaGv_Disabled" + + # Disable SGX + register "sgx_enable" = "0" # SGX is broken in coreboot + register "PrmrrSize" = "128 * MiB" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # SATA configuration + register "SataMode" = "0" # AHCI + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + + register "SataPortsDevSlp" = "{\ + [0] = 0, \ + [1] = 0, \ + [2] = 0, \ + [3] = 0, \ + [4] = 0, \ + [5] = 0, \ + [6] = 0, \ + [7] = 0, \ + }" + + # superspeed_inter-chip_supplement (SSIC) disabled + register "SsicPortEnable" = "0" + + # USB configuration + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # USB2/3 + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # USB2/3 + register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" # ? + register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" # ? + + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # USB4/5 + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # USB4/5 + + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # USB0/1 + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" # USB0/1 + + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB9/10 (USB3.0) + register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" # USB9/10 (USB3.0) + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" + + register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" # USB6/7 (USB3.0) + register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" # USB6/7 (USB3.0) + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" + + register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" # USB8 (USB3.0) + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" + + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # IPMI USB HUB + + # LPC + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # PCIe configuration + # Enable JPCIE1 + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "0" + + # Enable ASpeed PCI bridge + register "PcieRpEnable[2]" = "1" + register "PcieRpClkReqSupport[2]" = "0" + + # Enable X550T (10GbE) + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "0" + + # Enable M.2 + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "0" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # VR Settings Configuration for 4 Domains + # ICC_MAX = 0 (Auto) + # Voltage limit 1.52V (not used on KBL-S and KBL-DT) + # Disable PS4 powerstate in S0ix, thus no package C10 support + # psi threshold is using FSP default values + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, \ + .psi4enable = 0, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0, \ + .voltage_limit = 1520 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, \ + .psi4enable = 0, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0, \ + .voltage_limit = 1520 \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, \ + .psi4enable = 0, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0 ,\ + .voltage_limit = 1520 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, \ + .psi4enable = 0, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0, \ + .voltage_limit = 1520 \ + }" + + # No extra VR mailbox command + register "SendVrMbxCmd" = "0" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 01.0 on end # unused + device pci 01.1 on + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X" + end # PCIE Slot (JPCIE1) + device pci 04.0 on end # SA thermal subsystem + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 on end # Management Engine Interface 2 + device pci 17.0 on end # SATA + device pci 1c.0 on + smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X" + end # PCI Express Port 1 (Slot JPCIE1) + device pci 1c.2 on + device pci 00.0 on + device pci 00.0 on end # Aspeed 2400 VGA + end + end # PCI Express Port 3 + device pci 1c.4 on + device pci 00.0 on end # 10GbE + device pci 00.1 on end # 10GbE + end # PCI Express Port 5 + device pci 1d.0 on + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" + end # PCI Express Port 9 + device pci 1f.0 on + chip drivers/ipmi + # On cold boot it takes a while for the BMC to start the IPMI service + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + device pnp ca2.0 on end # IPMI KCS + end + chip superio/common + device pnp 2e.0 on + chip superio/aspeed/ast2400 + device pnp 2e.2 on # SUART1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # SUART2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.4 on # SWC + io 0x60 = 0xa00 + io 0x62 = 0xa10 + io 0x64 = 0xa20 + io 0x66 = 0xa30 + irq 0x70 = 0xb + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 0xc + end + device pnp 2e.7 on # GPIO + end + device pnp 2e.b on # SUART3 + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.c on # SUART4 + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.d on # iLPC2AHB + end + device pnp 2e.e on # Mailbox + io 0x60 = 0xa40 + irq 0x70 = 0x00 + end + end + end + end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # SPI Controller + end +end diff --git a/src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd b/src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd new file mode 100644 index 0000000..a295680 --- /dev/null +++ b/src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd @@ -0,0 +1,36 @@ +FLASH 16M { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x4ff000 + } + SI_BIOS@0x500000 0xb00000 { + RW_SECTION_A@0x0 0x33e000 { + VBLOCK_A@0x0 0x20000 + FW_MAIN_A(CBFS)@0x20000 0x31dfc0 + RW_FWID_A@0x33dfc0 0x40 + } + RW_SECTION_B@0x33e000 0x33e000 { + VBLOCK_B@0x0 0x20000 + FW_MAIN_B(CBFS)@0x20000 0x31dfc0 + RW_FWID_B@0x33dfc0 0x40 + } + MISC_RW@0x67d000 0x62000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x20000 0x2000 + SMMSTORE(PRESERVE)@0x22000 0x40000 + } + WP_RO@0x6df000 0x421000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x41d000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x32d000 + } + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 82 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit September 2019