coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Philipp Deppenwiese (Code Review) 01 Sep '19

01 Sep '19

1 0

Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Philipp Deppenwiese (Code Review) 01 Sep '19

01 Sep '19

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... Patch Set 81: (26 comments) https://review.coreboot.org/c/coreboot/+/32734/74/Documentation/mainboard/s… File Documentation/mainboard/supermicro/x11ssh-tf.md: https://review.coreboot.org/c/coreboot/+/32734/74/Documentation/mainboard/s… PS74, Line 30: S5 resume > We will do it in a follow-up. Done https://review.coreboot.org/c/coreboot/+/32734/74/Documentation/mainboard/s… PS74, Line 37: 10GB > Done Done https://review.coreboot.org/c/coreboot/+/32734/74/Documentation/mainboard/s… File Documentation/mainboard/supermicro/x11ssh_flash.jpg: PS74: > We will do it in a follow-up. Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/Kconfig: https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 9: select MAINBOARD_USES_FSP2_0 > Done Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 18: config SOC_INTEL_COMMON_BLOCK_SGX > Done Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 67: : config SUBSYSTEM_VENDOR_ID : hex : default 0x8086 > Yes, in `soc/intel/skylake/chip_fsp20. […] Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 76: endif > Done Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/Kconfig.name: https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 1: BOARD_SUPERMICRO_X11SSH_PLUS_TF : bool "X11SSH+-TF" > We will do it in a follow-up. Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/board_info.txt: https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 5: ROM socketed: n > They aren't. Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/bootblock.c: https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 37: garbeled > We will do it in a follow-up. Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/mainboard.c: PS74: > Done Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/ramstage.c: https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 3: * > Copyright holders will be transferred to AUTHORS file soon. Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/romstage.c: https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 3: * > Same. Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt: https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 5: ROM socketed: n > The retail ones are, so you don't have a retail board, right? Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb: https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 30: "Device4Enable" = "1" > Done Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 73: register "SsicPortEnable" = "0" > No. Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 114: X550T > Done Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 203: device domain 0 on > Maybe add a 'subsystemid 0x1234 0x5678 inherit' line right after this line ('device domain 0 on') […] We will do it in a follow-up. https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 205: unused > Looks like it's routed to the LSI SAS3008 (only on the X11SSH-CTF, unpopulated on the X11SSH-TF). Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 208: JPCIE1 > SLOT6 […] Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 216: JPCIE1 > SLOT4 Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 219: device pci 00.0 on end # Aspeed 2400 VGA > Mind elaborating a bit as to why? I am quite intrigued by it. Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 223: 10GBE > Done Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 239: device pnp 2e.0 off end > Done Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 263: device pnp 2e.b on # SUART3 > I guess one could try "listening" to that virtual UART and hope something will appear. […] Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 267: device pnp 2e.c on # SUART4 > Same. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 81 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 01 Sep 2019 22:16:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Keno Fischer <keno(a)alumni.harvard.edu> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner Comment-In-Reply-To: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Philipp Deppenwiese (Code Review) 01 Sep '19

01 Sep '19

1 0

Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Philipp Deppenwiese (Code Review) 01 Sep '19

01 Sep '19

1 0

Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Philipp Deppenwiese (Code Review) 01 Sep '19

01 Sep '19

1 0

Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Philipp Deppenwiese (Code Review) 01 Sep '19

01 Sep '19

1 0

Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Michael Niewöhner (Code Review) 01 Sep '19

01 Sep '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... Patch Set 81: (1 comment) https://review.coreboot.org/c/coreboot/+/32734/81/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb: https://review.coreboot.org/c/coreboot/+/32734/81/src/mainboard/supermicro/… PS81, Line 12: register "gpe0_dw0" = "GPP_B" is this checked against inteltool? on x11ssm this is GPP_G and I wouldn't be surprised if this would match -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 81 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 01 Sep 2019 16:08:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Michael Niewöhner (Code Review) 01 Sep '19

01 Sep '19

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... Patch Set 81: (2 comments) https://review.coreboot.org/c/coreboot/+/32734/68/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/gpio.h: https://review.coreboot.org/c/coreboot/+/32734/68/src/mainboard/supermicro/… PS68, Line 31: static const struct pad_config gpio_table[] = { > would it be reasonable easy to change this table in a way so that it doesn't just consists of a lot […] Unfortunately there is no board documentation / schematics publicly available https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt: https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 5: ROM socketed: n > They aren't. The retail ones are, so you don't have a retail board, right? -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 81 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 01 Sep 2019 10:36:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Comment-In-Reply-To: Michael Niewöhner Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboars: lenovo: add basic implementation for ts p320
by Michael Niewöhner (Code Review) 01 Sep '19

01 Sep '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34947 ) Change subject: mainboars: lenovo: add basic implementation for ts p320 ...................................................................... mainboars: lenovo: add basic implementation for ts p320 Change-Id: Ifda0144255c55f124688c133eac57d88498700d8 --- A src/mainboard/lenovo/thinkstation_p320/Kconfig A src/mainboard/lenovo/thinkstation_p320/Kconfig.name A src/mainboard/lenovo/thinkstation_p320/Makefile.inc A src/mainboard/lenovo/thinkstation_p320/acpi/ec.asl A src/mainboard/lenovo/thinkstation_p320/acpi/mainboard.asl A src/mainboard/lenovo/thinkstation_p320/acpi/superio.asl A src/mainboard/lenovo/thinkstation_p320/acpi_tables.c A src/mainboard/lenovo/thinkstation_p320/board_info.txt A src/mainboard/lenovo/thinkstation_p320/bootblock.c A src/mainboard/lenovo/thinkstation_p320/cmos.layout A src/mainboard/lenovo/thinkstation_p320/devicetree.cb A src/mainboard/lenovo/thinkstation_p320/dsdt.asl A src/mainboard/lenovo/thinkstation_p320/gpio.h A src/mainboard/lenovo/thinkstation_p320/mainboard.c A src/mainboard/lenovo/thinkstation_p320/ramstage.c A src/mainboard/lenovo/thinkstation_p320/romstage.c 16 files changed, 1,068 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/34947/1 diff --git a/src/mainboard/lenovo/thinkstation_p320/Kconfig b/src/mainboard/lenovo/thinkstation_p320/Kconfig new file mode 100644 index 0000000..13a8e35 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/Kconfig @@ -0,0 +1,50 @@ +if BOARD_LENOVO_THINKSTATION_P320 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select SOC_INTEL_KABYLAKE + select SKYLAKE_SOC_PCH_H + select MAINBOARD_USES_FSP2_0 + select MAINBOARD_HAS_LPC_TPM + select GENERATE_SMBIOS_TABLES + select SUPERIO_NUVOTON_NCT6683D + select SUPERIO_NUVOTON_NCT6683D_COM_A + + +config SOC_INTEL_COMMON_BLOCK_SGX + bool + default y + +config MAINBOARD_DIR + string + default "lenovo/thinkstation_p320" + +config MAINBOARD_PART_NUMBER + string + default "ThinkStation P320" + +config MAX_CPUS + int + default 8 + +config IRQ_SLOT_COUNT + int + default 18 + +config SUBSYSTEM_VENDOR_ID + hex + default 0x8086 + +config CONSOLE_POST + bool + default y + +config DIMM_SPD_SIZE + int + default 512 #DDR4 + +endif # BOARD_LENOVO_THINKSTATION_P320 diff --git a/src/mainboard/lenovo/thinkstation_p320/Kconfig.name b/src/mainboard/lenovo/thinkstation_p320/Kconfig.name new file mode 100644 index 0000000..df22214 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_THINKSTATION_P320 + bool "ThinkStation P320 (IQ1X0MS)" diff --git a/src/mainboard/lenovo/thinkstation_p320/Makefile.inc b/src/mainboard/lenovo/thinkstation_p320/Makefile.inc new file mode 100644 index 0000000..e9af214 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c + +ramstage-y += mainboard.c +ramstage-y += ramstage.c diff --git a/src/mainboard/lenovo/thinkstation_p320/acpi/ec.asl b/src/mainboard/lenovo/thinkstation_p320/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/acpi/ec.asl diff --git a/src/mainboard/lenovo/thinkstation_p320/acpi/mainboard.asl b/src/mainboard/lenovo/thinkstation_p320/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/acpi/mainboard.asl diff --git a/src/mainboard/lenovo/thinkstation_p320/acpi/superio.asl b/src/mainboard/lenovo/thinkstation_p320/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/acpi/superio.asl diff --git a/src/mainboard/lenovo/thinkstation_p320/acpi_tables.c b/src/mainboard/lenovo/thinkstation_p320/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/acpi_tables.c diff --git a/src/mainboard/lenovo/thinkstation_p320/board_info.txt b/src/mainboard/lenovo/thinkstation_p320/board_info.txt new file mode 100644 index 0000000..a6124eb --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Lenovo +Board name: ThinkStation P320 (IQ1X0MS1) +Category: workstation +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/lenovo/thinkstation_p320/bootblock.c b/src/mainboard/lenovo/thinkstation_p320/bootblock.c new file mode 100644 index 0000000..08c4f2c --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/bootblock.c @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <bootblock_common.h> +#include <soc/gpio.h> +#include "gpio.h" +//#include <superio/aspeed/common/aspeed.h> +//#include <superio/aspeed/ast2400/ast2400.h> +#include <device/pnp_ops.h> +#include <device/pnp.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6683d/nct6683d.h> +#include <delay.h> +#include <console/uart.h> +#include <console/console.h> +#include <halt.h> +#include <intelblocks/lpc_lib.h> +#include <soc/pch.h> +#include <soc/pci_devs.h> +#include <device/pci_ops.h> +#include <soc/bootblock.h> + +#define LPC_IO_ENABLES 0x82 + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6683D_SP1) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + + +static void print_reg(u8 dev, u8 reg) { + printk(BIOS_DEBUG, "0x%x: %x\n", reg, pnp_read_config(dev, reg)); +} + +static void early_config_superio(void) +{ + /* + * at this point any ec/sio lpc address deconding must be enabled in the + * chipset registers. relevant registers are 0x80, 0x82, 0x84 + */ + + //lpc_soc_init(SERIAL_DEV); + //enable_lpc(); + //pch_early_iorange_init(); + //uint16_t l = pci_read_config16(PCH_DEV_LPC, 0x82); + + uint16_t pcipnptmp = pci_read_config16(PCH_DEV_LPC, 0x80); + pci_write_config16(PCH_DEV_LPC, ..., pcipnptmp | ...); + + if (CONFIG(CONSOLE_SERIAL)) { + //const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT6683D_SP1); + //nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + pnp_devfn_t dev = PNP_DEV(0x2e, 0); + u8 pnptmp; + + nuvoton_pnp_enter_conf_state(dev); + + /* + * I reverse engineered the initialization phase from + * NCT6685DPeiInit (lenovo UEFI image). + * Most of this should be moved to the sio driver + * while keeping anything related to uart early init here + */ + + pnp_set_logical_device(dev); + pnptmp = pnp_read_config(dev, 0x1d); + pnp_write_config(dev, 0x1d, (pnptmp & 0xf7) | 0x08); + pnptmp = pnp_read_config(dev, 0x13); + pnp_write_config(dev, 0x13, (pnptmp & 0xf3) | 0x0c); + pnp_write_config(dev, 0x15, 0xf0); + pnp_write_config(dev, 0x1a, 0x03); + pnptmp = pnp_read_config(dev, 0x1b); + pnp_write_config(dev, 0x1b, (pnptmp & 0x0f) | 0xf0); + pnp_write_config(dev, 0x1d, 0x00); + pnp_write_config(dev, 0x14, 0x00); + pnp_write_config(dev, 0x1e, 0xf0); + pnp_write_config(dev, 0x1f, 0xf0); + pnptmp = pnp_read_config(dev, 0x22); + pnp_write_config(dev, 0x22, (pnptmp & 0x43) | 0xbc); + pnptmp = pnp_read_config(dev, 0x23); + pnp_write_config(dev, 0x23, (pnptmp & 0x20) | 0xdf); + pnptmp = pnp_read_config(dev, 0x24); + print_reg(dev, 0x1b); + print_reg(dev, 0x1d); + print_reg(dev, 0x24); + pnp_write_config(dev, 0x24, (pnptmp & 0x06) | 0x81); + pnp_write_config(dev, 0x25, 0xff); + pnp_write_config(dev, 0x26, 0x00); + pnptmp = pnp_read_config(dev, 0x27); + pnp_write_config(dev, 0x27, (pnptmp & 0xc0) | 0xbe); + pnp_write_config(dev, 0x28, 0x00); + pnp_write_config(dev, 0x29, 0xed); + pnptmp = pnp_read_config(dev, 0x2a); + pnp_write_config(dev, 0x2a, (pnptmp & 0x40) | 0x8f); + pnp_write_config(dev, 0x2b, 0x00); + pnptmp = pnp_read_config(dev, 0x27); + pnp_write_config(dev, 0x27, (pnptmp & 0x3f) | 0xc0); + pnptmp = pnp_read_config(dev, 0x1b); + pnp_write_config(dev, 0x1b, (pnptmp & 0xf7) | 0x00); + pnptmp = pnp_read_config(dev, 0x24); + pnp_write_config(dev, 0x24, (pnptmp & 0xf9) | 0x00); + pnptmp = pnp_read_config(dev, 0x2a); + pnp_write_config(dev, 0x2a, (pnptmp & 0xbf) | 0x40); + dev = PNP_DEV(0x2e, 0x05); + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x0060); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x0064); + pnp_set_irq(dev, PNP_IDX_IRQ0, 0x01); + pnp_set_irq(dev, PNP_IDX_IRQ1, 0x0c); + pnp_set_enable(dev, 0x01); + dev = PNP_DEV(0x2e, 0x03); + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x03f8); + pnp_set_enable(dev, 0x01); + dev = PNP_DEV(0x2e, 0x0b); + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x0a20); + pnp_set_enable(dev, 0x01); + dev = PNP_DEV(0x2e, 0x00); + pnptmp = pnp_read_config(dev, 0x1b); + pnp_write_config(dev, 0x1b, pnptmp | 0x08); + nuvoton_pnp_exit_conf_state(dev); + } +} + + +void bootblock_mainboard_early_init(void) +{ + early_config_gpio(); + early_config_superio(); +} diff --git a/src/mainboard/lenovo/thinkstation_p320/cmos.layout b/src/mainboard/lenovo/thinkstation_p320/cmos.layout new file mode 100644 index 0000000..201ca33 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/cmos.layout @@ -0,0 +1,62 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name + +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level +448 128 r 0 vbnv + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/lenovo/thinkstation_p320/devicetree.cb b/src/mainboard/lenovo/thinkstation_p320/devicetree.cb new file mode 100644 index 0000000..6eb2be4 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/devicetree.cb @@ -0,0 +1,360 @@ +## dt + +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + #register "gen1_dec" = "0x007c0a01" # Super IO + #register "gen2_dec" = "0x000c0ca1" # IPMI KCS + #register "gen3_dec" = "0x000c03e1" # UART3/4 + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # FSP Configuration + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "SaGv" = "SaGv_Enabled" + + # Disable SGX + register "sgx_enable" = "0" # SGX is broken in coreboot + register "PrmrrSize" = "128 * MiB" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + register "SataMode" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + + register "SataPortsDevSlp" = "{\ + [0] = 0, \ + [1] = 0, \ + [2] = 0, \ + [3] = 0, \ + [4] = 0, \ + [5] = 0, \ + [6] = 0, \ + [7] = 0, \ + }" + + # USB related + register "SsicPortEnable" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # OTG + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Touch Pad + register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" # OTG + register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" # Touch Pad + + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # OTG + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Touch Pad + + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # OTG + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" # Touch Pad + + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # OTG + register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" # Touch Pad + + register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" # OTG + register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" # Touch Pad + + register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" # Touch Pad + + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # IPMI USB HUB + + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # OTG + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" # M.2 WWAN + + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" # OTG + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" # M.2 WWAN + + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC5)" # M.2 WWAN + + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # Enable PCIE slot + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "0" + + # Enable PCIE slot + register "PcieRpEnable[2]" = "1" + register "PcieRpClkReqSupport[2]" = "0" + + # Enable PCIE slot + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "0" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x10, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0 ,\ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + ## VR Settings Configuration for 4 Domains + ##+----------------+-------+-------+-------+-------+ + ##| Domain/Setting | SA | IA | GTUS | GTS | + ##+----------------+-------+-------+-------+-------+ + ##| Psi1Threshold | 20A | 20A | 20A | 20A | + ##| Psi2Threshold | 5A | 5A | 5A | 5A | + ##| Psi3Threshold | 1A | 1A | 1A | 1A | + ##| Psi3Enable | 1 | 1 | 1 | 1 | + ##| Psi4Enable | 1 | 1 | 1 | 1 | + ##| ImonSlope | 0 | 0 | 0 | 0 | + ##| ImonOffset | 0 | 0 | 0 | 0 | + ##| IccMax | 7A | 34A | 35A | 35A | + ##| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + ##+----------------+-------+-------+-------+-------+ + #register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + # .vr_config_enable = 1, \ + # .psi1threshold = 0x50, \ + # .psi2threshold = 0x10, \ + # .psi3threshold = 0x4, \ + # .psi3enable = 1, \ + # .psi4enable = 1, \ + # .imon_slope = 0x0, \ + # .imon_offset = 0x0, \ + # .icc_max = 0x1C, \ + # .voltage_limit = 0x5F0 \ + #}" + # + #register "domain_vr_config[VR_IA_CORE]" = "{ + # .vr_config_enable = 1, \ + # .psi1threshold = 0x50, \ + # .psi2threshold = 0x14, \ + # .psi3threshold = 0x4, \ + # .psi3enable = 1, \ + # .psi4enable = 1, \ + # .imon_slope = 0x0, \ + # .imon_offset = 0x0, \ + # .icc_max = 0x88, \ + # .voltage_limit = 0x5F0 \ + #}" + # + #register "domain_vr_config[VR_GT_UNSLICED]" = "{ + # .vr_config_enable = 1, \ + # .psi1threshold = 0x50, \ + # .psi2threshold = 0x14, \ + # .psi3threshold = 0x4, \ + # .psi3enable = 1, \ + # .psi4enable = 1, \ + # .imon_slope = 0x0, \ + # .imon_offset = 0x0, \ + # .icc_max = 0x8C ,\ + # .voltage_limit = 0x5F0 \ + #}" + # + #register "domain_vr_config[VR_GT_SLICED]" = "{ + # .vr_config_enable = 1, \ + # .psi1threshold = 0x50, \ + # .psi2threshold = 0x14, \ + # .psi3threshold = 0x4, \ + # .psi3enable = 1, \ + # .psi4enable = 1, \ + # .imon_slope = 0x0, \ + # .imon_offset = 0x0, \ + # .icc_max = 0x8C, \ + # .voltage_limit = 0x5F0 \ + #}" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 01.0 on end # PCI Slot + device pci 01.1 on + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X" + end # PCIE Slot (JPCIE1) + device pci 14.0 on end # USB xHCI + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 on end # Management Engine Interface 2 + device pci 17.0 on end # SATA + device pci 1c.0 on + smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X" + end # PCI Express Port 1 (Slot JPCIE1) + device pci 1e.0 on end # UART 0 + device pci 1e.1 on end # UART 1 + device pci 1f.0 on # LPC bridge + #subsystemid 0x1849 0x1a43 + chip superio/nuvoton/nct6791d + #device pnp 2e.0 on end + device pnp 2e.1 off # Parallel + ## global + #irq 0x1c = 0x10 + #irq 0x27 = 0x10 + #irq 0x2a = 0x64 + ## parallel port + #io 0x60 = 0x0378 + #irq 0x70 = 7 + #drq 0x74 = 4 # No DMA + #irq 0xf0 = 0x3c # Printer mode + end + device pnp 2e.2 off # UART A + io 0x60 = 0x02f8 + #irq 0x70 = 4 + end + device pnp 2e.3 on # UART B, IR + io 0x60 = 0x03f8 + #irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + #device pnp 2e.107 off end # GPIO7 + #device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + #device pnp 2e.108 off end # GPIO0 + #device pnp 2e.308 off end # GPIO base + #device pnp 2e.408 off end # WDTMEM + #device pnp 2e.708 off end # GPIO1 + device pnp 2e.9 off end # GPIO2 + #device pnp 2e.109 off end # GPIO3 + #device pnp 2e.209 off end # GPIO4 + #device pnp 2e.309 off end # GPIO5 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, LED + # io 0x60 = 0x0290 + # io 0x62 = 0 + # irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + #device pnp 2e.f off end # GPIO PP/OD + #device pnp 2e.14 off end # SVID, Port 80 UART + #device pnp 2e.16 off end # DS5 + #device pnp 2e.116 off end # DS3 + #device pnp 2e.316 off end # PCHDSW + #device pnp 2e.416 off end # DSWWOPT + #device pnp 2e.516 off end # DS3OPT + #device pnp 2e.616 off end # DSDSS + #device pnp 2e.716 off end # DSPU + end # superio/nuvoton/nct6791d + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM module + end + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # SPI Controller + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/lenovo/thinkstation_p320/dsdt.asl b/src/mainboard/lenovo/thinkstation_p320/dsdt.asl new file mode 100644 index 0000000..ac929a6 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/dsdt.asl @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/lenovo/thinkstation_p320/gpio.h b/src/mainboard/lenovo/thinkstation_p320/gpio.h new file mode 100644 index 0000000..c3c3997 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/gpio.h @@ -0,0 +1,280 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIO_LNV_IQ1X0MS1_H +#define _GPIO_LNV_IQ1X0MS1_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#define IQ1X0MS1_PAD_DW0_DW1_CFG(val, config0, config1) \ + _PAD_CFG_STRUCT(val, config0, config1) + + +/* BIOS Flash Write Protect */ +//#define GPIO_PCH_WP GPP_C23 + +// ifndef __ACPI__ needed here? x11ssh has it, h110m-dvs not.... + +#ifndef __ACPI__ +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A7, 0x84000502, 0x0000001f), /* PIRQA# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A11, 0x84000502, 0x00000023), /* PME# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A12, 0x84000502, 0x00000024), /* BM_BUSY# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A16, 0x44000200, 0x00003028), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A17, 0x84000201, 0x00000029), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A18, 0x84000200, 0x0000002a), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A19, 0x44000200, 0x0000302b), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A20, 0x84000200, 0x0000002c), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A21, 0x84000100, 0x0000002d), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ + + /* GPIO Group GPP_B */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B0, 0x84000200, 0x00000030), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B1, 0x84000200, 0x00000031), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B2, 0x84000502, 0x00000032), /* VRALERT# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B3, 0x84000200, 0x00000033), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B4, 0x84000200, 0x00000034), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B6, 0x84000200, 0x00000036), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B7, 0x84000100, 0x00000037), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00000038), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B9, 0x84000500, 0x00000039), /* SRCCLKREQ4# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B10, 0x44000702, 0x0000003a), /* SRCCLKREQ5# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B11, 0x84000200, 0x0000003b), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B12, 0x44000600, 0x0000003c), /* SLP_S0# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B13, 0x44000600, 0x0000003d), /* PLTRST# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B14, 0x84060600, 0x0000103e), /* SPKR */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B15, 0x84000201, 0x0000003f), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B17, 0x84000200, 0x00000041), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B18, 0x84000500, 0x00000042), /* GSPIO_MOSI */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B19, 0x84000200, 0x00000043), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B20, 0x84060102, 0x00000044), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B21, 0x84000200, 0x00000045), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B22, 0x84000500, 0x00000046), /* GSPI1_MOSI */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B23, 0x84060500, 0x00001047), /* SML1ALERT# */ + + /* GPIO Group GPP_C */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C0, 0x44000502, 0x00000048), /* SMBCLK */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C1, 0x44000502, 0x00000049), /* SMBDATA */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C2, 0x44000502, 0x0000004a), /* SMBALERT# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C3, 0x44000502, 0x0000004b), /* SML0CLK */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C4, 0x44000502, 0x0000004c), /* SML0DATA */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C5, 0x84000500, 0x0000004d), /* SML0ALERT# */ + //IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C6, 0xffffffff, 0xffffffff), /* RESERVED */ + //IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C7, 0xffffffff, 0xffffffff), /* RESERVED */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C8, 0x84000102, 0x00000050), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C9, 0x84000200, 0x00000051), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C10, 0x84000200, 0x00000052), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C11, 0x84000102, 0x00000053), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C12, 0x84000201, 0x00000054), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C13, 0x84000201, 0x00000055), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C15, 0x84000201, 0x00000057), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C16, 0x84000200, 0x00000058), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C17, 0x84000200, 0x00000059), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C18, 0x84000200, 0x0000005a), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C19, 0x84000200, 0x0000005b), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C20, 0x84000200, 0x0000005c), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C21, 0x84000200, 0x0000005d), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C22, 0x84060200, 0x0000005e), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C23, 0x84060200, 0x0000005f), /* GPIO */ + + /* GPIO Group GPP_D */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D0, 0x84060200, 0x00000060), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D1, 0x84000201, 0x00000061), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D2, 0x84060500, 0x00000062), /* n/a */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D3, 0x84060500, 0x00000063), /* n/a */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D4, 0x04060201, 0x00000064), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D5, 0x04000200, 0x00000065), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D6, 0x04000200, 0x00000066), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D7, 0x04000200, 0x00000067), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D8, 0x04000200, 0x00000068), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D9, 0x04000200, 0x00000069), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D10, 0x04000200, 0x0000006a), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D14, 0x84000102, 0x0000006e), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D15, 0x84000102, 0x0000006f), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D16, 0x84000200, 0x00000070), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D19, 0x84000200, 0x00000073), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D20, 0x84000200, 0x00000074), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D21, 0x84000200, 0x00000075), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D22, 0x84000200, 0x00000076), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D23, 0x84000200, 0x00000077), /* GPIO */ + + /* GPIO Group GPP_E */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E0, 0x84060200, 0x00003018), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E1, 0x84060200, 0x00003019), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E2, 0x84060200, 0x0000301a), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E3, 0x84060201, 0x0000001b), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E4, 0x84060201, 0x0000001c), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E5, 0x80880102, 0x0000001d), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E6, 0x84060200, 0x0000001e), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E7, 0x84060200, 0x0000001f), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E8, 0x84000600, 0x00000020), /* SATA_LED# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E9, 0x44000502, 0x00000021), /* USB_OC0# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E10, 0x44000502, 0x00000022), /* USB_OC1# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E11, 0x44000502, 0x00000023), /* USB_OC2# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E12, 0x44000502, 0x00000024), /* USB_OC3# */ + + /* GPIO Group GPP_F */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F0, 0x84000200, 0x00000025), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F1, 0x84000600, 0x00000026), /* SATAXPCIE4 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F2, 0x84000600, 0x00000027), /* SATAXPCIE5 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F3, 0x84000200, 0x00000028), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F4, 0x84000200, 0x00000029), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F5, 0x02080500, 0x0000002a), /* SATA_DEVSLP3 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F6, 0x44000102, 0x0000002b), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F7, 0x42080200, 0x0000002c), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F8, 0x84000200, 0x0000002d), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F10, 0x80100600, 0x0000002f), /* SATA_SCLOCK */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F11, 0x84000600, 0x00000030), /* SATA_SLOAD */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F12, 0x80100600, 0x00000031), /* SATA_SDATAOUT1 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F13, 0x80100600, 0x00000032), /* SATA_SDATAOUT2 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F14, 0x40100100, 0x00000033), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F15, 0x44000502, 0x00000034), /* USB_OC4# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F16, 0x44000502, 0x00000035), /* USB_OC5# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F17, 0x44000502, 0x00000036), /* USB_OC6# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F18, 0x84000502, 0x00000037), /* USB_OC7# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F19, 0x84000200, 0x00000038), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F20, 0x84000200, 0x00000039), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F21, 0x84000200, 0x0000003a), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F22, 0x84000201, 0x0000003b), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F23, 0x84000200, 0x0000003c), /* GPIO */ + + /* GPIO Group GPP_G */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G0, 0x84000100, 0x0000003d), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G1, 0x84000100, 0x0000003e), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G2, 0x84000201, 0x0000003f), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G3, 0x84000201, 0x00000040), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G4, 0x84000200, 0x00000041), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G5, 0x84000200, 0x00000042), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G6, 0x84000200, 0x00000043), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G7, 0x84000200, 0x00000044), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G8, 0x84000200, 0x00000045), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G9, 0x84000200, 0x00000046), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G10, 0x84000200, 0x00000047), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G11, 0x84000201, 0x00000048), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G12, 0x84000100, 0x00000049), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G13, 0x84000100, 0x0000004a), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G14, 0x84000100, 0x0000004b), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G15, 0x84000102, 0x0000004c), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G16, 0x84000100, 0x0000004d), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G18, 0x80100201, 0x0000004f), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G19, 0x84800102, 0x00000050), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G23, 0x84000201, 0x00000054), /* GPIO */ + + /* GPIO Group GPP_H */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H1, 0x04000201, 0x00000056), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H4, 0x84000200, 0x00000059), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H5, 0x84000200, 0x0000005a), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H6, 0x84000200, 0x0000005b), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H7, 0x84000200, 0x0000005c), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H8, 0x84000200, 0x0000005d), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H9, 0x84000200, 0x0000005e), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H10, 0x84000201, 0x0000005f), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H11, 0x84000201, 0x00000060), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H12, 0x84000200, 0x00000061), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H13, 0x84000200, 0x00000062), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H14, 0x84000200, 0x00000063), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H15, 0x84000201, 0x00000064), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H16, 0x84000200, 0x00000065), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H17, 0x84000200, 0x00000066), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H18, 0x84000201, 0x00000067), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H19, 0x84000200, 0x00000068), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H20, 0x84000200, 0x00000069), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H21, 0x84000200, 0x0000006a), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H22, 0x84000200, 0x0000006b), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H23, 0x84000200, 0x0000006c), /* GPIO */ + + /* GPIO Group GPP_I */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I0, 0x84060500, 0x0000006d), /* DDPB_HPD0 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I1, 0x84060500, 0x0000006e), /* DDPC_HPD1 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I2, 0x84060500, 0x0000006f), /* DDPD_HPD2 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I3, 0x84060100, 0x00000070), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I5, 0x84000200, 0x00000072), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I6, 0x84000102, 0x00001073), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I7, 0x84000500, 0x00000074), /* DDPC_CTRLCLK */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I8, 0x84000500, 0x00001075), /* DDPC_CTRLDATA */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I9, 0x84000500, 0x00000076), /* DDPD_CTRLCLK */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I10, 0x84000500, 0x00001077), /* DDPD_CTRLDATA */ + + /* GPIO Group GPD */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD0, 0x84000502, 0x00000018), /* BATLOW# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD1, 0x04000602, 0x00000019), /* ACPRESENT */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD2, 0x00080502, 0x0000101a), /* LAN_WAKE# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD3, 0x04000502, 0x0000301b), /* PWRBTN# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD4, 0x04000600, 0x0000001c), /* SLP_S3# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD5, 0x04000600, 0x0000001d), /* SLP_S4# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD6, 0x04000600, 0x0000001e), /* SLP_A# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD7, 0x04000200, 0x0000001f), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD8, 0x04000600, 0x00000020), /* SUSCLK */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD9, 0x04000600, 0x00000021), /* SLP_WLAN# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD10, 0x04000600, 0x00000022), /* SLP_S5# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD11, 0x04000600, 0x00000023), /* LANPHYPC */ +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + /* GPIO Group GPP_A */ + /* LPC */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A7, 0x84000502, 0x0000001f), /* PIRQA# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + /* SUS */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ +}; +#endif /* __ACPI__ */ + +#endif /* _GPIO_LNV_IQ1X0MS1_H */ diff --git a/src/mainboard/lenovo/thinkstation_p320/mainboard.c b/src/mainboard/lenovo/thinkstation_p320/mainboard.c new file mode 100644 index 0000000..d09a373 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/mainboard.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> + +static void mainboard_enable(struct device *dev) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/thinkstation_p320/ramstage.c b/src/mainboard/lenovo/thinkstation_p320/ramstage.c new file mode 100644 index 0000000..bd86e0d --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/ramstage.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + params->CdClock = 3; + + /* This must be one, otherwise FSP crashes ... (from x11ssh)*/ + params->PchHdaVcType = 0x1; +} diff --git a/src/mainboard/lenovo/thinkstation_p320/romstage.c b/src/mainboard/lenovo/thinkstation_p320/romstage.c new file mode 100644 index 0000000..cb1f105 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/romstage.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/api.h> +#include <soc/romstage.h> +#include <spd_bin.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + struct spd_block blk = { + .addr_map = { 0x50, 0x51, 0x52, 0x53, }, + }; + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; + mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; + mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + mem_cfg->UserBd = BOARD_TYPE_SERVER; + + mupd->FspmTestConfig.DmiVc1 = 1; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifda0144255c55f124688c133eac57d88498700d8 Gerrit-Change-Number: 34947 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: soc/intel/common/timer: Make TSC frequency calculation dynamically
by Maulik V Vaghela (Code Review) 01 Sep '19

01 Sep '19

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35148 ) Change subject: soc/intel/common/timer: Make TSC frequency calculation dynamically ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Gerrit-Change-Number: 35148 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sun, 01 Sep 2019 09:42:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit September 2019