Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35125 )
Change subject: inteltool: Add Sky Lake Xeon E DMI3 Host bridge Id ......................................................................
inteltool: Add Sky Lake Xeon E DMI3 Host bridge Id
Change-Id: I4b429536fc2db16d770120487e4c383da437593a Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/memory.c M util/inteltool/pcie.c 4 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35125/1
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 6aff416..7eec062 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -128,6 +128,8 @@ "6th generation (Skylake-S family) Core Processor (Desktop)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2, "6th generation (Skylake-S family) Core Processor (Desktop)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E, + "6th generation (Skylake family) Core Processor Xeon E (Server)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U, "7th generation (Kaby Lake family) Core Processor (Mobile)" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 4e4bfc0..ec6ca4f 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -286,6 +286,7 @@ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M 0x1910 /* Skylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918 /* Skylake (Workstation) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D 0x191f /* Skylake (Desktop) */ +#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E 0x2020 /* Sky Lake E (Server) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U 0x5904 /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y 0x590C /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q 0x5914 /* Kabylake (Mobile) */ diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 222ac8a..e80f1ba 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -221,6 +221,7 @@ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 33644ab..b7c72cb 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -267,6 +267,7 @@ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: @@ -393,6 +394,7 @@ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: @@ -503,6 +505,7 @@ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q:
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35125 )
Change subject: inteltool: Add Sky Lake Xeon E DMI3 Host bridge Id ......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Has this been tested?
https://review.coreboot.org/c/coreboot/+/35125/3/util/inteltool/inteltool.h File util/inteltool/inteltool.h:
https://review.coreboot.org/c/coreboot/+/35125/3/util/inteltool/inteltool.h@... PS3, Line 289: Sky Lake Skylake
Hello Angel Pons, Stefan Reinauer, Felix Singer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35125
to look at the new patch set (#5).
Change subject: inteltool: Add Skylake Xeon E DMI3 Host bridge Id ......................................................................
inteltool: Add Skylake Xeon E DMI3 Host bridge Id
Tested on Intel S2600WF and SUPERMICRO MBD-X11DPL-I-O
Change-Id: I4b429536fc2db16d770120487e4c383da437593a Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/memory.c M util/inteltool/pcie.c 4 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/35125/5
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35125 )
Change subject: inteltool: Add Skylake Xeon E DMI3 Host bridge Id ......................................................................
Patch Set 5:
Patch Set 3: Code-Review+1
(1 comment)
Has this been tested?
Yes. You can see the inteltool gpio dump for the Supermicro MBD-X11DPL-I-O motherboard: https://github.com/maxpoliak/pch-pads-parser/blob/master/examples/inteltool-...
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35125 )
Change subject: inteltool: Add Skylake Xeon E DMI3 Host bridge Id ......................................................................
Patch Set 5: Code-Review+2
Looks good
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35125 )
Change subject: inteltool: Add Skylake Xeon E DMI3 Host bridge Id ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35125/3/util/inteltool/inteltool.h File util/inteltool/inteltool.h:
https://review.coreboot.org/c/coreboot/+/35125/3/util/inteltool/inteltool.h@... PS3, Line 289: Sky Lake
Skylake
Done
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35125 )
Change subject: inteltool: Add Skylake Xeon E DMI3 Host bridge Id ......................................................................
Patch Set 5:
Patch Set 5: Code-Review+2
Looks good
Thanks
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35125 )
Change subject: inteltool: Add Skylake Xeon E DMI3 Host bridge Id ......................................................................
inteltool: Add Skylake Xeon E DMI3 Host bridge Id
Tested on Intel S2600WF and SUPERMICRO MBD-X11DPL-I-O
Change-Id: I4b429536fc2db16d770120487e4c383da437593a Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35125 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h M util/inteltool/memory.c M util/inteltool/pcie.c 4 files changed, 7 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index cea3e0b..642b8d7 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -128,6 +128,8 @@ "6th generation (Skylake-S family) Core Processor (Desktop)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2, "6th generation (Skylake-S family) Core Processor (Desktop)" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E, + "6th generation (Skylake family) Core Processor Xeon E (Server)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U, "7th generation (Kaby Lake family) Core Processor (Mobile)" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 23b6d1d..1645f73 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -286,6 +286,7 @@ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M 0x1910 /* Skylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918 /* Skylake (Workstation) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D 0x191f /* Skylake (Desktop) */ +#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E 0x2020 /* Skylake-E (Server) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U 0x5904 /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y 0x590C /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q 0x5914 /* Kabylake (Mobile) */ diff --git a/util/inteltool/memory.c b/util/inteltool/memory.c index 222ac8a..e80f1ba 100644 --- a/util/inteltool/memory.c +++ b/util/inteltool/memory.c @@ -221,6 +221,7 @@ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index 33644ab..b7c72cb 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -267,6 +267,7 @@ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: @@ -393,6 +394,7 @@ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q: @@ -503,6 +505,7 @@ case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: + case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_E: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y: case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q:
-
Angel Pons (Code Review) -
Maxim Polyakov (Code Review)
-
Patrick Georgi (Code Review)