coreboot-gerrit August 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/skylake: enable GMM in devicetree
by Maxim Polyakov (Code Review) 02 Sep '19

02 Sep '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35168 ) Change subject: soc/intel/skylake: enable GMM in devicetree ...................................................................... soc/intel/skylake: enable GMM in devicetree Enables Gaussian Mixture Model (GMM) only if the corresponding pci device is enabled in the device tree Change-Id: I21409adf85b70bccc30dd8e12a03ad7921544b3c Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/include/soc/pci_devs.h 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/35168/1 diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 064f71e..c54de3a 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -441,6 +441,10 @@ dev->enabled = 0; params->XdciEnable = dev->enabled; + /* Enable or disable Gaussian Mixture Model in devicetree */ + dev = pcidev_path_on_root(SA_DEVFN_GMM); + params->GmmEnable = dev->enabled; + /* * Send VR specific mailbox commands: * 000b - no VR specific command sent diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 0e8bb68..e7f860d 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -42,6 +42,9 @@ #define SA_DEVFN_IGD PCI_DEVFN(SA_DEV_SLOT_IGD, 0) #define SA_DEV_IGD PCI_DEV(0, SA_DEV_SLOT_IGD, 0) +#define SA_DEV_SLOT_GMM 0x08 +#define SA_DEVFN_GMM PCI_DEVFN(SA_DEV_SLOT_GMM, 0) +#define SA_DEV_GMM PCI_DEV(0, SA_DEV_SLOT_IGD, 0) /* PCH Devices */ #define PCH_DEV_SLOT_ISH 0x13 -- To view, visit https://review.coreboot.org/c/coreboot/+/35168 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21409adf85b70bccc30dd8e12a03ad7921544b3c Gerrit-Change-Number: 35168 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/facebook/watson: Select no UART on SuperIO
by Patrick Rudolph (Code Review) 02 Sep '19

02 Sep '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35151 ) Change subject: mb/facebook/watson: Select no UART on SuperIO ...................................................................... mb/facebook/watson: Select no UART on SuperIO Select NO_UART_ON_SUPERIO as the SoC internal UART is used. The current code is working, so this is just a cosmetic fix to remove some unused options from Kconfig. Change-Id: I206557c397da74b572e669feb1e38f0c8473d0d9 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/facebook/watson/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/35151/1 diff --git a/src/mainboard/facebook/watson/Kconfig b/src/mainboard/facebook/watson/Kconfig index 6c2f954..43b4784 100644 --- a/src/mainboard/facebook/watson/Kconfig +++ b/src/mainboard/facebook/watson/Kconfig @@ -11,6 +11,7 @@ select MAINBOARD_USES_IFD_GBE_REGION select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 + select NO_UART_ON_SUPERIO config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/35151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I206557c397da74b572e669feb1e38f0c8473d0d9 Gerrit-Change-Number: 35151 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mediatek/mt8183: Remove unnecessary parentheses
by Yu-Ping Wu (Code Review) 02 Sep '19

02 Sep '19

Yu-Ping Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35142 ) Change subject: mediatek/mt8183: Remove unnecessary parentheses ...................................................................... mediatek/mt8183: Remove unnecessary parentheses Parentheses are unnecessary for conditions like '(a == b) || (c == d)'. Extra spaces are also removed. Change-Id: I0c554bf1577b40286f7a51a8fc5804bdbb7c8bd1 Signed-off-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/rtc.c 3 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/35142/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index cdba2af..cb462e9 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -63,7 +63,7 @@ (sw_impedance[dq_term][0] << 5) | (sw_impedance[dq_term][1] << 0)); clrsetbits_le32(&ch[0].ao.shu[0].drving[1], - (0x1f << 25)|(0x1f << 20) | (1 << 31), + (0x1f << 25) | (0x1f << 20) | (1 << 31), (sw_impedance[dq_term][0] << 25) | (sw_impedance[dq_term][1] << 20) | (!dq_term << 31)); clrsetbits_le32(&ch[0].ao.shu[0].drving[2], (0x1f << 5) | (0x1f << 0), diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 05f793e..e8ee818 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -1378,7 +1378,7 @@ static void dramc_set_dqdqs_dly(u8 chn, u8 rank, enum CAL_TYPE type, s32 dly) { - if ((type == RX_WIN_RD_DQC) || (type == RX_WIN_TEST_ENG)) + if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) dramc_set_rx_dly(chn, rank, dly); else dramc_set_tx_dly_factor(chn, rank, type, dly); @@ -1553,7 +1553,7 @@ dramc_dbg("[channel %d] [rank %d] type:%d, vref_enable:%d\n", chn, rank, type, vref_scan_enable); - if ((type == TX_WIN_DQ_ONLY) || (type == TX_WIN_DQ_DQM)) { + if (type == TX_WIN_DQ_ONLY || type == TX_WIN_DQ_DQM) { for (size_t i = 0; i < 2; i++) { write32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[0], 0); clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[1], @@ -1592,7 +1592,7 @@ if (vref_scan_enable) dramc_set_vref(chn, rank, type, vref_dly.vref); - if ((type == RX_WIN_RD_DQC) || (type == RX_WIN_TEST_ENG)) { + if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) { dramc_set_rx_dly_factor(chn, rank, RX_DQM, FIRST_DQ_DELAY); dramc_set_rx_dly_factor(chn, rank, @@ -1666,7 +1666,7 @@ if (vref_scan_enable) dramc_set_vref(chn, rank, type, vref_dly.vref); - if ((type == RX_WIN_RD_DQC) || (type == RX_WIN_TEST_ENG)) + if (type == RX_WIN_RD_DQC || type == RX_WIN_TEST_ENG) dramc_set_rx_best_dly(chn, rank, vref_dly.perbit_dly); else dramc_set_tx_best_dly(chn, rank, vref_dly.perbit_dly, diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index af30d1f..f8d81f8 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -177,7 +177,7 @@ /* select 26M as target clock */ val = rtc_get_frequency_meter(middle, PMIC_FQMTR_CON0_FQM26M_CK, 0); - if ((val >= RTC_FQMTR_LOW_BASE) && (val <= RTC_FQMTR_HIGH_BASE)) + if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE) break; if (val > RTC_FQMTR_HIGH_BASE) right = middle; @@ -185,7 +185,7 @@ left = middle; } - if ((val >= RTC_FQMTR_LOW_BASE) && (val <= RTC_FQMTR_HIGH_BASE)) + if (val >= RTC_FQMTR_LOW_BASE && val <= RTC_FQMTR_HIGH_BASE) return middle; val = rtc_get_frequency_meter(left, PMIC_FQMTR_CON0_FQM26M_CK, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/35142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c554bf1577b40286f7a51a8fc5804bdbb7c8bd1 Gerrit-Change-Number: 35142 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/drallion: add memory sku id
by EricR Lai (Code Review) 02 Sep '19

02 Sep '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35133 ) Change subject: mb/google/drallion: add memory sku id ...................................................................... mb/google/drallion: add memory sku id Drallion will use soldered down memory and use GPP_F12 to GPP_F16 indicates mem_id. BUG=b:139397313 BRANCH=N/A TEST=N/A Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ib5ada54fd2b8f358b59de8089e5405cf3e34825a --- M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h A src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/35133/1 diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc index 0400d33..8e070d2 100644 --- a/src/mainboard/google/drallion/variants/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -20,3 +20,5 @@ ramstage-y += gpio.c romstage-y += gpio.c verstage-y += gpio.c + +romstage-y += memory.c diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h index f7e0403..20cfbb8 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/gpio.h @@ -25,6 +25,13 @@ /* Recovery mode */ #define GPIO_REC_MODE GPP_E8 +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F12 +#define GPIO_MEM_CONFIG_1 GPP_F13 +#define GPIO_MEM_CONFIG_2 GPP_F14 +#define GPIO_MEM_CONFIG_3 GPP_F15 +#define GPIO_MEM_CONFIG_4 GPP_F16 + const struct pad_config *variant_gpio_table(size_t *num); const struct pad_config *variant_early_gpio_table(size_t *num); diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h index d878623..ca54580 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h @@ -22,4 +22,7 @@ #define VARIANT_SKU_ID_SIGNED_EC 4 #define VARIANT_SKU_NAME_SIGNED_EC "sku4" +/* Return memory SKU for the variant */ +int variant_memory_sku(void); + #endif diff --git a/src/mainboard/google/drallion/variants/drallion/memory.c b/src/mainboard/google/drallion/variants/drallion/memory.c new file mode 100644 index 0000000..2a1d8d9 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/memory.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <variant/variant.h> +#include <gpio.h> +#include <variant/gpio.h> + +int variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + GPIO_MEM_CONFIG_4, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5ada54fd2b8f358b59de8089e5405cf3e34825a Gerrit-Change-Number: 35133 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Enable HDA for drallion platform
by Selma Bensaid (Code Review) 02 Sep '19

02 Sep '19

Hello Aamir Bohra, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/35079 to review the following change. Change subject: Enable HDA for drallion platform ...................................................................... Enable HDA for drallion platform Enable PchHdaDspEnable, PchHdaIDispCodecDisconnect and PchHdaAudioLinkHda for drallion variants. This is needed with FSP 1263. Signed-off-by: Selma BENSAID <selma.bensaid(a)intel.com> Change-Id: I13d3dd832c6fbdc2aad5ba578695edb8470806e8 --- M src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb 3 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/35079/1 diff --git a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb index fe3b6c9..8470a2c 100644 --- a/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb @@ -50,6 +50,12 @@ # Enable DDC for DDI port B register "DdiPortBDdc" = "1" + # HDA a + register "PchHdaDspEnable" = "1" + # Disable iDisplay codec enumeration + register "PchHdaIDispCodecDisconnect" = "1" + register "PchHdaAudioLinkHda" = "1" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 575b610..8e54625 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -50,6 +50,12 @@ # Enable DDC for DDI port B register "DdiPortBDdc" = "1" + # HDA a + register "PchHdaDspEnable" = "1" + # Disable iDisplay codec enumeration + register "PchHdaIDispCodecDisconnect" = "1" + register "PchHdaAudioLinkHda" = "1" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | diff --git a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb index d3aab62..530d6f4 100644 --- a/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb +++ b/src/mainboard/google/drallion/variants/sarien_cml/devicetree.cb @@ -56,6 +56,12 @@ register "LanWakeFromDeepSx" = "0" register "WolEnableOverride" = "0" + # HDA a + register "PchHdaDspEnable" = "1" + # Disable iDisplay codec enumeration + register "PchHdaIDispCodecDisconnect" = "1" + register "PchHdaAudioLinkHda" = "1" + # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | -- To view, visit https://review.coreboot.org/c/coreboot/+/35079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13d3dd832c6fbdc2aad5ba578695edb8470806e8 Gerrit-Change-Number: 35079 Gerrit-PatchSet: 1 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/ppc64: move misc.c to qemu-power8 as timer.c
by Marty E. Plummer (Code Review) 02 Sep '19

02 Sep '19

Marty E. Plummer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35082 ) Change subject: arch/ppc64: move misc.c to qemu-power8 as timer.c ...................................................................... arch/ppc64: move misc.c to qemu-power8 as timer.c Its entirely no-op and is getting in the way of real hardware timers for power9/talos ii. Change-Id: I2d21d4ac3d1a7d3f099ed6ec4faf10079b1ee1d1 Signed-off-by: Marty E. Plummer <hanetzer(a)startmail.com> --- M src/arch/ppc64/Makefile.inc M src/mainboard/emulation/qemu-power8/Makefile.inc R src/mainboard/emulation/qemu-power8/timer.c 3 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/35082/1 diff --git a/src/arch/ppc64/Makefile.inc b/src/arch/ppc64/Makefile.inc index 03b455a..bb9c63dd 100644 --- a/src/arch/ppc64/Makefile.inc +++ b/src/arch/ppc64/Makefile.inc @@ -85,7 +85,6 @@ ramstage-y += rom_media.c ramstage-y += stages.c -ramstage-y += misc.c ramstage-y += boot.c ramstage-y += tables.c ramstage-y += \ diff --git a/src/mainboard/emulation/qemu-power8/Makefile.inc b/src/mainboard/emulation/qemu-power8/Makefile.inc index db005bb..5c6c56e 100644 --- a/src/mainboard/emulation/qemu-power8/Makefile.inc +++ b/src/mainboard/emulation/qemu-power8/Makefile.inc @@ -17,6 +17,7 @@ romstage-y += cbmem.c ramstage-y += cbmem.c romstage-y += romstage.c +ramstage-y += timer.c romstage-y += uart.c ramstage-y += uart.c diff --git a/src/arch/ppc64/misc.c b/src/mainboard/emulation/qemu-power8/timer.c similarity index 100% rename from src/arch/ppc64/misc.c rename to src/mainboard/emulation/qemu-power8/timer.c -- To view, visit https://review.coreboot.org/c/coreboot/+/35082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d21d4ac3d1a7d3f099ed6ec4faf10079b1ee1d1 Gerrit-Change-Number: 35082 Gerrit-PatchSet: 1 Gerrit-Owner: Marty E. Plummer <hanetzer(a)startmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/var/helios: Increase touchscreen reset delay to 120ms
by Philip Chen (Code Review) 02 Sep '19

02 Sep '19

Philip Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35158 ) Change subject: mb/google/hatch/var/helios: Increase touchscreen reset delay to 120ms ...................................................................... mb/google/hatch/var/helios: Increase touchscreen reset delay to 120ms As per GT7375P programming guide rev0.4, we want to enforece a delay of 120ms after the reset is completed before HID_I2C starts. BUG=b:140276418 Signed-off-by: Philip Chen <philipchen(a)google.com> Change-Id: Id69a9db996bcd9001ef850c50898fbd55327b4df --- M src/mainboard/google/hatch/variants/helios/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/35158/1 diff --git a/src/mainboard/google/hatch/variants/helios/overridetree.cb b/src/mainboard/google/hatch/variants/helios/overridetree.cb index f97f120..71e4856 100644 --- a/src/mainboard/google/hatch/variants/helios/overridetree.cb +++ b/src/mainboard/google/hatch/variants/helios/overridetree.cb @@ -100,7 +100,7 @@ register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "10" + register "generic.reset_delay_ms" = "120" register "generic.reset_off_delay_ms" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" -- To view, visit https://review.coreboot.org/c/coreboot/+/35158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id69a9db996bcd9001ef850c50898fbd55327b4df Gerrit-Change-Number: 35158 Gerrit-PatchSet: 1 Gerrit-Owner: Philip Chen <philipchen(a)google.com> Gerrit-MessageType: newchange

5 8

Change in em100[master]: firmware.c: Check pointer returned by malloc
by Patrick Georgi (Code Review) 02 Sep '19

02 Sep '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/35066 ) Change subject: firmware.c: Check pointer returned by malloc ...................................................................... firmware.c: Check pointer returned by malloc Change-Id: Iecf92a9acc54a4ab0a94867e5db265e1db943d53 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Found-by: Coverity Scan #220610 --- M firmware.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/66/35066/1 diff --git a/firmware.c b/firmware.c index b3abafe..d15eb69 100644 --- a/firmware.c +++ b/firmware.c @@ -191,6 +191,10 @@ fseek(f, 0, SEEK_SET); fw = malloc(fsize); + if (!fw) { + printf("ERROR: out of memory.\n"); + return 0; + } if (fread(fw, fsize, 1, f) != 1) { perror(filename); fclose(f); -- To view, visit https://review.coreboot.org/c/em100/+/35066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Iecf92a9acc54a4ab0a94867e5db265e1db943d53 Gerrit-Change-Number: 35066 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: payloads/external/LinuxBoot: Add curl flag
by Marcello Sylvester Bauer (Code Review) 02 Sep '19

02 Sep '19

Marcello Sylvester Bauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35169 ) Change subject: payloads/external/LinuxBoot: Add curl flag ...................................................................... payloads/external/LinuxBoot: Add curl flag add --show-error curl flag to see the error message, even on silent mode. Signed-off-by: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Change-Id: I4ad40718caab60413ffe9c1503a9870cb875dd43 --- M payloads/external/LinuxBoot/targets/linux.mk 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/35169/1 diff --git a/payloads/external/LinuxBoot/targets/linux.mk b/payloads/external/LinuxBoot/targets/linux.mk index e32ad1e..b7b3a0d 100644 --- a/payloads/external/LinuxBoot/targets/linux.mk +++ b/payloads/external/LinuxBoot/targets/linux.mk @@ -33,7 +33,7 @@ ifeq ($(CONFIG_LINUXBOOT_KERNEL_CUSTOM),y) kernel_version:=$(CONFIG_LINUXBOOT_KERNEL_CUSTOM_VERSION) else - kernel_version:=$(shell curl -s -k https://www.kernel.org/feeds/kdist.xml | \ + kernel_version:=$(shell curl -sS -k https://www.kernel.org/feeds/kdist.xml | \ sed -n -e 's@.*<guid isPermaLink="false">$.*$</guid>.*@\1@p' | \ awk -F ',' '/$(TAG-y)/{ print $$3 }' | \ head -n 1) @@ -67,7 +67,7 @@ if [[ ! -f $(tarball_dir)/$(kernel_tarball).xz && ! -f $(tarball_dir)/$(kernel_tarball).xz ]]; then \ echo " WWW $(kernel_tarball).xz"; \ cd $(tarball_dir); \ - curl -OLs "$(kernel_mirror_path)/$(kernel_tarball).xz"; \ + curl -OLSs "$(kernel_mirror_path)/$(kernel_tarball).xz"; \ cd $(pwd); \ fi endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ad40718caab60413ffe9c1503a9870cb875dd43 Gerrit-Change-Number: 35169 Gerrit-PatchSet: 1 Gerrit-Owner: Marcello Sylvester Bauer <sylvblck(a)sylv.io> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/ocp/monolake: use RW_VPD to configure FSP UPD
by Name of user not set (Code Review) 02 Sep '19

02 Sep '19

jonzhang(a)fb.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34636 ) Change subject: mb/ocp/monolake: use RW_VPD to configure FSP UPD ...................................................................... mb/ocp/monolake: use RW_VPD to configure FSP UPD Summary: This patch adds: * A framework to use VPD binary blob 2.0 data to configure FSP UPD. * A library to configure HyperThreading FSP UPD variable. The framework is added in romstage to customize FSP UPD settings. If RW_VPD and binary blob are not found, or if there is no "HyperThreading" setting in the binary blob, original configuration is used. Test Plan: * Build an OCP MonoLake coreboot image, run following command to initialize RW_VPD and insert HyperThreading key: vpd -f build/coreboot.rom -O -i RW_VPD -s 'HyperThreading=0' * Flash the image to MonoLake, boot and observe following message in boot log: Detected 16 CPU threads If RW_VPD partition does not exist, or if HyperThreading key/value pair does not exist, the boot log has: Detected 32 CPU threads Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Id66c3a7a0992037f59685c0c9250f90aefc3f105 Change-Id: I799d27734fe4b67cd1f40cae710151a01562b1b2 --- M src/mainboard/ocp/monolake/Makefile.inc M src/mainboard/ocp/monolake/romstage.c A src/mainboard/ocp/monolake/vpd_fsp.c A src/mainboard/ocp/monolake/vpd_fsp.h 4 files changed, 125 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/34636/1 diff --git a/src/mainboard/ocp/monolake/Makefile.inc b/src/mainboard/ocp/monolake/Makefile.inc index 1606476..ce674e4 100644 --- a/src/mainboard/ocp/monolake/Makefile.inc +++ b/src/mainboard/ocp/monolake/Makefile.inc @@ -13,4 +13,5 @@ ## GNU General Public License for more details. ## +romstage-y += vpd_fsp.c ramstage-y += irqroute.c diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c index f3ec7e3..4add5f1 100644 --- a/src/mainboard/ocp/monolake/romstage.c +++ b/src/mainboard/ocp/monolake/romstage.c @@ -23,6 +23,9 @@ #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/lpc.h> +#include <fmap.h> + +#include "vpd_fsp.h" /** * /brief mainboard call for setup that needs to be done before fsp init @@ -57,9 +60,61 @@ 0x0c0ca1); } +/* + * This function uses a key/value pair to configure UPD. + */ +static int board_configure_upd( + const uint8_t *key, int32_t key_len, + const uint8_t *value, int32_t value_len, + void *UpdData) +{ + set_upd_hyper_threading(key, key_len, value, value_len, UpdData); + + return VPD_OK; +} + /** - * /brief customize fsp parameters here if needed + * /brief customize fsp parameters, use data stored in VPD binary blob + * to configure FSP UPD variables. */ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) { + struct region_device rdev; + void *rw_vpd_addr = NULL; + size_t rw_vpd_size = -1; + int32_t consumed; + UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; + + /* + * If RW_VPD VPD partition exists, search key/value pairs + * to see if there are relevant FSP UPD variable setting(s). + * If so, use such setting(s) to customize FSP behavior. + */ + if (CONFIG(VPD)) { + if (!fmap_locate_area_as_rdev("RW_VPD", &rdev)) { + rdev_chain(&rdev, &rdev, GOOGLE_VPD_2_0_OFFSET, + region_device_sz(&rdev) - GOOGLE_VPD_2_0_OFFSET); + rw_vpd_addr = rdev_mmap_full(&rdev); + if (rw_vpd_addr != NULL) { + rw_vpd_size = region_device_sz(&rdev); + /* Skip the VPD info header */ + rw_vpd_addr += sizeof(struct google_vpd_info); + rw_vpd_size -= sizeof(struct google_vpd_info); + /* + * decodeVpdString() is called iteratively to process + * key/value pairs in RW_VPD iteratively. In such + * processing, callback function board_configure_upd() + * is called to process a pair and update FSP UPD + * variable. + */ + for (consumed = 0; consumed < rw_vpd_size; ) { + if (decodeVpdString(rw_vpd_size, rw_vpd_addr, &consumed, + board_configure_upd, (void *)UpdData) == VPD_FAIL) + break; + } + printk(FSP_INFO_LEVEL, + "Found and Processed VPD binary blob in RW_VPD.\n"); + } + } + }; } diff --git a/src/mainboard/ocp/monolake/vpd_fsp.c b/src/mainboard/ocp/monolake/vpd_fsp.c new file mode 100644 index 0000000..ee5c9ca --- /dev/null +++ b/src/mainboard/ocp/monolake/vpd_fsp.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 The coreboot Authors. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * This file is part of the coreboot project. + */ +#include <string.h> +#include <drivers/vpd/vpd_fsp.h> +#include "vpd_fsp.h" + +/* + * For "HyperThreading" UPD variable, given a key/value + * pair, use the value to set the variable if there is match. + */ +void set_upd_hyper_threading(const uint8_t *key, + const int32_t key_len, const uint8_t *value, const int32_t value_len, + UPD_DATA_REGION *UpdData) +{ + uint8_t val; + if (set_upd_bool(FSP_VAR_HYPERTHREADING, key, key_len, value, + value_len, &val) == true) { + UpdData->HyperThreading = val; + } +} diff --git a/src/mainboard/ocp/monolake/vpd_fsp.h b/src/mainboard/ocp/monolake/vpd_fsp.h new file mode 100644 index 0000000..1e0965a --- /dev/null +++ b/src/mainboard/ocp/monolake/vpd_fsp.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 The coreboot Authors. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MB_OCP_MONOLAKE_VPD_FSP__ +#define __MB_OCP_MONOLAKE_VPD_FSP__ + +#include <drivers/vpd/lib_vpd.h> +#include <drivers/vpd/vpd_fsp.h> +#include <drivers/vpd/vpd_tables.h> +#include <inttypes.h> +#include <fsp.h> + +/* Define the strings for UPD variables that could be customized */ +#define FSP_VAR_HYPERTHREADING "HyperThreading" + +/* + * For "HyperThreading" UPD variable, given a key/value + * pair, use the value to set the variable if there is match. + */ +void set_upd_hyper_threading(const uint8_t *key, + const int32_t key_len, const uint8_t *value, const int32_t value_len, + UPD_DATA_REGION *UpdData); +#endif /* __MB_OCP_MONOLAKE_VPD_FSP__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I799d27734fe4b67cd1f40cae710151a01562b1b2 Gerrit-Change-Number: 34636 Gerrit-PatchSet: 1 Gerrit-Owner: jonzhang(a)fb.com Gerrit-MessageType: newchange

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coreboot-gerrit August 2019