coreboot-gerrit August 2019

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Change in coreboot[master]: drivers/vpd: Set bool type variable matching with key/value pair
by Name of user not set (Code Review) 02 Sep '19

02 Sep '19

jonzhang(a)fb.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34634 ) Change subject: drivers/vpd: Set bool type variable matching with key/value pair ...................................................................... drivers/vpd: Set bool type variable matching with key/value pair Summary: Give a key/value pair in VPD binary blob, and name of a bool type variable, set the variable value if there is a match. Several checks are in place: * The key/value length needs to be correct. * The key name needs to match. * THe value is either '1' or '0'. Test Plan: * Build an OCP MonoLake coreboot image, flash and run. Reviewers: dhendrix, hpe, anpetrov Subscribers: Tasks: Tags: Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Iebdba59419a555147fc40391cf17cc6879d9e1b2 --- M src/drivers/vpd/Makefile.inc A src/drivers/vpd/vpd_fsp.c A src/drivers/vpd/vpd_fsp.h 3 files changed, 77 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/34634/1 diff --git a/src/drivers/vpd/Makefile.inc b/src/drivers/vpd/Makefile.inc index 17019b5..368024b 100644 --- a/src/drivers/vpd/Makefile.inc +++ b/src/drivers/vpd/Makefile.inc @@ -1,2 +1,2 @@ -romstage-$(CONFIG_VPD) += vpd_decode.c +romstage-$(CONFIG_VPD) += vpd_decode.c vpd_fsp.c ramstage-$(CONFIG_VPD) += vpd.c vpd_decode.c diff --git a/src/drivers/vpd/vpd_fsp.c b/src/drivers/vpd/vpd_fsp.c new file mode 100644 index 0000000..adff8e9 --- /dev/null +++ b/src/drivers/vpd/vpd_fsp.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 The coreboot Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + */ +#include <string.h> +#include "vpd_fsp.h" + +/* + * Process UPD variable of boolean type. + * Match the variable name with key name in the key/value pair, + * use the value to set *val. + * During the process, necessary checking is done, such as making + * sure the value length is 1, and value is either '1' or '0'. + */ +bool set_upd_bool(const char *upd_var, + const uint8_t *key, const int32_t key_len, + const uint8_t *value, const int32_t value_len, + uint8_t *val) +{ + int i; + /* Check key length and value length */ + if (key_len != strlen(upd_var) || value_len != 1) + return false; + + /* Matching key with variable name */ + for (i = 0; i < key_len; i++) { + if (key[i] != upd_var[i]) + return false; + } + + /* Make sure the value is either '1' or '0' */ + if (*value == '1') { + *val = 1; + return true; + } else if (*value == '0') { + *val = 0; + return true; + } else + return false; +} diff --git a/src/drivers/vpd/vpd_fsp.h b/src/drivers/vpd/vpd_fsp.h new file mode 100644 index 0000000..c59f249 --- /dev/null +++ b/src/drivers/vpd/vpd_fsp.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 The coreboot Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + */ + +#ifndef __VPD_FSP__ +#define __VPD_FSP__ + +#include <inttypes.h> + +#define GOOGLE_VPD_2_0_OFFSET 0x600 + +/* + * Process UPD variable of boolean type. + * + * Match the variable name with key name in the key/value pair, + * use the value to set *val. + * During the process, necessary checking is done, such as making + * sure the value length is 1, and value is either '1' or '0'. + * + * If there is a match and checking is successful, set *val + * accordingly, and return true; otherwise return false. + */ +bool set_upd_bool(const char *upd_var, + const uint8_t *key, const int32_t key_len, + const uint8_t *value, const int32_t value_len, + uint8_t *val); +#endif /* __VPD_FSP__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebdba59419a555147fc40391cf17cc6879d9e1b2 Gerrit-Change-Number: 34634 Gerrit-PatchSet: 1 Gerrit-Owner: jonzhang(a)fb.com Gerrit-MessageType: newchange

6 55

Change in coreboot[master]: vboot: remove fastboot support
by Joel Kitching (Code Review) 02 Sep '19

02 Sep '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35002 ) Change subject: vboot: remove fastboot support ...................................................................... vboot: remove fastboot support BUG=b:124141368, chromium:995172 TEST=make clean && make test-abuild BRANCH=none Change-Id: I06ea816ffb910163ec2c3c456b3c09408c806d0b Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/ec/google/chromeec/switches.c M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc 3 files changed, 3 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35002/1 diff --git a/src/ec/google/chromeec/switches.c b/src/ec/google/chromeec/switches.c index 7b3f4d4..3fd3808 100644 --- a/src/ec/google/chromeec/switches.c +++ b/src/ec/google/chromeec/switches.c @@ -34,10 +34,9 @@ (google_chromeec_get_switches() & EC_SWITCH_DEDICATED_RECOVERY)) return 1; - /* Check if the EC has posted the keyboard recovery/fastboot event. */ + /* Check if the EC has posted the keyboard recovery event. */ return !!(google_chromeec_get_events_b() & - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) | - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT))); + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } int get_recovery_mode_retrain_switch(void) @@ -68,6 +67,5 @@ /* Clear all host event bits requesting recovery mode. */ return google_chromeec_clear_events_b( EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY) | - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT) | - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_FASTBOOT)); + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT)); } diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index c5146c6..1e372d8 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -286,10 +286,6 @@ bool "Disable shutdown on closed lid" default n -config GBB_FLAG_FORCE_DEV_BOOT_FASTBOOT_FULL_CAP - bool "Allow fastboot even if dev_boot_fastboot_full_cap=0" - default n - config GBB_FLAG_FORCE_MANUAL_RECOVERY bool "Always assume manual recovery in recovery mode" default n diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index d554f10..3078e30 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -220,7 +220,6 @@ $(call bool-to-mask,$(CONFIG_GBB_FLAG_DEFAULT_DEV_BOOT_LEGACY),0x400) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC),0x800) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_DISABLE_LID_SHUTDOWN),0x1000) \ - $(call bool-to-mask,$(CONFIG_GBB_FLAG_FORCE_DEV_BOOT_FASTBOOT_FULL_CAP),0x2000) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_FORCE_MANUAL_RECOVERY),0x4000) \ $(call bool-to-mask,$(CONFIG_GBB_FLAG_DISABLE_FWMP),0x8000) \ ) -- To view, visit https://review.coreboot.org/c/coreboot/+/35002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I06ea816ffb910163ec2c3c456b3c09408c806d0b Gerrit-Change-Number: 35002 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

3 7

Change in ...coreboot[master]: mb/*: Use common IPMI KCS driver
by Patrick Rudolph (Code Review) 02 Sep '19

02 Sep '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33490 Change subject: mb/*: Use common IPMI KCS driver ...................................................................... mb/*: Use common IPMI KCS driver Remove duplicated code and instead use the IPMI KCS driver, which provides the same functionality. Change-Id: I419713c9bef02084cca1ff4cf11c33c2e3e8d3c1 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/asus/kgpe-d16/Kconfig M src/mainboard/asus/kgpe-d16/devicetree.cb M src/mainboard/asus/kgpe-d16/dsdt.asl M src/mainboard/asus/kgpe-d16/mainboard.c M src/mainboard/ocp/monolake/Kconfig M src/mainboard/ocp/monolake/devicetree.cb M src/mainboard/ocp/monolake/dsdt.asl M src/mainboard/ocp/monolake/mainboard.c 8 files changed, 7 insertions(+), 171 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/33490/1 diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index 32c4dbc..64beaf0 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -33,6 +33,7 @@ select DRIVERS_ASPEED_AST2050 select MAINBOARD_FORCE_NATIVE_VGA_INIT select POWER_STATE_DEFAULT_ON_AFTER_FAILURE + select IPMI_KCS config MAINBOARD_DIR string diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb index 0ea4216..31bd3e3 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb @@ -217,7 +217,7 @@ chip drivers/pc80/tpm device pnp 4e.0 on end # TPM module end - chip drivers/generic/generic # BMC KCS + chip drivers/ipmi # BMC KCS device pnp ca2.0 on end end end diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl index ea52488..efb67a5 100644 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -53,9 +53,6 @@ #include <southbridge/amd/common/acpi/sleepstates.asl> - /* IPMI KCS enable */ - Name (KCSE, 0x1) - /* The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. * @@ -489,13 +486,6 @@ Name (_HID, EisaId ("PNP0A05")) Name (_ADR, 0x00140003) - OperationRegion (BMRG, SystemIO, 0xca2, 0x02) /* BMC KCS registers */ - Field (BMRG, AnyAcc, NoLock, Preserve) - { - BMRI, 8, /* Index */ - BMRD, 8, /* Data */ - } - /* Real Time Clock Device */ Device(RTC0) { Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ @@ -617,27 +607,6 @@ }) } } - - Device (KCS1) { /* IPMI KCS */ - Name (_HID, EISAID ("IPI0001")) /* ASpeed BMC */ - Method (_STA, 0, NotSerialized) { - If (KCSE) { /* Detection enabled */ - If (LNotEqual (BMRD, 0xff)) { - Return (0x0f) /* Device present */ - } - Return (Zero) - } - Return (Zero) - } - Method (_CRS, 0) { - Return (ResourceTemplate() { - IO(Decode16, 0x0ca2, 0x0ca2, 0x01, 0x02) - }) - } - Method (_IFT, 0, NotSerialized) { /* Interface type */ - Return (One) /* KCS interface */ - } - } } /* High Precision Event Timer */ diff --git a/src/mainboard/asus/kgpe-d16/mainboard.c b/src/mainboard/asus/kgpe-d16/mainboard.c index 14bb986..a03953b 100644 --- a/src/mainboard/asus/kgpe-d16/mainboard.c +++ b/src/mainboard/asus/kgpe-d16/mainboard.c @@ -47,7 +47,6 @@ * enable the dedicated function in kgpe-d16 board. * This function is called earlier than sr5650_enable. *************************************************/ -#define BMC_KCS_BASE 0xca2 static void mainboard_enable(struct device *dev) { @@ -69,13 +68,6 @@ set_pcie_dereset(); /* get_ide_dma66(); */ - - /* Enable access to the BMC IPMI via KCS */ - struct device *lpc_sio_dev = dev_find_slot_pnp(BMC_KCS_BASE, 0); - struct resource *res = new_resource(lpc_sio_dev, BMC_KCS_BASE); - res->base = BMC_KCS_BASE; - res->size = 1; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } /* override the default SATA PHY setup */ diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig index 037c322..7af4ae9 100644 --- a/src/mainboard/ocp/monolake/Kconfig +++ b/src/mainboard/ocp/monolake/Kconfig @@ -13,6 +13,7 @@ select MAINBOARD_USES_IFD_GBE_REGION select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 + select IPMI_KCS config INTEGRATED_UART def_bool n diff --git a/src/mainboard/ocp/monolake/devicetree.cb b/src/mainboard/ocp/monolake/devicetree.cb index 2d91b73..5b990db 100644 --- a/src/mainboard/ocp/monolake/devicetree.cb +++ b/src/mainboard/ocp/monolake/devicetree.cb @@ -11,8 +11,10 @@ chip drivers/pc80/tpm device pnp 0c31.0 on end end - chip drivers/generic/generic # BMC KCS - device pnp ca2.0 on end + chip drivers/ipmi # BMC KCS + device pnp ca2.0 on + register "bmc_i2c_address" = "0x20" + end end end # LPC Bridge device pci 1f.2 on end # SATA Controller diff --git a/src/mainboard/ocp/monolake/dsdt.asl b/src/mainboard/ocp/monolake/dsdt.asl index 72b1c3c..1248703 100644 --- a/src/mainboard/ocp/monolake/dsdt.asl +++ b/src/mainboard/ocp/monolake/dsdt.asl @@ -27,9 +27,6 @@ { #include "acpi/platform.asl" - Name (IDTP, 0x0CA2) - Name (ICDP, 0x0CA6) - Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) @@ -293,97 +290,5 @@ } } - Scope (_SB.PCI0.LPC0) - { - Device (SPMI) - { - Name (_HID, EisaId ("IPI0001")) - Name (_STR, Unicode ("IPMI_KCS")) - Name (_UID, 0x00) - OperationRegion (IPST, SystemIO, ICDP, 0x01) - Field (IPST, ByteAcc, NoLock, Preserve) - { - STAS, 8 - } - Method (_STA, 0, NotSerialized) { - Return (0x0f) - } - Name (ICRS, ResourceTemplate () - { - IO (Decode16, - 0x0000, - 0x0000, - 0x00, - 0x00, - _Y01) - IO (Decode16, - 0x0000, - 0x0000, - 0x00, - 0x00, - _Y02) - - }) - Method (_CRS, 0, NotSerialized) - { - CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MIN, IPDB) - CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._MAX, IPDH) - CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y01._LEN, IPDL) - CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MIN, IPCB) - CreateWordField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._MAX, IPCH) - CreateByteField (ICRS, \_SB.PCI0.LPC0.SPMI._Y02._LEN, IPCL) - - IPDB = IDTP - IPDH = IDTP - IPDL = 0x01 - - IPCB = ICDP - IPCH = ICDP - IPCL = 0x01 - - Return (ICRS) - } - Method (_IFT, 0, NotSerialized) { - Return (0x01) - } - Method(_SRV, 0, NotSerialized) { - Return (0x0200) - } - } - - Device (SYSR) - { - Name (_HID, EisaId ("PNP0C02")) - - Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings - { - IO (Decode16, - 0x0CA2, - 0x0CA2, - 0x01, - 0x01, - ) - IO (Decode16, - 0x0CA6, - 0x0CA6, - 0x01, - 0x01, - ) - IO (Decode16, - 0x0CA8, - 0x0CA8, - 0x01, - 0x01, - ) - IO (Decode16, - 0x0CAC, - 0x0CAC, - 0x01, - 0x01, - ) - }) - } - } - #include "acpi/mainboard.asl" } diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c index bbfeeaf..4395436 100644 --- a/src/mainboard/ocp/monolake/mainboard.c +++ b/src/mainboard/ocp/monolake/mainboard.c @@ -20,46 +20,12 @@ #include <x86emu/x86emu.h> #endif -#define BMC_KCS_BASE 0xca2 -#define INTERFACE_IS_IO 0x1 - -#if CONFIG(GENERATE_SMBIOS_TABLES) -static int mainboard_smbios_data(struct device *dev, int *handle, - unsigned long *current) -{ - int len = 0; - - // add IPMI Device Information - len += smbios_write_type38( - current, handle, - SMBIOS_BMC_INTERFACE_KCS, - 0x20, // IPMI Version - 0x20, // I2C address - 0xff, // no NV storage - BMC_KCS_BASE | INTERFACE_IS_IO, // IO port interface address - 0x40, - 0); // no IRQ - - return len; -} -#endif - /* * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. */ static void mainboard_enable(struct device *dev) { -#if CONFIG(GENERATE_SMBIOS_TABLES) - dev->ops->get_smbios_data = mainboard_smbios_data; -#endif - - /* Enable access to the BMC IPMI via KCS */ - struct device *lpc_sio_dev = dev_find_slot_pnp(BMC_KCS_BASE, 0); - struct resource *res = new_resource(lpc_sio_dev, BMC_KCS_BASE); - res->base = BMC_KCS_BASE; - res->size = 1; - res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I419713c9bef02084cca1ff4cf11c33c2e3e8d3c1 Gerrit-Change-Number: 33490 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: drivers/ipmi/ipmi_kcs_ops: Advertise correct register spacing
by Patrick Rudolph (Code Review) 02 Sep '19

02 Sep '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35152 ) Change subject: drivers/ipmi/ipmi_kcs_ops: Advertise correct register spacing ...................................................................... drivers/ipmi/ipmi_kcs_ops: Advertise correct register spacing Advertise the register spacing used by the BMC as set by the Kconfig. Needs test on FB Watson and OCP Weedge100s. Change-Id: Ib926d30f6a0e78fbf613a6f71f765c5f51eee77d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/ipmi/ipmi_kcs_ops.c 1 file changed, 28 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/35152/1 diff --git a/src/drivers/ipmi/ipmi_kcs_ops.c b/src/drivers/ipmi/ipmi_kcs_ops.c index 21102bb..21f927e 100644 --- a/src/drivers/ipmi/ipmi_kcs_ops.c +++ b/src/drivers/ipmi/ipmi_kcs_ops.c @@ -126,10 +126,21 @@ u32 apic_interrupt = 0; acpi_addr_t addr = { .space_id = ACPI_ADDRESS_SPACE_IO, - .access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS, .addrl = dev->path.pnp.port, }; + switch (CONFIG_IPMI_KCS_REGISTER_SPACING) { + case 4: + addr.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + break; + case 16: + default: /* fallthrough */ + printk(BIOS_ERR, "IPMI: Unsupported register spacing for SPMI\n"); + case 1: /* fallthrough */ + addr.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + break; + } + current = ALIGN_UP(current, 8); printk(BIOS_DEBUG, "ACPI: * SPMI at %lx\n", current); spmi = (struct acpi_spmi *)current; @@ -214,6 +225,8 @@ struct drivers_ipmi_config *conf = NULL; u8 nv_storage = 0xff; u8 i2c_address = 0; + u8 register_spacing; + int len = 0; if (dev->chip_info) @@ -225,6 +238,20 @@ i2c_address = conf->bmc_i2c_address; } + switch (CONFIG_IPMI_KCS_REGISTER_SPACING) { + case 4: + register_spacing = 1 << 6; + break; + case 16: + register_spacing = 2 << 6; + break; + default: + printk(BIOS_ERR, "IPMI: Unsupported register spacing for SMBIOS\n"); + case 1: /* fallthrough */ + register_spacing = 0 << 6; + break; + } + // add IPMI Device Information len += smbios_write_type38( current, handle, -- To view, visit https://review.coreboot.org/c/coreboot/+/35152 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib926d30f6a0e78fbf613a6f71f765c5f51eee77d Gerrit-Change-Number: 35152 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: security/intel: Add TXT infrastructure
by Patrick Rudolph (Code Review) 02 Sep '19

02 Sep '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34585 ) Change subject: security/intel: Add TXT infrastructure ...................................................................... security/intel: Add TXT infrastructure * Add Kconfig to enable TXT * Add possibility to add BIOS and SINIT ACMs * Set default BIOS ACM alignment * Increase FIT space if TXT is enabled The following commits depend on the basic Kconfig infrastructure. Intel TXT isn't supported until all following commits are merged. Change-Id: I5f0f956d2b7ba43d4e7e0062803c6d8ba569a052 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/security/intel/txt.md M src/cpu/intel/fit/Kconfig M src/security/Kconfig M src/security/Makefile.inc A src/security/intel/Kconfig A src/security/intel/Makefile.inc A src/security/intel/txt/Kconfig A src/security/intel/txt/Makefile.inc M src/soc/intel/cannonlake/Kconfig M src/soc/intel/skylake/Kconfig 10 files changed, 115 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/34585/1 diff --git a/Documentation/security/intel/txt.md b/Documentation/security/intel/txt.md index f67b639..f80a731 100644 --- a/Documentation/security/intel/txt.md +++ b/Documentation/security/intel/txt.md @@ -90,11 +90,11 @@ ## For developers ### Configuring Intel TXT in Kconfig -Enable ``TEE_INTEL_TXT`` and set the following: +Enable ``INTEL_TXT`` and set the following: -``TEE_INTEL_TXT_BIOSACM_FILE`` to the path of the BIOS ACM provided by Intel +``INTEL_TXT_BIOSACM_FILE`` to the path of the BIOS ACM provided by Intel -``TEE_INTEL_TXT_SINITACM_FILE`` to the path of the SINIT ACM provided by Intel +``INTEL_TXT_SINITACM_FILE`` to the path of the SINIT ACM provided by Intel ### Print TXT status as early as possible Add platform code to print the TXT status as early as possible, as the register is cleared on cold reset. diff --git a/src/cpu/intel/fit/Kconfig b/src/cpu/intel/fit/Kconfig index e48dca9..fa10802 100644 --- a/src/cpu/intel/fit/Kconfig +++ b/src/cpu/intel/fit/Kconfig @@ -5,6 +5,7 @@ config CPU_INTEL_NUM_FIT_ENTRIES int + default 16 if INTEL_TXT default 4 depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE help diff --git a/src/security/Kconfig b/src/security/Kconfig index 8a1531a..4e08bbd 100644 --- a/src/security/Kconfig +++ b/src/security/Kconfig @@ -15,3 +15,4 @@ source "src/security/vboot/Kconfig" source "src/security/tpm/Kconfig" source "src/security/memory/Kconfig" +source "src/security/intel/Kconfig" diff --git a/src/security/Makefile.inc b/src/security/Makefile.inc index f62413e..fd78438 100644 --- a/src/security/Makefile.inc +++ b/src/security/Makefile.inc @@ -1,3 +1,4 @@ subdirs-y += vboot subdirs-y += tpm subdirs-y += memory +subdirs-y += intel diff --git a/src/security/intel/Kconfig b/src/security/intel/Kconfig new file mode 100644 index 0000000..333e385 --- /dev/null +++ b/src/security/intel/Kconfig @@ -0,0 +1,20 @@ +## This file is part of the coreboot project. +## +## Copyright (C) 2019 9elements Agency GmbH +## Copyright (C) 2019 Facebook Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +menu "Intel" + +source "src/security/intel/txt/Kconfig" + +endmenu # Intel diff --git a/src/security/intel/Makefile.inc b/src/security/intel/Makefile.inc new file mode 100644 index 0000000..9388d3f --- /dev/null +++ b/src/security/intel/Makefile.inc @@ -0,0 +1 @@ +subdirs-y += txt diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig new file mode 100644 index 0000000..b6c5d19 --- /dev/null +++ b/src/security/intel/txt/Kconfig @@ -0,0 +1,55 @@ +## This file is part of the coreboot project. +## +## Copyright (C) 2019 9elements Agency GmbH +## Copyright (C) 2019 Facebook Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config INTEL_TXT + bool "Intel TXT support" + default n + select MRC_SETTINGS_PROTECT if CACHE_MRC_SETTINGS + select SOC_INTEL_COMMON_BLOCK_VMX if PLATFORM_USES_FSP2_0 + select AP_IN_SIPI_WAIT + depends on TSC_CONSTANT_RATE + depends on (TPM1 || TPM2) + depends on CPU_INTEL_FIRMWARE_INTERFACE_TABLE + depends on PLATFORM_HAS_DRAM_CLEAR + depends on SOC_INTEL_FSP_BROADWELL_DE || SOC_INTEL_COMMON_BLOCK_SA + +if INTEL_TXT + +config INTEL_TXT_BIOSACM_FILE + string "BIOS ACM file" + default "3rdparty/blobs/soc/intel/fsp_broadwell_de/biosacm.bin" if SOC_INTEL_FSP_BROADWELL_DE + default "3rdparty/blobs/soc/intel/skylake/biosacm.bin" if SOC_INTEL_COMMON_SKYLAKE_BASE + help + Intel TXT BIOS ACM file. This file can be obtained by privileged + access to intel resources. Or for some platforms found inside the + blob repository. + +config INTEL_TXT_SINITACM_FILE + string "SINIT ACM file" + default "3rdparty/blobs/soc/intel/fsp_broadwell_de/sinitacm.bin" if SOC_INTEL_FSP_BROADWELL_DE + default "3rdparty/blobs/soc/intel/skylake/sinitacm.bin" if SOC_INTEL_COMMON_SKYLAKE_BASE + help + Intel TXT SINIT ACM file. This file can be obtained by privileged + access to intel resources. Or for some platforms found inside the + blob repository. + +config INTEL_TXT_BIOSACM_ALIGNMENT + hex + default 0x20000 # 128KB + help + Exceptions are Ivy- and Sandybridge with 64KB and Purely with 256KB + alignment size. Please overwrite it SoC specific. + +endif diff --git a/src/security/intel/txt/Makefile.inc b/src/security/intel/txt/Makefile.inc new file mode 100644 index 0000000..f123510 --- /dev/null +++ b/src/security/intel/txt/Makefile.inc @@ -0,0 +1,25 @@ +ifeq ($(CONFIG_INTEL_TXT),y) + +cbfs-files-y += txt_bios_acm.bin +txt_bios_acm.bin-file := $(CONFIG_INTEL_TXT_BIOSACM_FILE) +txt_bios_acm.bin-type := raw +txt_bios_acm.bin-align := $(CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT) + +cbfs-files-($(CONFIG_INTEL_FIT_BIOS_POLICY)) += txt_bios_policy.bin +txt_bios_policy.bin-file := $(objgenerated)/txt_bios_policy.bin +txt_bios_policy.bin-type := raw +txt_bios_policy.bin-align := 0x10 + +ifneq ($(CONFIG_INTEL_TXT_SINITACM_FILE),"") +cbfs-files-y += txt_sinit_acm.bin +txt_sinit_acm.bin-file := $(CONFIG_INTEL_TXT_SINITACM_FILE) +txt_sinit_acm.bin-type := raw +txt_sinit_acm.bin-align := 0x10 +txt_sinit_acm.bin-compression := lzma +endif + +INTERMEDIATE+=add_acm_fit +add_acm_fit: $(obj)/coreboot.pre $(IFITTOOL) + $(IFITTOOL) -r COREBOOT -a -n txt_bios_acm.bin -t 2 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -f $< + +endif diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f859cd5..a63b829 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -319,4 +319,8 @@ hex default 0xe00 +config INTEL_TXT_BIOSACM_ALIGNMENT + hex + default 0x40000 # 256KB + endif diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f36d5ca..310619e 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -309,4 +309,8 @@ string default "sklkbl" +config INTEL_TXT_BIOSACM_ALIGNMENT + hex + default 0x40000 # 256KB + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f0f956d2b7ba43d4e7e0062803c6d8ba569a052 Gerrit-Change-Number: 34585 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: mainboars: lenovo: add basic implementation for ts p320
by Michael Niewöhner (Code Review) 01 Sep '19

01 Sep '19

Michael Niewöhner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34947 ) Change subject: mainboars: lenovo: add basic implementation for ts p320 ...................................................................... mainboars: lenovo: add basic implementation for ts p320 Change-Id: Ifda0144255c55f124688c133eac57d88498700d8 --- A src/mainboard/lenovo/thinkstation_p320/Kconfig A src/mainboard/lenovo/thinkstation_p320/Kconfig.name A src/mainboard/lenovo/thinkstation_p320/Makefile.inc A src/mainboard/lenovo/thinkstation_p320/acpi/ec.asl A src/mainboard/lenovo/thinkstation_p320/acpi/mainboard.asl A src/mainboard/lenovo/thinkstation_p320/acpi/superio.asl A src/mainboard/lenovo/thinkstation_p320/acpi_tables.c A src/mainboard/lenovo/thinkstation_p320/board_info.txt A src/mainboard/lenovo/thinkstation_p320/bootblock.c A src/mainboard/lenovo/thinkstation_p320/cmos.layout A src/mainboard/lenovo/thinkstation_p320/devicetree.cb A src/mainboard/lenovo/thinkstation_p320/dsdt.asl A src/mainboard/lenovo/thinkstation_p320/gpio.h A src/mainboard/lenovo/thinkstation_p320/mainboard.c A src/mainboard/lenovo/thinkstation_p320/ramstage.c A src/mainboard/lenovo/thinkstation_p320/romstage.c 16 files changed, 1,068 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/34947/1 diff --git a/src/mainboard/lenovo/thinkstation_p320/Kconfig b/src/mainboard/lenovo/thinkstation_p320/Kconfig new file mode 100644 index 0000000..13a8e35 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/Kconfig @@ -0,0 +1,50 @@ +if BOARD_LENOVO_THINKSTATION_P320 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select SOC_INTEL_KABYLAKE + select SKYLAKE_SOC_PCH_H + select MAINBOARD_USES_FSP2_0 + select MAINBOARD_HAS_LPC_TPM + select GENERATE_SMBIOS_TABLES + select SUPERIO_NUVOTON_NCT6683D + select SUPERIO_NUVOTON_NCT6683D_COM_A + + +config SOC_INTEL_COMMON_BLOCK_SGX + bool + default y + +config MAINBOARD_DIR + string + default "lenovo/thinkstation_p320" + +config MAINBOARD_PART_NUMBER + string + default "ThinkStation P320" + +config MAX_CPUS + int + default 8 + +config IRQ_SLOT_COUNT + int + default 18 + +config SUBSYSTEM_VENDOR_ID + hex + default 0x8086 + +config CONSOLE_POST + bool + default y + +config DIMM_SPD_SIZE + int + default 512 #DDR4 + +endif # BOARD_LENOVO_THINKSTATION_P320 diff --git a/src/mainboard/lenovo/thinkstation_p320/Kconfig.name b/src/mainboard/lenovo/thinkstation_p320/Kconfig.name new file mode 100644 index 0000000..df22214 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_THINKSTATION_P320 + bool "ThinkStation P320 (IQ1X0MS)" diff --git a/src/mainboard/lenovo/thinkstation_p320/Makefile.inc b/src/mainboard/lenovo/thinkstation_p320/Makefile.inc new file mode 100644 index 0000000..e9af214 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +bootblock-y += bootblock.c + +ramstage-y += mainboard.c +ramstage-y += ramstage.c diff --git a/src/mainboard/lenovo/thinkstation_p320/acpi/ec.asl b/src/mainboard/lenovo/thinkstation_p320/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/acpi/ec.asl diff --git a/src/mainboard/lenovo/thinkstation_p320/acpi/mainboard.asl b/src/mainboard/lenovo/thinkstation_p320/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/acpi/mainboard.asl diff --git a/src/mainboard/lenovo/thinkstation_p320/acpi/superio.asl b/src/mainboard/lenovo/thinkstation_p320/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/acpi/superio.asl diff --git a/src/mainboard/lenovo/thinkstation_p320/acpi_tables.c b/src/mainboard/lenovo/thinkstation_p320/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/acpi_tables.c diff --git a/src/mainboard/lenovo/thinkstation_p320/board_info.txt b/src/mainboard/lenovo/thinkstation_p320/board_info.txt new file mode 100644 index 0000000..a6124eb --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Lenovo +Board name: ThinkStation P320 (IQ1X0MS1) +Category: workstation +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/lenovo/thinkstation_p320/bootblock.c b/src/mainboard/lenovo/thinkstation_p320/bootblock.c new file mode 100644 index 0000000..08c4f2c --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/bootblock.c @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <bootblock_common.h> +#include <soc/gpio.h> +#include "gpio.h" +//#include <superio/aspeed/common/aspeed.h> +//#include <superio/aspeed/ast2400/ast2400.h> +#include <device/pnp_ops.h> +#include <device/pnp.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6683d/nct6683d.h> +#include <delay.h> +#include <console/uart.h> +#include <console/console.h> +#include <halt.h> +#include <intelblocks/lpc_lib.h> +#include <soc/pch.h> +#include <soc/pci_devs.h> +#include <device/pci_ops.h> +#include <soc/bootblock.h> + +#define LPC_IO_ENABLES 0x82 + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6683D_SP1) +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + + +static void print_reg(u8 dev, u8 reg) { + printk(BIOS_DEBUG, "0x%x: %x\n", reg, pnp_read_config(dev, reg)); +} + +static void early_config_superio(void) +{ + /* + * at this point any ec/sio lpc address deconding must be enabled in the + * chipset registers. relevant registers are 0x80, 0x82, 0x84 + */ + + //lpc_soc_init(SERIAL_DEV); + //enable_lpc(); + //pch_early_iorange_init(); + //uint16_t l = pci_read_config16(PCH_DEV_LPC, 0x82); + + uint16_t pcipnptmp = pci_read_config16(PCH_DEV_LPC, 0x80); + pci_write_config16(PCH_DEV_LPC, ..., pcipnptmp | ...); + + if (CONFIG(CONSOLE_SERIAL)) { + //const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT6683D_SP1); + //nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); + pnp_devfn_t dev = PNP_DEV(0x2e, 0); + u8 pnptmp; + + nuvoton_pnp_enter_conf_state(dev); + + /* + * I reverse engineered the initialization phase from + * NCT6685DPeiInit (lenovo UEFI image). + * Most of this should be moved to the sio driver + * while keeping anything related to uart early init here + */ + + pnp_set_logical_device(dev); + pnptmp = pnp_read_config(dev, 0x1d); + pnp_write_config(dev, 0x1d, (pnptmp & 0xf7) | 0x08); + pnptmp = pnp_read_config(dev, 0x13); + pnp_write_config(dev, 0x13, (pnptmp & 0xf3) | 0x0c); + pnp_write_config(dev, 0x15, 0xf0); + pnp_write_config(dev, 0x1a, 0x03); + pnptmp = pnp_read_config(dev, 0x1b); + pnp_write_config(dev, 0x1b, (pnptmp & 0x0f) | 0xf0); + pnp_write_config(dev, 0x1d, 0x00); + pnp_write_config(dev, 0x14, 0x00); + pnp_write_config(dev, 0x1e, 0xf0); + pnp_write_config(dev, 0x1f, 0xf0); + pnptmp = pnp_read_config(dev, 0x22); + pnp_write_config(dev, 0x22, (pnptmp & 0x43) | 0xbc); + pnptmp = pnp_read_config(dev, 0x23); + pnp_write_config(dev, 0x23, (pnptmp & 0x20) | 0xdf); + pnptmp = pnp_read_config(dev, 0x24); + print_reg(dev, 0x1b); + print_reg(dev, 0x1d); + print_reg(dev, 0x24); + pnp_write_config(dev, 0x24, (pnptmp & 0x06) | 0x81); + pnp_write_config(dev, 0x25, 0xff); + pnp_write_config(dev, 0x26, 0x00); + pnptmp = pnp_read_config(dev, 0x27); + pnp_write_config(dev, 0x27, (pnptmp & 0xc0) | 0xbe); + pnp_write_config(dev, 0x28, 0x00); + pnp_write_config(dev, 0x29, 0xed); + pnptmp = pnp_read_config(dev, 0x2a); + pnp_write_config(dev, 0x2a, (pnptmp & 0x40) | 0x8f); + pnp_write_config(dev, 0x2b, 0x00); + pnptmp = pnp_read_config(dev, 0x27); + pnp_write_config(dev, 0x27, (pnptmp & 0x3f) | 0xc0); + pnptmp = pnp_read_config(dev, 0x1b); + pnp_write_config(dev, 0x1b, (pnptmp & 0xf7) | 0x00); + pnptmp = pnp_read_config(dev, 0x24); + pnp_write_config(dev, 0x24, (pnptmp & 0xf9) | 0x00); + pnptmp = pnp_read_config(dev, 0x2a); + pnp_write_config(dev, 0x2a, (pnptmp & 0xbf) | 0x40); + dev = PNP_DEV(0x2e, 0x05); + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x0060); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x0064); + pnp_set_irq(dev, PNP_IDX_IRQ0, 0x01); + pnp_set_irq(dev, PNP_IDX_IRQ1, 0x0c); + pnp_set_enable(dev, 0x01); + dev = PNP_DEV(0x2e, 0x03); + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x03f8); + pnp_set_enable(dev, 0x01); + dev = PNP_DEV(0x2e, 0x0b); + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x0a20); + pnp_set_enable(dev, 0x01); + dev = PNP_DEV(0x2e, 0x00); + pnptmp = pnp_read_config(dev, 0x1b); + pnp_write_config(dev, 0x1b, pnptmp | 0x08); + nuvoton_pnp_exit_conf_state(dev); + } +} + + +void bootblock_mainboard_early_init(void) +{ + early_config_gpio(); + early_config_superio(); +} diff --git a/src/mainboard/lenovo/thinkstation_p320/cmos.layout b/src/mainboard/lenovo/thinkstation_p320/cmos.layout new file mode 100644 index 0000000..201ca33 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/cmos.layout @@ -0,0 +1,62 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name + +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 6 debug_level +448 128 r 0 vbnv + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/lenovo/thinkstation_p320/devicetree.cb b/src/mainboard/lenovo/thinkstation_p320/devicetree.cb new file mode 100644 index 0000000..6eb2be4 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/devicetree.cb @@ -0,0 +1,360 @@ +## dt + +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + #register "gen1_dec" = "0x007c0a01" # Super IO + #register "gen2_dec" = "0x000c0ca1" # IPMI KCS + #register "gen3_dec" = "0x000c03e1" # UART3/4 + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # FSP Configuration + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "SaGv" = "SaGv_Enabled" + + # Disable SGX + register "sgx_enable" = "0" # SGX is broken in coreboot + register "PrmrrSize" = "128 * MiB" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + register "SataMode" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + + register "SataPortsDevSlp" = "{\ + [0] = 0, \ + [1] = 0, \ + [2] = 0, \ + [3] = 0, \ + [4] = 0, \ + [5] = 0, \ + [6] = 0, \ + [7] = 0, \ + }" + + # USB related + register "SsicPortEnable" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # OTG + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Touch Pad + register "usb2_ports[14]" = "USB2_PORT_MID(OC0)" # OTG + register "usb2_ports[15]" = "USB2_PORT_MID(OC0)" # Touch Pad + + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # OTG + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" # Touch Pad + + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # OTG + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" # Touch Pad + + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # OTG + register "usb2_ports[12]" = "USB2_PORT_MID(OC3)" # Touch Pad + + register "usb2_ports[10]" = "USB2_PORT_MID(OC4)" # OTG + register "usb2_ports[11]" = "USB2_PORT_MID(OC4)" # Touch Pad + + register "usb2_ports[9]" = "USB2_PORT_MID(OC5)" # Touch Pad + + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # IPMI USB HUB + + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # OTG + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC3)" # M.2 WWAN + + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC4)" # OTG + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC4)" # M.2 WWAN + + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC5)" # M.2 WWAN + + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # Enable PCIE slot + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "0" + + # Enable PCIE slot + register "PcieRpEnable[2]" = "1" + register "PcieRpClkReqSupport[2]" = "0" + + # Enable PCIE slot + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "0" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x10, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0 ,\ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + ## VR Settings Configuration for 4 Domains + ##+----------------+-------+-------+-------+-------+ + ##| Domain/Setting | SA | IA | GTUS | GTS | + ##+----------------+-------+-------+-------+-------+ + ##| Psi1Threshold | 20A | 20A | 20A | 20A | + ##| Psi2Threshold | 5A | 5A | 5A | 5A | + ##| Psi3Threshold | 1A | 1A | 1A | 1A | + ##| Psi3Enable | 1 | 1 | 1 | 1 | + ##| Psi4Enable | 1 | 1 | 1 | 1 | + ##| ImonSlope | 0 | 0 | 0 | 0 | + ##| ImonOffset | 0 | 0 | 0 | 0 | + ##| IccMax | 7A | 34A | 35A | 35A | + ##| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + ##+----------------+-------+-------+-------+-------+ + #register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + # .vr_config_enable = 1, \ + # .psi1threshold = 0x50, \ + # .psi2threshold = 0x10, \ + # .psi3threshold = 0x4, \ + # .psi3enable = 1, \ + # .psi4enable = 1, \ + # .imon_slope = 0x0, \ + # .imon_offset = 0x0, \ + # .icc_max = 0x1C, \ + # .voltage_limit = 0x5F0 \ + #}" + # + #register "domain_vr_config[VR_IA_CORE]" = "{ + # .vr_config_enable = 1, \ + # .psi1threshold = 0x50, \ + # .psi2threshold = 0x14, \ + # .psi3threshold = 0x4, \ + # .psi3enable = 1, \ + # .psi4enable = 1, \ + # .imon_slope = 0x0, \ + # .imon_offset = 0x0, \ + # .icc_max = 0x88, \ + # .voltage_limit = 0x5F0 \ + #}" + # + #register "domain_vr_config[VR_GT_UNSLICED]" = "{ + # .vr_config_enable = 1, \ + # .psi1threshold = 0x50, \ + # .psi2threshold = 0x14, \ + # .psi3threshold = 0x4, \ + # .psi3enable = 1, \ + # .psi4enable = 1, \ + # .imon_slope = 0x0, \ + # .imon_offset = 0x0, \ + # .icc_max = 0x8C ,\ + # .voltage_limit = 0x5F0 \ + #}" + # + #register "domain_vr_config[VR_GT_SLICED]" = "{ + # .vr_config_enable = 1, \ + # .psi1threshold = 0x50, \ + # .psi2threshold = 0x14, \ + # .psi3threshold = 0x4, \ + # .psi3enable = 1, \ + # .psi4enable = 1, \ + # .imon_slope = 0x0, \ + # .imon_offset = 0x0, \ + # .icc_max = 0x8C, \ + # .voltage_limit = 0x5F0 \ + #}" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 01.0 on end # PCI Slot + device pci 01.1 on + smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X" + end # PCIE Slot (JPCIE1) + device pci 14.0 on end # USB xHCI + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 on end # Management Engine Interface 2 + device pci 17.0 on end # SATA + device pci 1c.0 on + smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X" + end # PCI Express Port 1 (Slot JPCIE1) + device pci 1e.0 on end # UART 0 + device pci 1e.1 on end # UART 1 + device pci 1f.0 on # LPC bridge + #subsystemid 0x1849 0x1a43 + chip superio/nuvoton/nct6791d + #device pnp 2e.0 on end + device pnp 2e.1 off # Parallel + ## global + #irq 0x1c = 0x10 + #irq 0x27 = 0x10 + #irq 0x2a = 0x64 + ## parallel port + #io 0x60 = 0x0378 + #irq 0x70 = 7 + #drq 0x74 = 4 # No DMA + #irq 0xf0 = 0x3c # Printer mode + end + device pnp 2e.2 off # UART A + io 0x60 = 0x02f8 + #irq 0x70 = 4 + end + device pnp 2e.3 on # UART B, IR + io 0x60 = 0x03f8 + #irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + #device pnp 2e.107 off end # GPIO7 + #device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + #device pnp 2e.108 off end # GPIO0 + #device pnp 2e.308 off end # GPIO base + #device pnp 2e.408 off end # WDTMEM + #device pnp 2e.708 off end # GPIO1 + device pnp 2e.9 off end # GPIO2 + #device pnp 2e.109 off end # GPIO3 + #device pnp 2e.209 off end # GPIO4 + #device pnp 2e.309 off end # GPIO5 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, LED + # io 0x60 = 0x0290 + # io 0x62 = 0 + # irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + #device pnp 2e.f off end # GPIO PP/OD + #device pnp 2e.14 off end # SVID, Port 80 UART + #device pnp 2e.16 off end # DS5 + #device pnp 2e.116 off end # DS3 + #device pnp 2e.316 off end # PCHDSW + #device pnp 2e.416 off end # DSWWOPT + #device pnp 2e.516 off end # DS3OPT + #device pnp 2e.616 off end # DSDSS + #device pnp 2e.716 off end # DSPU + end # superio/nuvoton/nct6791d + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM module + end + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # SPI Controller + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/lenovo/thinkstation_p320/dsdt.asl b/src/mainboard/lenovo/thinkstation_p320/dsdt.asl new file mode 100644 index 0000000..ac929a6 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/dsdt.asl @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/lenovo/thinkstation_p320/gpio.h b/src/mainboard/lenovo/thinkstation_p320/gpio.h new file mode 100644 index 0000000..c3c3997 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/gpio.h @@ -0,0 +1,280 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIO_LNV_IQ1X0MS1_H +#define _GPIO_LNV_IQ1X0MS1_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#define IQ1X0MS1_PAD_DW0_DW1_CFG(val, config0, config1) \ + _PAD_CFG_STRUCT(val, config0, config1) + + +/* BIOS Flash Write Protect */ +//#define GPIO_PCH_WP GPP_C23 + +// ifndef __ACPI__ needed here? x11ssh has it, h110m-dvs not.... + +#ifndef __ACPI__ +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A7, 0x84000502, 0x0000001f), /* PIRQA# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A11, 0x84000502, 0x00000023), /* PME# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A12, 0x84000502, 0x00000024), /* BM_BUSY# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A16, 0x44000200, 0x00003028), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A17, 0x84000201, 0x00000029), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A18, 0x84000200, 0x0000002a), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A19, 0x44000200, 0x0000302b), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A20, 0x84000200, 0x0000002c), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A21, 0x84000100, 0x0000002d), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ + + /* GPIO Group GPP_B */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B0, 0x84000200, 0x00000030), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B1, 0x84000200, 0x00000031), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B2, 0x84000502, 0x00000032), /* VRALERT# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B3, 0x84000200, 0x00000033), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B4, 0x84000200, 0x00000034), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B6, 0x84000200, 0x00000036), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B7, 0x84000100, 0x00000037), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00000038), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B9, 0x84000500, 0x00000039), /* SRCCLKREQ4# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B10, 0x44000702, 0x0000003a), /* SRCCLKREQ5# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B11, 0x84000200, 0x0000003b), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B12, 0x44000600, 0x0000003c), /* SLP_S0# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B13, 0x44000600, 0x0000003d), /* PLTRST# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B14, 0x84060600, 0x0000103e), /* SPKR */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B15, 0x84000201, 0x0000003f), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B17, 0x84000200, 0x00000041), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B18, 0x84000500, 0x00000042), /* GSPIO_MOSI */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B19, 0x84000200, 0x00000043), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B20, 0x84060102, 0x00000044), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B21, 0x84000200, 0x00000045), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B22, 0x84000500, 0x00000046), /* GSPI1_MOSI */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_B23, 0x84060500, 0x00001047), /* SML1ALERT# */ + + /* GPIO Group GPP_C */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C0, 0x44000502, 0x00000048), /* SMBCLK */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C1, 0x44000502, 0x00000049), /* SMBDATA */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C2, 0x44000502, 0x0000004a), /* SMBALERT# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C3, 0x44000502, 0x0000004b), /* SML0CLK */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C4, 0x44000502, 0x0000004c), /* SML0DATA */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C5, 0x84000500, 0x0000004d), /* SML0ALERT# */ + //IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C6, 0xffffffff, 0xffffffff), /* RESERVED */ + //IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C7, 0xffffffff, 0xffffffff), /* RESERVED */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C8, 0x84000102, 0x00000050), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C9, 0x84000200, 0x00000051), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C10, 0x84000200, 0x00000052), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C11, 0x84000102, 0x00000053), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C12, 0x84000201, 0x00000054), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C13, 0x84000201, 0x00000055), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C15, 0x84000201, 0x00000057), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C16, 0x84000200, 0x00000058), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C17, 0x84000200, 0x00000059), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C18, 0x84000200, 0x0000005a), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C19, 0x84000200, 0x0000005b), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C20, 0x84000200, 0x0000005c), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C21, 0x84000200, 0x0000005d), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C22, 0x84060200, 0x0000005e), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_C23, 0x84060200, 0x0000005f), /* GPIO */ + + /* GPIO Group GPP_D */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D0, 0x84060200, 0x00000060), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D1, 0x84000201, 0x00000061), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D2, 0x84060500, 0x00000062), /* n/a */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D3, 0x84060500, 0x00000063), /* n/a */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D4, 0x04060201, 0x00000064), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D5, 0x04000200, 0x00000065), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D6, 0x04000200, 0x00000066), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D7, 0x04000200, 0x00000067), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D8, 0x04000200, 0x00000068), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D9, 0x04000200, 0x00000069), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D10, 0x04000200, 0x0000006a), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D14, 0x84000102, 0x0000006e), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D15, 0x84000102, 0x0000006f), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D16, 0x84000200, 0x00000070), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D19, 0x84000200, 0x00000073), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D20, 0x84000200, 0x00000074), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D21, 0x84000200, 0x00000075), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D22, 0x84000200, 0x00000076), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_D23, 0x84000200, 0x00000077), /* GPIO */ + + /* GPIO Group GPP_E */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E0, 0x84060200, 0x00003018), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E1, 0x84060200, 0x00003019), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E2, 0x84060200, 0x0000301a), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E3, 0x84060201, 0x0000001b), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E4, 0x84060201, 0x0000001c), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E5, 0x80880102, 0x0000001d), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E6, 0x84060200, 0x0000001e), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E7, 0x84060200, 0x0000001f), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E8, 0x84000600, 0x00000020), /* SATA_LED# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E9, 0x44000502, 0x00000021), /* USB_OC0# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E10, 0x44000502, 0x00000022), /* USB_OC1# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E11, 0x44000502, 0x00000023), /* USB_OC2# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_E12, 0x44000502, 0x00000024), /* USB_OC3# */ + + /* GPIO Group GPP_F */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F0, 0x84000200, 0x00000025), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F1, 0x84000600, 0x00000026), /* SATAXPCIE4 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F2, 0x84000600, 0x00000027), /* SATAXPCIE5 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F3, 0x84000200, 0x00000028), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F4, 0x84000200, 0x00000029), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F5, 0x02080500, 0x0000002a), /* SATA_DEVSLP3 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F6, 0x44000102, 0x0000002b), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F7, 0x42080200, 0x0000002c), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F8, 0x84000200, 0x0000002d), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F10, 0x80100600, 0x0000002f), /* SATA_SCLOCK */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F11, 0x84000600, 0x00000030), /* SATA_SLOAD */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F12, 0x80100600, 0x00000031), /* SATA_SDATAOUT1 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F13, 0x80100600, 0x00000032), /* SATA_SDATAOUT2 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F14, 0x40100100, 0x00000033), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F15, 0x44000502, 0x00000034), /* USB_OC4# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F16, 0x44000502, 0x00000035), /* USB_OC5# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F17, 0x44000502, 0x00000036), /* USB_OC6# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F18, 0x84000502, 0x00000037), /* USB_OC7# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F19, 0x84000200, 0x00000038), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F20, 0x84000200, 0x00000039), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F21, 0x84000200, 0x0000003a), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F22, 0x84000201, 0x0000003b), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_F23, 0x84000200, 0x0000003c), /* GPIO */ + + /* GPIO Group GPP_G */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G0, 0x84000100, 0x0000003d), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G1, 0x84000100, 0x0000003e), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G2, 0x84000201, 0x0000003f), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G3, 0x84000201, 0x00000040), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G4, 0x84000200, 0x00000041), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G5, 0x84000200, 0x00000042), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G6, 0x84000200, 0x00000043), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G7, 0x84000200, 0x00000044), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G8, 0x84000200, 0x00000045), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G9, 0x84000200, 0x00000046), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G10, 0x84000200, 0x00000047), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G11, 0x84000201, 0x00000048), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G12, 0x84000100, 0x00000049), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G13, 0x84000100, 0x0000004a), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G14, 0x84000100, 0x0000004b), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G15, 0x84000102, 0x0000004c), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G16, 0x84000100, 0x0000004d), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G18, 0x80100201, 0x0000004f), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G19, 0x84800102, 0x00000050), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_G23, 0x84000201, 0x00000054), /* GPIO */ + + /* GPIO Group GPP_H */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H1, 0x04000201, 0x00000056), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H4, 0x84000200, 0x00000059), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H5, 0x84000200, 0x0000005a), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H6, 0x84000200, 0x0000005b), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H7, 0x84000200, 0x0000005c), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H8, 0x84000200, 0x0000005d), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H9, 0x84000200, 0x0000005e), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H10, 0x84000201, 0x0000005f), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H11, 0x84000201, 0x00000060), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H12, 0x84000200, 0x00000061), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H13, 0x84000200, 0x00000062), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H14, 0x84000200, 0x00000063), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H15, 0x84000201, 0x00000064), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H16, 0x84000200, 0x00000065), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H17, 0x84000200, 0x00000066), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H18, 0x84000201, 0x00000067), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H19, 0x84000200, 0x00000068), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H20, 0x84000200, 0x00000069), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H21, 0x84000200, 0x0000006a), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H22, 0x84000200, 0x0000006b), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_H23, 0x84000200, 0x0000006c), /* GPIO */ + + /* GPIO Group GPP_I */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I0, 0x84060500, 0x0000006d), /* DDPB_HPD0 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I1, 0x84060500, 0x0000006e), /* DDPC_HPD1 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I2, 0x84060500, 0x0000006f), /* DDPD_HPD2 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I3, 0x84060100, 0x00000070), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I5, 0x84000200, 0x00000072), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I6, 0x84000102, 0x00001073), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I7, 0x84000500, 0x00000074), /* DDPC_CTRLCLK */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I8, 0x84000500, 0x00001075), /* DDPC_CTRLDATA */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I9, 0x84000500, 0x00000076), /* DDPD_CTRLCLK */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_I10, 0x84000500, 0x00001077), /* DDPD_CTRLDATA */ + + /* GPIO Group GPD */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD0, 0x84000502, 0x00000018), /* BATLOW# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD1, 0x04000602, 0x00000019), /* ACPRESENT */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD2, 0x00080502, 0x0000101a), /* LAN_WAKE# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD3, 0x04000502, 0x0000301b), /* PWRBTN# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD4, 0x04000600, 0x0000001c), /* SLP_S3# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD5, 0x04000600, 0x0000001d), /* SLP_S4# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD6, 0x04000600, 0x0000001e), /* SLP_A# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD7, 0x04000200, 0x0000001f), /* GPIO */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD8, 0x04000600, 0x00000020), /* SUSCLK */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD9, 0x04000600, 0x00000021), /* SLP_WLAN# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD10, 0x04000600, 0x00000022), /* SLP_S5# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPD11, 0x04000600, 0x00000023), /* LANPHYPC */ +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + /* GPIO Group GPP_A */ + /* LPC */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A7, 0x84000502, 0x0000001f), /* PIRQA# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + /* SUS */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ + IQ1X0MS1_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ +}; +#endif /* __ACPI__ */ + +#endif /* _GPIO_LNV_IQ1X0MS1_H */ diff --git a/src/mainboard/lenovo/thinkstation_p320/mainboard.c b/src/mainboard/lenovo/thinkstation_p320/mainboard.c new file mode 100644 index 0000000..d09a373 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/mainboard.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> + +static void mainboard_enable(struct device *dev) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/thinkstation_p320/ramstage.c b/src/mainboard/lenovo/thinkstation_p320/ramstage.c new file mode 100644 index 0000000..bd86e0d --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/ramstage.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + params->CdClock = 3; + + /* This must be one, otherwise FSP crashes ... (from x11ssh)*/ + params->PchHdaVcType = 0x1; +} diff --git a/src/mainboard/lenovo/thinkstation_p320/romstage.c b/src/mainboard/lenovo/thinkstation_p320/romstage.c new file mode 100644 index 0000000..cb1f105 --- /dev/null +++ b/src/mainboard/lenovo/thinkstation_p320/romstage.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/api.h> +#include <soc/romstage.h> +#include <spd_bin.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + + struct spd_block blk = { + .addr_map = { 0x50, 0x51, 0x52, 0x53, }, + }; + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; + mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; + mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + mem_cfg->UserBd = BOARD_TYPE_SERVER; + + mupd->FspmTestConfig.DmiVc1 = 1; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifda0144255c55f124688c133eac57d88498700d8 Gerrit-Change-Number: 34947 Gerrit-PatchSet: 1 Gerrit-Owner: Michael Niewöhner Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Felix Singer (Code Review) 31 Aug '19

31 Aug '19

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... Patch Set 80: (5 comments) https://review.coreboot.org/c/coreboot/+/32734/68//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/32734/68//COMMIT_MSG@12 PS68, Line 12: * SeaBios payload : * LinuxBoot payload > master Done https://review.coreboot.org/c/coreboot/+/32734/68//COMMIT_MSG@15 PS68, Line 15: PCIe > Does PEG work with Gen3? Ack https://review.coreboot.org/c/coreboot/+/32734/68//COMMIT_MSG@25 PS68, Line 25: Please apply those patches as well for good user experience: : : I456be647b159f7a2ea7d94986a24424e56dcc8c4 : I22c6885eae6fd7c778ac37b18f95b8775e9064e3 : Ica0c20255f661dd61edc3a7d15646b7447c4658e > How do you add comments to the commit message? Done https://review.coreboot.org/c/coreboot/+/32734/72/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb: https://review.coreboot.org/c/coreboot/+/32734/72/src/mainboard/supermicro/… PS72, Line 234: ca2.0 > it's the default IPMI I/O KCS port. Have a look at dmidecode or ACPI tables to find this value. Done https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb: https://review.coreboot.org/c/coreboot/+/32734/74/src/mainboard/supermicro/… PS74, Line 239: device pnp 2e.0 off end > This device doesn't seem to exist Done -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 80 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 31 Aug 2019 19:37:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Christoph Pomaska <github(a)aufmachen.jetzt> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Maxim Polyakov <max.senia.poliak(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Felix Singer (Code Review) 31 Aug '19

31 Aug '19

Felix Singer has uploaded a new patch set (#81) to the change originally created by Christian Walter. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... mb/supermicro/x11ssh: Add Supermicro X11SSH-TF Add support for the X11SSH-TF which is based on Intel KBL. Working: * SeaBIOS payload * LinuxBoot payload * IPMI of BMC * PCIe, SATA, USB and M.2 ports * RS232 serial * Native graphics init Not working: * TianoCore doesn't work yet as the Aspeed NGI is text mode only. * Intel SGX, due to random crashes in soc/intel/common For more details have a look at the documentation. Please apply those patches as well for good user experience: Ica0c20255f661dd61edc3a7d15646b7447c4658e Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Signed-off-by: Felix Singer <felix.singer(a)9elements.com> Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 --- M Documentation/mainboard/index.md A Documentation/mainboard/supermicro/x11ssh-tf.md A Documentation/mainboard/supermicro/x11ssh_flash.jpg A src/mainboard/supermicro/x11ssh/Kconfig A src/mainboard/supermicro/x11ssh/Kconfig.name A src/mainboard/supermicro/x11ssh/Makefile.inc A src/mainboard/supermicro/x11ssh/acpi/ec.asl A src/mainboard/supermicro/x11ssh/acpi/mainboard.asl A src/mainboard/supermicro/x11ssh/acpi/superio.asl A src/mainboard/supermicro/x11ssh/acpi_tables.c A src/mainboard/supermicro/x11ssh/board_info.txt A src/mainboard/supermicro/x11ssh/bootblock.c A src/mainboard/supermicro/x11ssh/cmos.layout A src/mainboard/supermicro/x11ssh/dsdt.asl A src/mainboard/supermicro/x11ssh/gpio.h A src/mainboard/supermicro/x11ssh/ramstage.c A src/mainboard/supermicro/x11ssh/romstage.c A src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt A src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb A src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd 20 files changed, 989 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/32734/81 -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 81 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/common/timer: Make TSC frequency calculation dynamically
by Subrata Banik (Code Review) 31 Aug '19

31 Aug '19

Hello Aaron Durbin, Patrick Rudolph, Meera Ravindranath, Lean Sheng Tan, Aamir Bohra, Wonkyu Kim, Maulik V Vaghela, Duncan Laurie, V Sowmya, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35148 to look at the new patch set (#9). Change subject: soc/intel/common/timer: Make TSC frequency calculation dynamically ...................................................................... soc/intel/common/timer: Make TSC frequency calculation dynamically tsc_freq_mhz() had a static table of Intel CPU families and crystal clock, but it is possible to calculate the crystal clock speed dynamically, and this is preferred over hardcoded table. Recommendation is to make use of CPUID.16h where crystal clock frequency was not reported by CPUID.15h to calculate the crystal clock. On SKL/KBL/CML CPUID.15h.ecx = nominal core crystal clock = 0 Hz hence we had to use static table to calculate crystal clock. BUG=b:139798422, b:129839774 TEST=Able to build and boot KBL/CML/ICL. Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- D src/arch/x86/include/arch/intel-family.h M src/soc/intel/common/block/timer/timer.c 2 files changed, 77 insertions(+), 117 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/35148/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/35148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Gerrit-Change-Number: 35148 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/common/timer: Make TSC frequency calculation dynamically
by Subrata Banik (Code Review) 31 Aug '19

31 Aug '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35148 ) Change subject: soc/intel/common/timer: Make TSC frequency calculation dynamically ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/35148/8/src/soc/intel/common/block… File src/soc/intel/common/block/timer/timer.c: https://review.coreboot.org/c/coreboot/+/35148/8/src/soc/intel/common/block… PS8, Line 68: > I am thinking if this function would be more clear if split into multiple functions: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Gerrit-Change-Number: 35148 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sat, 31 Aug 2019 16:07:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit August 2019