coreboot-gerrit August 2019

coreboot-gerrit@coreboot.org

1 participants
1942 discussions

Change in coreboot[master]: arch/x86: Make X86 stages select ARCH_X86
by David Guckian (Code Review) 31 Aug '19

31 Aug '19

David Guckian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31316 ) Change subject: arch/x86: Make X86 stages select ARCH_X86 ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/31316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic77b696f493d7648f317f0ba0a27fdee5212961e Gerrit-Change-Number: 31316 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 31 Aug 2019 12:07:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Add Razer Blade Stealth (2016) H2U
by Mimoja (Code Review) 31 Aug '19

31 Aug '19

Mimoja has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34475 ) Change subject: Add Razer Blade Stealth (2016) H2U ...................................................................... Patch Set 33: (5 comments) https://review.coreboot.org/c/coreboot/+/34475/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/34475/6//COMMIT_MSG@16 PS6, Line 16: - BUG: Dmesg: ioapic 2 has no mapping iommu, interrupt remapping will be disabled > Thanks. […] Not a board specific problem. https://review.coreboot.org/c/coreboot/+/34475/7//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/34475/7//COMMIT_MSG@41 PS7, Line 41: - Headphones > Yes - most likely. Did not have the time to look into it so far. Done https://review.coreboot.org/c/coreboot/+/34475/9//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/34475/9//COMMIT_MSG@46 PS9, Line 46: - > Didn't look into it so far. […] No it is not (only). I would need to debug the USB-PD handshake and partially reverse the EC firmware to understand the magic values the ACPI is 'writing' to it. When connected at boot, devices show up on PCIe, I would consider that usable. Waking the chip up does not work. https://review.coreboot.org/c/coreboot/+/34475/16//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/34475/16//COMMIT_MSG@46 PS16, Line 46: - Onboard Keyboard in SeaBIOS > Do you have a debug log? Does the GRUB payload work correctly? Done https://review.coreboot.org/c/coreboot/+/34475/28/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_kbl/gma-mainboard.ads: https://review.coreboot.org/c/coreboot/+/34475/28/src/mainboard/razer/blade… PS28, Line 25: DP1, : DP2, > Try adding 'HDMI2, HDMI3,' to see if it helps with your HDMI issues The HDMI is connected to the DP-1 Port via a conversion Chip.. It works, when plugged at boot. -- To view, visit https://review.coreboot.org/c/coreboot/+/34475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Gerrit-Change-Number: 34475 Gerrit-PatchSet: 33 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 31 Aug 2019 09:14:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alexander Couzens <lynxis(a)fe80.eu> Comment-In-Reply-To: Mimoja <coreboot(a)mimoja.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: Add Razer Blade Stealth (2016) H2U
by build bot (Jenkins) (Code Review) 31 Aug '19

31 Aug '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34475 ) Change subject: Add Razer Blade Stealth (2016) H2U ...................................................................... Patch Set 33: (2 comments) https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c: https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… PS33, Line 26: {0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00}}; space required after that close brace '}' https://review.coreboot.org/c/coreboot/+/34475/33/src/mainboard/razer/blade… PS33, Line 33: const u8 dqs_map[2][8] = {{0, 1, 3, 2, 4, 5, 6, 7}, {1, 0, 4, 5, 2, 3, 6, 7}}; space required after that close brace '}' -- To view, visit https://review.coreboot.org/c/coreboot/+/34475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Gerrit-Change-Number: 34475 Gerrit-PatchSet: 33 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 31 Aug 2019 09:01:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Add Razer Blade Stealth (2016) H2U
by Mimoja (Code Review) 31 Aug '19

31 Aug '19

Hello Alexander Couzens, Christoph Pomaska, Angel Pons, Jonathan Neuschäfer, Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34475 to look at the new patch set (#33). Change subject: Add Razer Blade Stealth (2016) H2U ...................................................................... Add Razer Blade Stealth (2016) H2U The Razer Blade Stealth H2U is a KabyLake System using: - Intel KBL 7500U - ITE8528E SuperIO - Intel 600P Series NVMe SSD - Either four MT52L1G32D4PG (16GB) or MT52L512MB32D4PG (8GB) of soldered memory in dualchannel mode - (Optional) Touchscreen Even tho it has a 16MB chip equipped (W25Q128.V) only the first 8MB are used and mapped. The rest should be left empty (0xFF) The flash is not secured in any way and can be read via flashrom. It should be the source for this ports IFD and ME blobs. Working: - USB-A Ports left and right - Speakers - Touchscreen (USB) - Onboard Keyboard in Linux - NVMe SSD - SeaBIOS, Tianocore and Grub Payloads - Webcam - Powersaving Modes - Battery state and LID switch - Touchpad (I2C) - Headphones Not going to implement: - Thunderbolt (Requires EC out of band signaling) - HDMI (Connected to DP-1 via conversion chip. Currently requires plugged connection at boot) Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> --- A src/mainboard/razer/Kconfig A src/mainboard/razer/Kconfig.name A src/mainboard/razer/blade_stealth_kbl/Kconfig A src/mainboard/razer/blade_stealth_kbl/Kconfig.name A src/mainboard/razer/blade_stealth_kbl/Makefile.inc A src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl A src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl A src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl A src/mainboard/razer/blade_stealth_kbl/acpi/mainboard.asl A src/mainboard/razer/blade_stealth_kbl/acpi/superio.asl A src/mainboard/razer/blade_stealth_kbl/acpi_tables.c A src/mainboard/razer/blade_stealth_kbl/board_info.txt A src/mainboard/razer/blade_stealth_kbl/devicetree.cb A src/mainboard/razer/blade_stealth_kbl/dsdt.asl A src/mainboard/razer/blade_stealth_kbl/gma-mainboard.ads A src/mainboard/razer/blade_stealth_kbl/gpio.h A src/mainboard/razer/blade_stealth_kbl/hda_verb.c A src/mainboard/razer/blade_stealth_kbl/mainboard.c A src/mainboard/razer/blade_stealth_kbl/ramstage.c A src/mainboard/razer/blade_stealth_kbl/romstage.c A src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc A src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex A src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex A src/mainboard/razer/blade_stealth_kbl/spd/spd.h A src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c 25 files changed, 1,341 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/34475/33 -- To view, visit https://review.coreboot.org/c/coreboot/+/34475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Gerrit-Change-Number: 34475 Gerrit-PatchSet: 33 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Add Razer Blade Stealth (2016) H2U
by build bot (Jenkins) (Code Review) 31 Aug '19

31 Aug '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34475 ) Change subject: Add Razer Blade Stealth (2016) H2U ...................................................................... Patch Set 32: (2 comments) https://review.coreboot.org/c/coreboot/+/34475/32/src/mainboard/razer/blade… File src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c: https://review.coreboot.org/c/coreboot/+/34475/32/src/mainboard/razer/blade… PS32, Line 26: {0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00}}; space required after that close brace '}' https://review.coreboot.org/c/coreboot/+/34475/32/src/mainboard/razer/blade… PS32, Line 33: const u8 dqs_map[2][8] = {{0, 1, 3, 2, 4, 5, 6, 7}, {1, 0, 4, 5, 2, 3, 6, 7}}; space required after that close brace '}' -- To view, visit https://review.coreboot.org/c/coreboot/+/34475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Gerrit-Change-Number: 34475 Gerrit-PatchSet: 32 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 31 Aug 2019 08:52:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Add Razer Blade Stealth (2016) H2U
by Mimoja (Code Review) 31 Aug '19

31 Aug '19

Hello Alexander Couzens, Christoph Pomaska, Angel Pons, Jonathan Neuschäfer, Felix Singer, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34475 to look at the new patch set (#32). Change subject: Add Razer Blade Stealth (2016) H2U ...................................................................... Add Razer Blade Stealth (2016) H2U The Razer Blade Stealth H2U is a KabyLake System using: - Intel KBL 7500U - ITE8528E SuperIO - Intel 600P Series NVMe SSD - Either four MT52L1G32D4PG (16GB) or MT52L512MB32D4PG (8GB) of soldered memory in dualchannel mode - (Optional) Touchscreen Even tho it has a 16MB chip equipped (W25Q128.V) only the first 8MB are used and mapped. The rest should be left empty (0xFF) The flash is not secured in any way and can be read via flashrom. It should be the source for this ports IFD and ME blobs. Working: - USB-A Ports left and right - Speakers - Touchscreen (USB) - Onboard Keyboard in Linux - NVMe SSD - SeaBIOS, Tianocore and Grub Payloads - Webcam - Powersaving Modes - Battery state and LID switch - Touchpad (I2C) - Headphones Not going to implement: - Thunderbolt (Requires EC out of band signaling) - HDMI (Connected to DP-1 via conversion chip. Currently requires plugged connection at boot) Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> --- A src/mainboard/razer/Kconfig A src/mainboard/razer/Kconfig.name A src/mainboard/razer/blade_stealth_kbl/Kconfig A src/mainboard/razer/blade_stealth_kbl/Kconfig.name A src/mainboard/razer/blade_stealth_kbl/Makefile.inc A src/mainboard/razer/blade_stealth_kbl/acpi/ac.asl A src/mainboard/razer/blade_stealth_kbl/acpi/battery.asl A src/mainboard/razer/blade_stealth_kbl/acpi/ec.asl A src/mainboard/razer/blade_stealth_kbl/acpi/mainboard.asl A src/mainboard/razer/blade_stealth_kbl/acpi/superio.asl A src/mainboard/razer/blade_stealth_kbl/acpi_tables.c A src/mainboard/razer/blade_stealth_kbl/board_info.txt A src/mainboard/razer/blade_stealth_kbl/devicetree.cb A src/mainboard/razer/blade_stealth_kbl/dsdt.asl A src/mainboard/razer/blade_stealth_kbl/gma-mainboard.ads A src/mainboard/razer/blade_stealth_kbl/gpio.h A src/mainboard/razer/blade_stealth_kbl/hda_verb.c A src/mainboard/razer/blade_stealth_kbl/mainboard.c A src/mainboard/razer/blade_stealth_kbl/ramstage.c A src/mainboard/razer/blade_stealth_kbl/romstage.c A src/mainboard/razer/blade_stealth_kbl/spd/Makefile.inc A src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex A src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex A src/mainboard/razer/blade_stealth_kbl/spd/spd.h A src/mainboard/razer/blade_stealth_kbl/spd/spd_util.c 25 files changed, 1,339 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/34475/32 -- To view, visit https://review.coreboot.org/c/coreboot/+/34475 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350 Gerrit-Change-Number: 34475 Gerrit-PatchSet: 32 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/timer: Make TSC frequency calculation dynamically
by Furquan Shaikh (Code Review) 31 Aug '19

31 Aug '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35148 ) Change subject: soc/intel/common/timer: Make TSC frequency calculation dynamically ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/35148/8/src/soc/intel/common/block… File src/soc/intel/common/block/timer/timer.c: https://review.coreboot.org/c/coreboot/+/35148/8/src/soc/intel/common/block… PS8, Line 68: I am thinking if this function would be more clear if split into multiple functions: static void get_hardcoded_crystal_freq(void) { ... switch (get_processor_model()) { case CPU_MODEL_INTEL_ATOM_DENVERTON: core_crystal_nominal_freq_khz = 25000; break; } return core_crystal_nominal_freq_khz; } static unsigned long calculate_tsc_freq_from_core_crystal(void) { ... if (get_max_cpuid_func() < 0x15) return 0; cpuidr_15h = cpuid(0x15); ... if (!core_crystal_nominal_freq_khz) core_crystal_nominal_freq_khz = get_hardcoded_crystal_freq(); return (core_crystal_nominal_freq_khz * cpuidr_15h.ebx / cpuidr_15h.eax) / 1000; } static unsigned long get_freq_from_cpuid16h(void) { if (get_max_cpuid_func() < 0x15) return 0; return cpuid_eax(0x16); } unsigned long tsc_freq_mhz(void) { unsigned long tsc_freq; tsc_freq = calculate_tsc_freq_from_core_crystal(); if (tsc_freq) return tsc_freq; return get_freq_from_cpuid16h(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Gerrit-Change-Number: 35148 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Sat, 31 Aug 2019 07:32:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: arch/ppc64: add initial isav300 stubs
by Marty E. Plummer (Code Review) 31 Aug '19

31 Aug '19

Marty E. Plummer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35183 ) Change subject: arch/ppc64: add initial isav300 stubs ...................................................................... arch/ppc64: add initial isav300 stubs Change-Id: Ice269fff6859b4c70ec6693cd2e458a48cafba69 Signed-off-by: Marty E. Plummer <hanetzer(a)startmail.com> --- M src/arch/ppc64/Kconfig M src/arch/ppc64/Makefile.inc A src/arch/ppc64/isav300/Kconfig A src/arch/ppc64/isav300/Makefile.inc M src/soc/ibm/power9/Kconfig 5 files changed, 38 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/35183/1 diff --git a/src/arch/ppc64/Kconfig b/src/arch/ppc64/Kconfig index 6d43f79..497510c 100644 --- a/src/arch/ppc64/Kconfig +++ b/src/arch/ppc64/Kconfig @@ -20,6 +20,7 @@ select ARCH_PPC64 source "src/arch/ppc64/power8/Kconfig" +source "src/arch/ppc64/isav300/Kconfig" config PPC64_USE_ARCH_TIMER bool diff --git a/src/arch/ppc64/Makefile.inc b/src/arch/ppc64/Makefile.inc index d6f0b77..4ced3f8 100644 --- a/src/arch/ppc64/Makefile.inc +++ b/src/arch/ppc64/Makefile.inc @@ -20,7 +20,7 @@ ## Take care of subdirectories ################################################################################ -subdirs-y += power8/ +subdirs-y += power8/ isav300/ ################################################################################ ## bootblock diff --git a/src/arch/ppc64/isav300/Kconfig b/src/arch/ppc64/isav300/Kconfig new file mode 100644 index 0000000..1ab7b20 --- /dev/null +++ b/src/arch/ppc64/isav300/Kconfig @@ -0,0 +1,15 @@ +config ARCH_BOOTBLOCK_PPC64_ISAV300 + def_bool n + select ARCH_BOOTBLOCK_PPC64 + +config ARCH_VERSTAGE_PPC64_ISAV300 + def_bool n + select ARCH_VERSTAGE_PPC64 + +config ARCH_ROMSTAGE_PPC64_ISAV300 + def_bool n + select ARCH_ROMSTAGE_PPC64 + +config ARCH_RAMSTAGE_PPC64_ISAV300 + def_bool n + select ARCH_RAMSTAGE_PPC64 diff --git a/src/arch/ppc64/isav300/Makefile.inc b/src/arch/ppc64/isav300/Makefile.inc new file mode 100644 index 0000000..6e24d9a --- /dev/null +++ b/src/arch/ppc64/isav300/Makefile.inc @@ -0,0 +1,17 @@ +ppc64_flags += -mcpu=power9 -mtune=power9 + +################################################################################ +## bootblock +################################################################################ +ifeq ($(CONFIG_ARCH_BOOTBLOCK_PPC64_ISAV300),y) + +endif # CONFIG_ARCH_BOOTBLOCK_PPC64_ISAV300 + +################################################################################ +## ramstage +################################################################################ +ifeq ($(CONFIG_ARCH_RAMSTAGE_PPC64_ISAV300),y) + +$(eval $(call create_class_compiler,rmodules,power9)) + +endif # CONFIG_ARCH_RAMSTAGE_PPC64_ISAV300 diff --git a/src/soc/ibm/power9/Kconfig b/src/soc/ibm/power9/Kconfig index 5bb2ec0..095fc69 100644 --- a/src/soc/ibm/power9/Kconfig +++ b/src/soc/ibm/power9/Kconfig @@ -1,4 +1,8 @@ config SOC_IBM_POWER9 bool default n + select ARCH_BOOTBLOCK_PPC64_ISAV300 + select ARCH_ROMSTAGE_PPC64_ISAV300 + select ARCH_RAMSTAGE_PPC64_ISAV300 + select ARCH_VERSTAGE_PPC64_ISAV300 select PPC64_USE_ARCH_TIMER -- To view, visit https://review.coreboot.org/c/coreboot/+/35183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice269fff6859b4c70ec6693cd2e458a48cafba69 Gerrit-Change-Number: 35183 Gerrit-PatchSet: 1 Gerrit-Owner: Marty E. Plummer <hanetzer(a)startmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ibm/nimbus: initial stub directory tree
by Marty E. Plummer (Code Review) 31 Aug '19

31 Aug '19

Marty E. Plummer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35182 ) Change subject: ibm/nimbus: initial stub directory tree ...................................................................... ibm/nimbus: initial stub directory tree The power9 subdirectory is code which would be common to nimbus, cumulus, and axone processors. Change-Id: Iae87da6ad47226e67d7a0944ec878e34f1d3904d Signed-off-by: Marty E. Plummer <hanetzer(a)startmail.com> --- A src/soc/ibm/Kconfig A src/soc/ibm/nimbus/Kconfig A src/soc/ibm/nimbus/Makefile.inc A src/soc/ibm/power9/Kconfig A src/soc/ibm/power9/include/soc/memlayout.ld 5 files changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/35182/1 diff --git a/src/soc/ibm/Kconfig b/src/soc/ibm/Kconfig new file mode 100644 index 0000000..3e84cf2 --- /dev/null +++ b/src/soc/ibm/Kconfig @@ -0,0 +1,2 @@ +# Load all chipsets +source "src/soc/ibm/*/Kconfig" diff --git a/src/soc/ibm/nimbus/Kconfig b/src/soc/ibm/nimbus/Kconfig new file mode 100644 index 0000000..c5dd6a3 --- /dev/null +++ b/src/soc/ibm/nimbus/Kconfig @@ -0,0 +1,4 @@ +config SOC_IBM_NIMBUS + bool + default n + select SOC_IBM_POWER9 diff --git a/src/soc/ibm/nimbus/Makefile.inc b/src/soc/ibm/nimbus/Makefile.inc new file mode 100644 index 0000000..06c7a67 --- /dev/null +++ b/src/soc/ibm/nimbus/Makefile.inc @@ -0,0 +1,6 @@ +ifeq ($(CONFIG_SOC_IBM_NIMBUS),y) + +CPPFLAGS_common += -I$(src)/soc/ibm/nimbus/include +CPPFLAGS_common += -I$(src)/soc/ibm/power9/include + +endif diff --git a/src/soc/ibm/power9/Kconfig b/src/soc/ibm/power9/Kconfig new file mode 100644 index 0000000..3a41939 --- /dev/null +++ b/src/soc/ibm/power9/Kconfig @@ -0,0 +1,8 @@ +config SOC_IBM_POWER9 + bool + default n + select ARCH_BOOTBLOCK_PPC64_ISAV300 + select ARCH_RAMSTAGE_PPC64_ISAV300 + select ARCH_ROMSTAGE_PPC64_ISAV300 + select ARCH_VERSTAGE_PPC64_ISAV300 + select PPC64_USE_ARCH_TIMER diff --git a/src/soc/ibm/power9/include/soc/memlayout.ld b/src/soc/ibm/power9/include/soc/memlayout.ld new file mode 100644 index 0000000..13fb1cb --- /dev/null +++ b/src/soc/ibm/power9/include/soc/memlayout.ld @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <memlayout.h> +#include <arch/header.ld> + +SECTIONS +{ + DRAM_START(0x00000000) + BOOTBLOCK(0x0, 64K) + ROMSTAGE(0x20000, 128K) + STACK(0x40000, 0x3ff00) + RAMSTAGE(0x100000, 16M) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae87da6ad47226e67d7a0944ec878e34f1d3904d Gerrit-Change-Number: 35182 Gerrit-PatchSet: 1 Gerrit-Owner: Marty E. Plummer <hanetzer(a)startmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86: Remove WB attribute from 0..CACHE_TMP_RAMTOP
by Kyösti Mälkki (Code Review) 31 Aug '19

31 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35161 ) Change subject: arch/x86: Remove WB attribute from 0..CACHE_TMP_RAMTOP ...................................................................... arch/x86: Remove WB attribute from 0..CACHE_TMP_RAMTOP Platforms using postcar are with RELOCATABLE_RAMSTAGE=y. They don't benefit from having low-memory set as writeback-cacheable. This also fixes regression from CB:34893 that caused some random hangs with more recent intel SoCs in ramstage. Change-Id: Ia66910a6c85286f5c05823b87d48edc7e4ad9541 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/postcar_loader.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/35161/1 diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 6a7d389..61a9d52 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -125,9 +125,6 @@ if (pcf->skip_common_mtrr) return; - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(pcf, MTRR_TYPE_WRPROT); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia66910a6c85286f5c05823b87d48edc7e4ad9541 Gerrit-Change-Number: 35161 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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