coreboot-gerrit August 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[4.10_branch]: drivers/fsp1_1/raminit: fix use of mrc_hob
by Patrick Georgi (Code Review) 30 Aug '19

30 Aug '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/35047 ) Change subject: drivers/fsp1_1/raminit: fix use of mrc_hob ...................................................................... drivers/fsp1_1/raminit: fix use of mrc_hob Commit 509f469 [drivers/fsp1_1/raminit.c: Always check FSP HOBs] inadvertently made use of the mrc_hob conditional on CONFIG_DISPLAY_HOBS, when there is no relation between the two, leading to MRC cache data being corrupted. On some devices this caused RAM training to be redone, on others it resulted in a bricked device. Fix this by removing the condition on CONFIG_DISPLAY_HOBS. Test: boot google/{cyan,edgar}, observe third boot and onward do not brick device, properly use mrc_hob via cbmem console and timestamps. Change-Id: I01f6d1d6dfd10297b30de638301c5e0b6545da9c Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34685 Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> (cherry picked from commit 4183312cec55f00fe22c4dbfd682376e521fc6d3) Reviewed-on: https://review.coreboot.org/c/coreboot/+/35047 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/drivers/intel/fsp1_1/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index e71c9a2..21f4ab9 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -259,7 +259,7 @@ /* Locate the memory configuration data to speed up the next reboot */ mrc_hob = get_next_guid_hob(&mrc_guid, hob_list_ptr); - if ((mrc_hob == NULL) && CONFIG(DISPLAY_HOBS)) + if (mrc_hob == NULL) printk(BIOS_DEBUG, "Memory Configuration Data Hob not present\n"); else if (!vboot_recovery_mode_enabled()) { -- To view, visit https://review.coreboot.org/c/coreboot/+/35047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.10_branch Gerrit-Change-Id: I01f6d1d6dfd10297b30de638301c5e0b6545da9c Gerrit-Change-Number: 35047 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[4.10_branch]: mb/purism/librem_skl: use SOC_INTEL_COMMON_BLOCK_HDA_VERB
by Patrick Georgi (Code Review) 30 Aug '19

30 Aug '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35048 ) Change subject: mb/purism/librem_skl: use SOC_INTEL_COMMON_BLOCK_HDA_VERB ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.10_branch Gerrit-Change-Id: I2fd5363aad027f215f93964bc6a85f00fea86c88 Gerrit-Change-Number: 35048 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Aug 2019 10:44:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[4.10_branch]: drivers/fsp1_1/raminit: fix use of mrc_hob
by Patrick Georgi (Code Review) 30 Aug '19

30 Aug '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35047 ) Change subject: drivers/fsp1_1/raminit: fix use of mrc_hob ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.10_branch Gerrit-Change-Id: I01f6d1d6dfd10297b30de638301c5e0b6545da9c Gerrit-Change-Number: 35047 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Aug 2019 10:44:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ipq40xx: Increase CBFS and RAMSTAGE size.
by Patrick Georgi (Code Review) 30 Aug '19

30 Aug '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35134 ) Change subject: ipq40xx: Increase CBFS and RAMSTAGE size. ...................................................................... ipq40xx: Increase CBFS and RAMSTAGE size. Increase CBFS and RAMSTAGE size to accommodate larger binary component. BUG=b:77641795 TEST=Build and test on Gale. BRANCH=none Change-Id: I25f7121221ab2bb66dfedbc4a66e06976d88cef5 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: e4d3d2d078d0a8f705afe2b6c741118727614bf0 Original-Change-Id: I6ad16c0073a683cb66d5ae8a46b8990f3346f183 Original-Signed-off-by: Kan Yan <kyan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/1366388 Original-Reviewed-by: Zhihong Yu <zhihongyu(a)chromium.org> --- M src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/35134/1 diff --git a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld index a69b60b..f1a7bc5 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld +++ b/src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld @@ -58,7 +58,7 @@ DRAM_START(0x80000000) SYMBOL(memlayout_cbmem_top, 0x87280000) - POSTRAM_CBFS_CACHE(0x87280000, 384K) - RAMSTAGE(0x872e0000, 128K) - DMA_COHERENT(0x87300000, 2M) + POSTRAM_CBFS_CACHE(0x87280000, 512K) + RAMSTAGE(0x87300000, 512K) + DMA_COHERENT(0x87400000, 2M) } -- To view, visit https://review.coreboot.org/c/coreboot/+/35134 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25f7121221ab2bb66dfedbc4a66e06976d88cef5 Gerrit-Change-Number: 35134 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[4.10_branch]: soc/intel/fsp_broadwell_de: Fix use of config_of()
by Patrick Georgi (Code Review) 30 Aug '19

30 Aug '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/35045 ) Change subject: soc/intel/fsp_broadwell_de: Fix use of config_of() ...................................................................... soc/intel/fsp_broadwell_de: Fix use of config_of() Change-Id: I96d423720fbe67c067373436ad250edf37939e99 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34547 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> (cherry picked from commit c9c80c69073bb2677b0b2e58b60fcf93822cb2c7) Reviewed-on: https://review.coreboot.org/c/coreboot/+/35045 Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/fsp_broadwell_de/iou_complto.c 1 file changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/fsp_broadwell_de/iou_complto.c b/src/soc/intel/fsp_broadwell_de/iou_complto.c index c50cbb4..f998d97 100644 --- a/src/soc/intel/fsp_broadwell_de/iou_complto.c +++ b/src/soc/intel/fsp_broadwell_de/iou_complto.c @@ -17,12 +17,14 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <soc/intel/fsp_broadwell_de/chip.h> +#include <soc/pci_devs.h> #define DEVCTL2 0xb8 static void iou_init(struct device *dev) { - const config_t *config = config_of(dev); + /* Use config from device always present in static devicetree. */ + const config_t *config = config_of_path(SOC_DEV_FUNC); u16 devctl2; /* pcie completion timeout -- To view, visit https://review.coreboot.org/c/coreboot/+/35045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.10_branch Gerrit-Change-Id: I96d423720fbe67c067373436ad250edf37939e99 Gerrit-Change-Number: 35045 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[4.10_branch]: google/link: fix detection of dimm on channel 1
by Patrick Georgi (Code Review) 30 Aug '19

30 Aug '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/35046 ) Change subject: google/link: fix detection of dimm on channel 1 ...................................................................... google/link: fix detection of dimm on channel 1 Changes to the sandybridge memory init code (both MRC and native) now require SPD data on all populated channels in order for dimms to be detected properly, so copy spd_data[0] to spd_data[2], as LINK always has 2 channels of memory down. Test: boot google/link, observe onboard RAM correctly detected on both channels Change-Id: Id01d57d5e5f928dfc1cd9063ab1625c440ef2bbe Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35084 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> (cherry picked from commit 4af1fe23f8658ec51380b68ecdd317ddc1dfb854) Reviewed-on: https://review.coreboot.org/c/coreboot/+/35046 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/link/romstage.c 1 file changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 2f3f07c..8e8d943 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -156,8 +156,12 @@ }, }; *pei_data = pei_data_template; + /* LINK has 2 channels of memory down, so spd_data[0] and [2] + both need to be populated */ memcpy(pei_data->spd_data[0], locate_spd(), sizeof(pei_data->spd_data[0])); + memcpy(pei_data->spd_data[2], pei_data->spd_data[0], + sizeof(pei_data->spd_data[0])); } const struct southbridge_usb_port mainboard_usb_ports[] = { @@ -180,7 +184,10 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) { + /* LINK has 2 channels of memory down, so spd_data[0] and [2] + both need to be populated */ memcpy(&spd[0], locate_spd(), 128); + memcpy(&spd[2], &spd[0], 128); } void mainboard_early_init(int s3resume) -- To view, visit https://review.coreboot.org/c/coreboot/+/35046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.10_branch Gerrit-Change-Id: Id01d57d5e5f928dfc1cd9063ab1625c440ef2bbe Gerrit-Change-Number: 35046 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Kconfig: Write tmp files into same directory as target files
by Raul Rangel (Code Review) 30 Aug '19

30 Aug '19

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34244 ) Change subject: Kconfig: Write tmp files into same directory as target files ...................................................................... Kconfig: Write tmp files into same directory as target files This removes the need for COREBOOT_BUILD_DIR in Kconfig. Since the original files will be replaced with the tmp file, the parent directory already needs to be writable. Before this change, the tmp files would be created in the CWD (src) if COREBOOT_BUILD_DIR was not specified. BUG=b:112267918 TEST=emerge-grunt coreboot and verified no tmp files were created in the src directory. Change-Id: Icdaf2ff3dd1ec98813b75ef55b96e38e1ca19ec7 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M Documentation/getting_started/kconfig.md M util/kconfig/confdata.c 2 files changed, 65 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/34244/1 diff --git a/Documentation/getting_started/kconfig.md b/Documentation/getting_started/kconfig.md index 852ca08..ecdfe62 100644 --- a/Documentation/getting_started/kconfig.md +++ b/Documentation/getting_started/kconfig.md @@ -73,9 +73,6 @@ These variables were added to Kconfig specifically for coreboot and are not included in the Linux version. -- COREBOOT_BUILD_DIR=path for temporary files. This is used by coreboot’s - abuild tool. - - KCONFIG_STRICT=value. Define to enable warnings as errors. This is enabled in coreboot, and should not be changed. diff --git a/util/kconfig/confdata.c b/util/kconfig/confdata.c index 88a65e3..0c4ddcf 100644 --- a/util/kconfig/confdata.c +++ b/util/kconfig/confdata.c @@ -764,6 +764,16 @@ return 0; } + +int conf_mktemp(const char *path, char *tmpfile) +{ + if (snprintf(tmpfile, PATH_MAX, "%s.tmp.XXXXXX", path) >= PATH_MAX) { + errno = EOVERFLOW; + return -1; + } + return mkstemp(tmpfile); +} + int conf_write(const char *name) { FILE *out; @@ -805,9 +815,11 @@ sprintf(newname, "%s%s", dirname, basename); env = getenv("KCONFIG_OVERWRITECONFIG"); if (!env || !*env) { - sprintf(tmpname, "%s.tmpconfig.%d", dirname, (int)getpid()); + conf_mktemp(newname, tmpname); + fprintf(stderr, _("\n*** USING TEMP CONFIG: %s\n\n"), tmpname); out = fopen(tmpname, "w"); } else { + fprintf(stderr, _("\n*** NOT USING TEMP CONFIG\n\n")); *tmpname = 0; out = fopen(newname, "w"); } @@ -990,7 +1002,6 @@ int conf_write_autoconf(void) { struct symbol *sym; - const char *name; FILE *out, *tristate, *out_h; int i; int print_negatives; @@ -1007,49 +1018,41 @@ if (conf_split_config()) return 1; - char *tmpconfig_name = malloc(PATH_MAX); - if (getenv("COREBOOT_BUILD_DIR")) { - sprintf(tmpconfig_name, "%s/.tmpconfig.XXXXXX", - getenv("COREBOOT_BUILD_DIR")); - } else { - tmpconfig_name = strdup(".tmpconfig.XXXXXX"); - } - if ((i = mkstemp(tmpconfig_name)) == -1) - return 1; + char tmpconfig_name[PATH_MAX]; + const char *config_name = conf_get_autoconfig_name(); + + i = conf_mktemp(config_name, tmpconfig_name); + if (i == -1) + goto error_auto_conf_cmd_tmp; out = fdopen(i, "w"); if (!out) - return 1; + goto error_auto_conf_cmd_open; - char *tmpconfig_triname = malloc(PATH_MAX); - if (getenv("COREBOOT_BUILD_DIR")) { - sprintf(tmpconfig_triname, "%s/.tmpconfig_tristate.XXXXXX", - getenv("COREBOOT_BUILD_DIR")); - } else { - tmpconfig_triname = strdup(".tmpconfig_tristate.XXXXXX"); - } - if ((i = mkstemp(tmpconfig_triname)) == -1) - return 1; + char tmpconfig_triname[PATH_MAX]; + const char *config_triname = getenv("KCONFIG_TRISTATE"); + if (!config_triname) + config_triname = "include/config/tristate.conf"; + + i = conf_mktemp(config_triname, tmpconfig_triname); + if (i == -1) + goto error_tristate_tmp; + tristate = fdopen(i, "w"); - if (!tristate) { - fclose(out); - return 1; - } + if (!tristate) + goto error_tristate_open; - char *tmpconfig_h = malloc(PATH_MAX); - if (getenv("COREBOOT_BUILD_DIR")) { - sprintf(tmpconfig_h, "%s/.tmpconfig_tristate.XXXXXX", - getenv("COREBOOT_BUILD_DIR")); - } else { - tmpconfig_h = strdup(".tmpconfig_tristate.XXXXXX"); - } - if ((i = mkstemp(tmpconfig_h)) == -1) - return 1; + char tmpconfig_h[PATH_MAX]; + const char *config_h = getenv("KCONFIG_AUTOHEADER"); + if (!config_h) + config_h = "include/generated/autoconf.h"; + + i = conf_mktemp(config_h, tmpconfig_h); + if (i == -1) + goto error_auto_conf_h_tmp; + out_h = fdopen(i, "w"); - if (!out_h) { - fclose(out); - fclose(tristate); - return 1; - } + if (!out_h) + goto error_auto_conf_h_open; conf_write_heading(out, &kconfig_printer_cb, NULL); @@ -1083,25 +1086,38 @@ fclose(tristate); fclose(out_h); - name = getenv("KCONFIG_AUTOHEADER"); - if (!name) - name = "include/generated/autoconf.h"; - if (rename(tmpconfig_h, name)) + if (rename(tmpconfig_h, config_h)) return 1; - name = getenv("KCONFIG_TRISTATE"); - if (!name) - name = "include/config/tristate.conf"; - if (rename(tmpconfig_triname, name)) + + if (rename(tmpconfig_triname, config_triname)) return 1; - name = conf_get_autoconfig_name(); + /* * This must be the last step, kbuild has a dependency on auto.conf * and this marks the successful completion of the previous steps. */ - if (rename(tmpconfig_name, name)) + if (rename(tmpconfig_name, config_name)) return 1; return 0; + +error_auto_conf_h_open: + unlink(tmpconfig_h); + +error_auto_conf_h_tmp: + fclose(tristate); + +error_tristate_open: + unlink(tmpconfig_triname); + +error_tristate_tmp: + fclose(out); + +error_auto_conf_cmd_open: + unlink(tmpconfig_name); + +error_auto_conf_cmd_tmp: + return 1; } static int sym_change_count; -- To view, visit https://review.coreboot.org/c/coreboot/+/34244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdaf2ff3dd1ec98813b75ef55b96e38e1ca19ec7 Gerrit-Change-Number: 34244 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: kconfig: Use config's full path when generating tmp file
by Raul Rangel (Code Review) 30 Aug '19

30 Aug '19

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34243 ) Change subject: kconfig: Use config's full path when generating tmp file ...................................................................... kconfig: Use config's full path when generating tmp file If KCONFIG_CONFIG is set to a full path, we should generate the tmp file in the same directory instead of the current working directory. BUG=b:112267918 TEST=emerge-grunt coreboot and verified with print statements that the correct path was used. Change-Id: Ia21e930a9b0a693f851c34bcde26b34886cbe902 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M util/kconfig/confdata.c 1 file changed, 11 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/34243/1 diff --git a/util/kconfig/confdata.c b/util/kconfig/confdata.c index fc4a07a..88a65e3 100644 --- a/util/kconfig/confdata.c +++ b/util/kconfig/confdata.c @@ -769,7 +769,7 @@ FILE *out; struct symbol *sym; struct menu *menu; - const char *basename; + const char *basename = NULL; const char *str; char dirname[PATH_MAX+1], tmpname[PATH_MAX+1], newname[PATH_MAX+1]; char *env; @@ -777,13 +777,20 @@ dirname[0] = 0; if (name && name[0]) { struct stat st; - char *slash; if (!stat(name, &st) && S_ISDIR(st.st_mode)) { strcpy(dirname, name); strcat(dirname, "/"); basename = conf_get_configname(); - } else if ((slash = strrchr(name, '/'))) { + } + } else { + name = conf_get_configname(); + } + + if (!basename) { + char *slash = strrchr(name, '/'); + + if (slash) { int size = slash - name + 1; memcpy(dirname, name, size); dirname[size] = 0; @@ -793,8 +800,7 @@ basename = conf_get_configname(); } else basename = name; - } else - basename = conf_get_configname(); + } sprintf(newname, "%s%s", dirname, basename); env = getenv("KCONFIG_OVERWRITECONFIG"); -- To view, visit https://review.coreboot.org/c/coreboot/+/34243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia21e930a9b0a693f851c34bcde26b34886cbe902 Gerrit-Change-Number: 34243 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: ec/google/chromeec: Add config option for eSPI
by Martin Roth (Code Review) 30 Aug '19

30 Aug '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35128 ) Change subject: ec/google/chromeec: Add config option for eSPI ...................................................................... ec/google/chromeec: Add config option for eSPI The Intel platforms using eSPI EC communication have just been enabling the EC_GOOGLE_CHROMEEC_LPC option for simplicity. This does basically the same, but at least marks it as eSPI in Kconfig for clarity. BUG=b:140055300 TEST=Build tested only. Change-Id: Ib56ec9d1dc204809a05c846494ff0e0d69cf70ea Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/ec/google/chromeec/Kconfig 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/35128/1 diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 3eb2c48..8c7d24e 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -47,6 +47,16 @@ help Use only proto3 for i2c EC communication. +config EC_GOOGLE_CHROMEEC_ESPI + depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play. + def_bool n + select EC_GOOGLE_CHROMEEC_LPC + help + Google Chrome EC via eSPI bus. + The EC communication code is the same between eSPI and LPC, so + this option simply enables the LPC EC code. The eSPI device + still needs to correctly configure the bus transactions. + config EC_GOOGLE_CHROMEEC_LPC depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play. def_bool y -- To view, visit https://review.coreboot.org/c/coreboot/+/35128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib56ec9d1dc204809a05c846494ff0e0d69cf70ea Gerrit-Change-Number: 35128 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skl/acpi: add description for missing PCIe ports
by Maxim Polyakov (Code Review) 30 Aug '19

30 Aug '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35072 ) Change subject: soc/intel/skl/acpi: add description for missing PCIe ports ...................................................................... soc/intel/skl/acpi: add description for missing PCIe ports According to the documentation, Sunrise PCH-H [1,2] and Lewisburg PCH [3] supports up to 16 PCIe ports. However, apci contains a description for only 12 ports. This patch adds ACPI code for missing ports [1] page 182, Intel (R) 100 Series and Intel (R) C230 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2, December 2018, Document Number: 332690-005EN [2] page 180, Intel (R) 200 Series and Intel (R) Z370 Series PCH Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2, October 2017, Document Number: 335192-003 [3] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Change-Id: I954870136e0c8e5ff5d7ff623c7a6432b829abaf Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/skylake/acpi/pcie.asl 1 file changed, 72 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/35072/1 diff --git a/src/soc/intel/skylake/acpi/pcie.asl b/src/soc/intel/skylake/acpi/pcie.asl index 84cb437..b039f53 100644 --- a/src/soc/intel/skylake/acpi/pcie.asl +++ b/src/soc/intel/skylake/acpi/pcie.asl @@ -69,7 +69,7 @@ Switch (ToInteger (Arg0)) { - Case (Package () { 1, 5, 9 }) { + Case (Package () { 1, 5, 9, 13 }) { If (PICM) { Return (IQAA) } Else { @@ -77,7 +77,7 @@ } } - Case (Package () { 2, 6, 10 }) { + Case (Package () { 2, 6, 10, 14 }) { If (PICM) { Return (IQBA) } Else { @@ -85,7 +85,7 @@ } } - Case (Package () { 3, 7, 11 }) { + Case (Package () { 3, 7, 11, 15 }) { If (PICM) { Return (IQCA) } Else { @@ -93,7 +93,7 @@ } } - Case (Package () { 4, 8, 12 }) { + Case (Package () { 4, 8, 12, 16 }) { If (PICM) { Return (IQDA) } Else { @@ -314,3 +314,71 @@ Return (IRQM (RPPN)) } } + +Device (RP13) +{ + Name (_ADR, 0x001D0004) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP14) +{ + Name (_ADR, 0x001D0005) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP15) +{ + Name (_ADR, 0x001D0006) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (RP16) +{ + Name (_ADR, 0x001D0007) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I954870136e0c8e5ff5d7ff623c7a6432b829abaf Gerrit-Change-Number: 35072 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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