coreboot-gerrit August 2019

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Change in coreboot[master]: soc/intel/skylake: Remove duplicated PCI Id
by Maxim Polyakov (Code Review) 30 Aug '19

30 Aug '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35121 ) Change subject: soc/intel/skylake: Remove duplicated PCI Id ...................................................................... soc/intel/skylake: Remove duplicated PCI Id Removes PCI_DEVICE_ID_INTEL_SKL_ID_DT because this PCI Id duplicates PCI_DEVICE_ID_INTEL_SKL_ID_S_4 (0x191f) Change-Id: I028a22d6a42c040f5991a03def3e410f515c1c7f Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/skylake/bootblock/report_platform.c 3 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/35121/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index cdd1c62..075780f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3108,7 +3108,6 @@ #define PCI_DEVICE_ID_INTEL_SKL_ID_S_4 0x191f #define PCI_DEVICE_ID_INTEL_KBL_ID_S 0x590f #define PCI_DEVICE_ID_INTEL_SKL_ID_H_EM 0x1918 -#define PCI_DEVICE_ID_INTEL_SKL_ID_DT 0x191f #define PCI_DEVICE_ID_INTEL_KBL_ID_U 0x5904 #define PCI_DEVICE_ID_INTEL_KBL_ID_Y 0x590c #define PCI_DEVICE_ID_INTEL_KBL_ID_H 0x5910 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index b7964e6..b19b8ca 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -348,7 +348,6 @@ PCI_DEVICE_ID_INTEL_WHL_ID_W_4, PCI_DEVICE_ID_INTEL_KBL_ID_S, PCI_DEVICE_ID_INTEL_SKL_ID_H_EM, - PCI_DEVICE_ID_INTEL_SKL_ID_DT, PCI_DEVICE_ID_INTEL_KBL_ID_U, PCI_DEVICE_ID_INTEL_KBL_ID_Y, PCI_DEVICE_ID_INTEL_KBL_ID_H, diff --git a/src/soc/intel/skylake/bootblock/report_platform.c b/src/soc/intel/skylake/bootblock/report_platform.c index a643bbe..1a66a6b 100644 --- a/src/soc/intel/skylake/bootblock/report_platform.c +++ b/src/soc/intel/skylake/bootblock/report_platform.c @@ -52,7 +52,6 @@ { PCI_DEVICE_ID_INTEL_SKL_ID_ULX, "Skylake-ULX" }, { PCI_DEVICE_ID_INTEL_SKL_ID_H, "Skylake-H" }, { PCI_DEVICE_ID_INTEL_SKL_ID_H_EM, "Skylake-H Embedded" }, - { PCI_DEVICE_ID_INTEL_SKL_ID_DT, "Skylake-DT" }, { PCI_DEVICE_ID_INTEL_SKL_ID_H_2, "Skylake-H (2 Core)" }, { PCI_DEVICE_ID_INTEL_SKL_ID_S_2, "Skylake-S (2 Core)" }, { PCI_DEVICE_ID_INTEL_SKL_ID_S_4, "Skylake-S (4 Core)" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/35121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I028a22d6a42c040f5991a03def3e410f515c1c7f Gerrit-Change-Number: 35121 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/drallion: change servo board debug to UART 0
by EricR Lai (Code Review) 30 Aug '19

30 Aug '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35132 ) Change subject: mb/google/drallion: change servo board debug to UART 0 ...................................................................... mb/google/drallion: change servo board debug to UART 0 Drallion will change debug port UART from 2 to 0. Followed HW schematic to modify it. BUG=b:139095062 BRANCH=N/A TEST=Build without error Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ib2bcded8de3c9fb2c0a4ccbd002b1f219bccceb5 --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/drallion/variants/drallion/gpio.c 2 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/35132/1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 575b610..54184f0 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -355,7 +355,7 @@ end end # I2C #4 device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 + device pci 19.2 off end # UART #2 device pci 1a.0 off end # eMMC device pci 1c.0 off end # PCI Express Port 1 (USB) device pci 1c.1 off end # PCI Express Port 2 (USB) @@ -374,7 +374,7 @@ device pci 1d.4 on smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" end # PCI Express Port 13 (x4) - device pci 1e.0 off end # UART #0 + device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 device pci 1e.3 off end # GSPI #1 diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index ff0240c..ebe5ee2 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -87,8 +87,8 @@ /* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K), /* SM1CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */ /* SM1DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */ -/* UART0_RXD */ PAD_NC(GPP_C8, NONE), /* PCH_TBT_PERST# (nostuff) */ -/* UART0_TXD */ PAD_NC(GPP_C9, NONE), +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* SERVOTX_UART */ +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* SERVORX_UART */ /* UART0_RTS# */ PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */ /* UART0_CTS# */ PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */ /* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP, @@ -100,8 +100,8 @@ /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */ /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */ /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */ -/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */ -/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ +/* UART2_RXD */ PAD_NC(GPP_C20, NONE), +/* UART2_TXD */ PAD_NC(GPP_C21, NONE), /* UART2_RTS# */ PAD_NC(GPP_C22, NONE), /* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, LEVEL, NONE), /* TS_INT# */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2bcded8de3c9fb2c0a4ccbd002b1f219bccceb5 Gerrit-Change-Number: 35132 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch: Add settings for noise mitgation
by Dtrain Hsu (Code Review) 30 Aug '19

30 Aug '19

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35005 ) Change subject: mb/google/hatch: Add settings for noise mitgation ...................................................................... mb/google/hatch: Add settings for noise mitgation Enable acoustic noise mitgation for hatch platform, the slow slew rates are fast time dived by 8 and disable Fast PKG C State Ramp(IA, GT, SA). BUG=b:131779678 TEST=waveform test and reduce the noise level. Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I49e834825b3f1e5bf02f9523d7caa93b544c9d17 --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/35005/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index c87a8bc..62cb3ca 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -193,6 +193,15 @@ # register "common_soc_config.<variable_name>" = "value" register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT + # VR Slew rate setting + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" + register "SlowSlewRateForSa" = "2" + register "FastPkgCRampDisableIa" = "1" + register "FastPkgCRampDisableGt" = "1" + register "FastPkgCRampDisableSa" = "1" + device cpu_cluster 0 on device lapic 0 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/35005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49e834825b3f1e5bf02f9523d7caa93b544c9d17 Gerrit-Change-Number: 35005 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arm64: Rename arm_tf.c/h to bl31.c/h
by Julius Werner (Code Review) 30 Aug '19

30 Aug '19

Hello Patrick Rudolph, Hung-Te Lin, Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34677 to review the following change. Change subject: arm64: Rename arm_tf.c/h to bl31.c/h ...................................................................... arm64: Rename arm_tf.c/h to bl31.c/h This patch renames arm_tf.c and arm_tf.h to bl31.c and bl31.h, respectively. That name is closer to the terminology used in most functions related to Trusted Firmware, and it removes the annoying auto-completion clash between arm64/arm_tf.c and arm64/armv8. Change-Id: I2741e2bce9d079b1025f82ecb3bb78a02fe39ed5 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/arch/arm64/Makefile.inc R src/arch/arm64/bl31.c M src/arch/arm64/boot.c R src/arch/arm64/include/bl31.h M src/soc/mediatek/mt8173/bl31_plat_params.c M src/soc/nvidia/tegra210/arm_tf.c M src/soc/rockchip/rk3399/bl31_plat_params.c 7 files changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/34677/1 diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 6bb7196..2f862da 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -135,7 +135,7 @@ ramstage-y += memset.S ramstage-y += memcpy.S ramstage-y += memmove.S -ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += arm_tf.c +ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31.c ramstage-y += transition.c transition_asm.S ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/bl31.c similarity index 96% rename from src/arch/arm64/arm_tf.c rename to src/arch/arm64/bl31.c index 291e4ee..0a793ee 100644 --- a/src/arch/arm64/arm_tf.c +++ b/src/arch/arm64/bl31.c @@ -17,7 +17,7 @@ #include <arch/lib_helpers.h> #include <arch/mmu.h> #include <arch/transition.h> -#include <arm_tf.h> +#include <bl31.h> #include <bootmem.h> #include <cbfs.h> #include <console/console.h> @@ -42,7 +42,7 @@ return NULL; } -void arm_tf_run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr) +void run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr) { struct prog bl31 = PROG_INIT(PROG_BL31, CONFIG_CBFS_PREFIX"/bl31"); void (*bl31_entry)(bl31_params_t *params, void *plat_params) = NULL; diff --git a/src/arch/arm64/boot.c b/src/arch/arm64/boot.c index 7fbc525..2c3d243 100644 --- a/src/arch/arm64/boot.c +++ b/src/arch/arm64/boot.c @@ -17,7 +17,7 @@ #include <arch/lib_helpers.h> #include <arch/stages.h> #include <arch/transition.h> -#include <arm_tf.h> +#include <bl31.h> #include <program_loading.h> static void run_payload(struct prog *prog) @@ -30,7 +30,7 @@ u64 payload_spsr = get_eret_el(EL2, SPSR_USE_L); if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE)) - arm_tf_run_bl31((u64)doit, (u64)arg, payload_spsr); + run_bl31((u64)doit, (u64)arg, payload_spsr); else transition_to_el2(doit, arg, payload_spsr); } diff --git a/src/arch/arm64/include/arm_tf.h b/src/arch/arm64/include/bl31.h similarity index 85% rename from src/arch/arm64/include/arm_tf.h rename to src/arch/arm64/include/bl31.h index ea5a0f4..460286b 100644 --- a/src/arch/arm64/include/arm_tf.h +++ b/src/arch/arm64/include/bl31.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef __ARM_TF_H__ -#define __ARM_TF_H__ +#ifndef __BL31_H__ +#define __BL31_H__ #include <types.h> @@ -22,9 +22,9 @@ #include <arm_tf_temp.h> /* Load and enter BL31, set it up to exit to payload according to arguments. */ -void arm_tf_run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr); +void run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr); /* Return platform-specific bl31_plat_params. May update bl31_params. */ void *soc_get_bl31_plat_params(bl31_params_t *bl31_params); -#endif /* __ARM_TF_H__ */ +#endif /* __BL31_H__ */ diff --git a/src/soc/mediatek/mt8173/bl31_plat_params.c b/src/soc/mediatek/mt8173/bl31_plat_params.c index 245866a..44ef934 100644 --- a/src/soc/mediatek/mt8173/bl31_plat_params.c +++ b/src/soc/mediatek/mt8173/bl31_plat_params.c @@ -12,7 +12,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <arm_tf.h> +#include <bl31.h> void *soc_get_bl31_plat_params(bl31_params_t *bl31_params) { diff --git a/src/soc/nvidia/tegra210/arm_tf.c b/src/soc/nvidia/tegra210/arm_tf.c index 38bb8bf..1da351a 100644 --- a/src/soc/nvidia/tegra210/arm_tf.c +++ b/src/soc/nvidia/tegra210/arm_tf.c @@ -14,8 +14,8 @@ */ #include <arch/cache.h> -#include <arm_tf.h> #include <assert.h> +#include <bl31.h> #include <soc/addressmap.h> #include <soc/console_uart.h> #include <symbols.h> diff --git a/src/soc/rockchip/rk3399/bl31_plat_params.c b/src/soc/rockchip/rk3399/bl31_plat_params.c index 9c11552..b8836c1 100644 --- a/src/soc/rockchip/rk3399/bl31_plat_params.c +++ b/src/soc/rockchip/rk3399/bl31_plat_params.c @@ -14,7 +14,7 @@ * */ -#include <arm_tf.h> +#include <bl31.h> #include <cbmem.h> #include <soc/bl31_plat_params.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/34677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2741e2bce9d079b1025f82ecb3bb78a02fe39ed5 Gerrit-Change-Number: 34677 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch: Add 16G 3200 generic SPD file
by Shelley Chen (Code Review) 30 Aug '19

30 Aug '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35138 ) Change subject: mb/google/hatch: Add 16G 3200 generic SPD file ...................................................................... mb/google/hatch: Add 16G 3200 generic SPD file BUG=b:139792883 BRANCH=None TEST=None Change-Id: I22974b015a40fb7ae592e182cf5da83a8252c031 Signed-off-by: Shelley Chen <shchen(a)google.com> --- A src/mainboard/google/hatch/spd/16G_3200.spd.hex 1 file changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/35138/1 diff --git a/src/mainboard/google/hatch/spd/16G_3200.spd.hex b/src/mainboard/google/hatch/spd/16G_3200.spd.hex new file mode 100644 index 0000000..09e1206 --- /dev/null +++ b/src/mainboard/google/hatch/spd/16G_3200.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 40 36 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/35138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22974b015a40fb7ae592e182cf5da83a8252c031 Gerrit-Change-Number: 35138 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/timer: Make TSC frequency calculation dynamically
by Subrata Banik (Code Review) 30 Aug '19

30 Aug '19

Hello Aaron Durbin, Patrick Rudolph, Meera Ravindranath, Lean Sheng Tan, Aamir Bohra, Wonkyu Kim, Maulik V Vaghela, V Sowmya, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35148 to look at the new patch set (#8). Change subject: soc/intel/common/timer: Make TSC frequency calculation dynamically ...................................................................... soc/intel/common/timer: Make TSC frequency calculation dynamically tsc_freq_mhz() had a static table of Intel CPU families and crystal clock, but it is possible to calculate the crystal clock speed dynamically, and this is preferred over hardcoded table. Recommendation is to make use of CPUID.16h where crystal clock frequency was not reported by CPUID.15h to calculate the crystal clock. On SKL/KBL/CML CPUID.15h.ecx = nominal core crystal clock = 0 Hz hence we had to use static table to calculate crystal clock. BUG=b:139798422, b:129839774 TEST=Able to build and boot KBL/CML/ICL. Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- D src/arch/x86/include/arch/intel-family.h M src/soc/intel/common/block/timer/timer.c 2 files changed, 53 insertions(+), 114 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/35148/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/35148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Gerrit-Change-Number: 35148 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: arch/x86: Include stack_top region into postcar_frame
by Subrata Banik (Code Review) 30 Aug '19

30 Aug '19

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34991 to review the following change. Change subject: arch/x86: Include stack_top region into postcar_frame ...................................................................... arch/x86: Include stack_top region into postcar_frame This patch signals to the system that stack region also needs to be accounted for as it holds MTRR related values. Change-Id: I9279bbd66be0ad309bdabbbb90bf59c6f5967c47 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/include/arch/cpu.h M src/arch/x86/postcar_loader.c 2 files changed, 12 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/34991/1 diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 9aa446e..075e890 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -298,6 +298,7 @@ */ struct postcar_frame { + uintptr_t stack_top; uintptr_t stack; uint32_t upper_mask; int max_var_mtrrs; diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index b1b2da0..d017260 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -66,7 +66,10 @@ postcar_frame_prepare(pcf); pcf->stack = (uintptr_t)stack; - pcf->stack += stack_size; + /* Keep track of stack top to calculate size used */ + pcf->stack_top = pcf->stack; + pcf->stack_top += stack_size; + return 0; } @@ -143,15 +146,18 @@ return (void *) pcf->stack; } -static void finalize_load(uintptr_t *stack_top_ptr, uintptr_t stack_top) +static void finalize_load(uintptr_t *stack_top_ptr, + const struct postcar_frame *pcf) { - *stack_top_ptr = stack_top; + *stack_top_ptr = pcf->stack; /* * Signal to rest of system that another update was made to the * postcar program prior to running it. */ prog_segment_loaded((uintptr_t)stack_top_ptr, sizeof(uintptr_t), SEG_FINAL); + /* Also signal the stack region that was written as well */ + prog_segment_loaded(pcf->stack, pcf->stack_top - pcf->stack, SEG_FINAL); } static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf) @@ -173,7 +179,7 @@ die_with_post_code(POST_INVALID_ROM, "No parameters found in after CAR program.\n"); - finalize_load(rsl.params, pcf->stack); + finalize_load(rsl.params, pcf); stage_cache_add(STAGE_POSTCAR, prog); } @@ -191,7 +197,7 @@ /* This is here to allow platforms to pass different stack parameters between S3 resume and normal boot. On the platforms where the values are the same it's a nop. */ - finalize_load(prog.arg, pcf->stack); + finalize_load(prog.arg, pcf); } else load_postcar_cbfs(&prog, pcf); -- To view, visit https://review.coreboot.org/c/coreboot/+/34991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9279bbd66be0ad309bdabbbb90bf59c6f5967c47 Gerrit-Change-Number: 34991 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

3 21

Change in coreboot[master]: mediatek/mt8183: put md_init flow to romstage
by Yanjie Jiang (Code Review) 30 Aug '19

30 Aug '19

Yanjie Jiang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35162 ) Change subject: mediatek/mt8183: put md_init flow to romstage ...................................................................... mediatek/mt8183: put md_init flow to romstage Consider the association between modem[1] and DCXO, modem should be powerred off before DCXO, so we move it to romstage from ramstage. BRANCH=none Test=Boots correctly on Kukui, suspend test pass. Change-Id: Id147e30f2e2bbf018443bbadc869cc8e004cc65b Signed-off-by: Yanjie.jiang <yanjie.jiang(a)mediatek.com --- M src/mainboard/google/kukui/romstage.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/soc.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/35162/1 diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index baaca43..71e0ba8 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -15,6 +15,7 @@ #include <arch/stages.h> #include <soc/emi.h> +#include <soc/md_ctrl.h> #include <soc/mmu_operations.h> #include <soc/mt6358.h> #include <soc/pll.h> @@ -30,6 +31,7 @@ mt6358_init(); mt_pll_raise_ca53_freq(1989 * MHz); + mtk_md_early_init(); rtc_boot(); mt_mem_init(get_sdram_config()); mtk_mmu_after_dram(); diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 6e2207a..4655d7f 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -39,6 +39,7 @@ romstage-y += ../common/timer.c romstage-y += ../common/uart.c romstage-y += ../common/wdt.c +romstage-y += md_ctrl.c ramstage-y += auxadc.c ramstage-y += ../common/cbmem.c emi.c @@ -51,7 +52,6 @@ ramstage-y += ../common/uart.c ramstage-y += ../common/usb.c ramstage-y += ../common/wdt.c -ramstage-y += md_ctrl.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8183/soc.c b/src/soc/mediatek/mt8183/soc.c index 501ae19..7dcbce9 100644 --- a/src/soc/mediatek/mt8183/soc.c +++ b/src/soc/mediatek/mt8183/soc.c @@ -15,7 +15,6 @@ #include <device/device.h> #include <soc/emi.h> -#include <soc/md_ctrl.h> #include <soc/mmu_operations.h> #include <symbols.h> @@ -27,7 +26,6 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); - mtk_md_early_init(); } static struct device_operations soc_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/35162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id147e30f2e2bbf018443bbadc869cc8e004cc65b Gerrit-Change-Number: 35162 Gerrit-PatchSet: 1 Gerrit-Owner: Yanjie Jiang <yanjie.jiang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/supermicro: Change X10SLM+-F's tree to X10SLM and add variant X10S...
by Christoph Pomaska (Code Review) 30 Aug '19

30 Aug '19

Christoph Pomaska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34906 ) Change subject: mb/supermicro: Change X10SLM+-F's tree to X10SLM and add variant X10SLM+-LN4F ...................................................................... mb/supermicro: Change X10SLM+-F's tree to X10SLM and add variant X10SLM+-LN4F This commit modifies the source tree of the X10SLM-F board to support building a slightly different variant of the board, the X10SLM-LN4F. Change-Id: I8ec3b983e195ac0f840558f86472c43c4f815ad4 Signed-off-by: Christoph Pomaska <c.pomaska(a)hosting.de> --- D src/mainboard/supermicro/x10slm-f/Kconfig.name R src/mainboard/supermicro/x10slm/Kconfig A src/mainboard/supermicro/x10slm/Kconfig.name R src/mainboard/supermicro/x10slm/Makefile.inc R src/mainboard/supermicro/x10slm/acpi/ec.asl R src/mainboard/supermicro/x10slm/acpi/platform.asl R src/mainboard/supermicro/x10slm/acpi/superio.asl R src/mainboard/supermicro/x10slm/acpi_tables.c R src/mainboard/supermicro/x10slm/board_info.txt R src/mainboard/supermicro/x10slm/bootblock.c R src/mainboard/supermicro/x10slm/cmos.default R src/mainboard/supermicro/x10slm/cmos.layout R src/mainboard/supermicro/x10slm/dsdt.asl R src/mainboard/supermicro/x10slm/gpio.c R src/mainboard/supermicro/x10slm/mainboard.c R src/mainboard/supermicro/x10slm/romstage.c R src/mainboard/supermicro/x10slm/variants/x10slm-f/devicetree.cb R src/mainboard/supermicro/x10slm/variants/x10slm-f/hda_verb.c A src/mainboard/supermicro/x10slm/variants/x10slm-ln4f/devicetree.cb C src/mainboard/supermicro/x10slm/variants/x10slm-ln4f/hda_verb.c 20 files changed, 171 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/34906/1 diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig.name b/src/mainboard/supermicro/x10slm-f/Kconfig.name deleted file mode 100644 index a1965a3..0000000 --- a/src/mainboard/supermicro/x10slm-f/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_SUPERMICRO_X10SLM_PLUS_F - bool "X10SLM+-F" diff --git a/src/mainboard/supermicro/x10slm-f/Kconfig b/src/mainboard/supermicro/x10slm/Kconfig similarity index 61% rename from src/mainboard/supermicro/x10slm-f/Kconfig rename to src/mainboard/supermicro/x10slm/Kconfig index 6effff2..99a3099 100644 --- a/src/mainboard/supermicro/x10slm-f/Kconfig +++ b/src/mainboard/supermicro/x10slm/Kconfig @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> +## Copyright (C) 2019 Hosting.de GmbH <c.pomaska(a)hosting.de> ## ## This program is free software: you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -14,36 +15,48 @@ ## GNU General Public License for more details. ## -if BOARD_SUPERMICRO_X10SLM_PLUS_F +if BOARD_SUPERMICRO_X10SLM_PLUS_F || BOARD_SUPERMICRO_X10SLM_PLUS_LN4F config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_16384 select CPU_INTEL_HASWELL - select SOUTHBRIDGE_INTEL_LYNXPOINT select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select NORTHBRIDGE_INTEL_HASWELL select SERIRQ_CONTINUOUS_MODE - select DRIVERS_ASPEED_AST2050 # Supports AST2400 too. - select SUPERIO_ASPEED_AST2400 # The board's BMC - select SUPERIO_NUVOTON_NCT6776 # the board's superio + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 select SUPERIO_NUVOTON_NCT6776_COM_A + select DRIVERS_ASPEED_AST2050 + select SUPERIO_ASPEED_AST2400 # The board's BMC + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + +config MAINBOARD_DIR + string + default "supermicro/x10slm" + +config VARIANT_DIR + string + default "x10slm-f" if BOARD_SUPERMICRO_X10SLM_PLUS_F + default "x10slm-ln4f" if BOARD_SUPERMICRO_X10SLM_PLUS_LN4F + +config MAINBOARD_PART_NUMBER + string + default "X10SLM+-F" if BOARD_SUPERMICRO_X10SLM_PLUS_F + default "X10SLM+-LN4F" if BOARD_SUPERMICRO_X10SLM_PLUS_LN4F + +config DEVICETREE + default "variants/x10slm-f/devicetree.cb" if BOARD_SUPERMICRO_X10SLM_PLUS_F + default "variants/x10slm-ln4f/devicetree.cb" if BOARD_SUPERMICRO_X10SLM_PLUS_LN4F config CBFS_SIZE hex default 0xb00000 -config MAINBOARD_DIR - string - default "supermicro/x10slm-f" - -config MAINBOARD_PART_NUMBER - string - default "X10SLM+-F" - config MAX_CPUS int default 8 diff --git a/src/mainboard/supermicro/x10slm/Kconfig.name b/src/mainboard/supermicro/x10slm/Kconfig.name new file mode 100644 index 0000000..6f95d97 --- /dev/null +++ b/src/mainboard/supermicro/x10slm/Kconfig.name @@ -0,0 +1,4 @@ +config BOARD_SUPERMICRO_X10SLM_PLUS_F + bool "X10SLM+-F" +config BOARD_SUPERMICRO_X10SLM_PLUS_LN4F + bool "X10SLM+-LN4F" diff --git a/src/mainboard/supermicro/x10slm-f/Makefile.inc b/src/mainboard/supermicro/x10slm/Makefile.inc similarity index 100% rename from src/mainboard/supermicro/x10slm-f/Makefile.inc rename to src/mainboard/supermicro/x10slm/Makefile.inc diff --git a/src/mainboard/supermicro/x10slm-f/acpi/ec.asl b/src/mainboard/supermicro/x10slm/acpi/ec.asl similarity index 100% rename from src/mainboard/supermicro/x10slm-f/acpi/ec.asl rename to src/mainboard/supermicro/x10slm/acpi/ec.asl diff --git a/src/mainboard/supermicro/x10slm-f/acpi/platform.asl b/src/mainboard/supermicro/x10slm/acpi/platform.asl similarity index 100% rename from src/mainboard/supermicro/x10slm-f/acpi/platform.asl rename to src/mainboard/supermicro/x10slm/acpi/platform.asl diff --git a/src/mainboard/supermicro/x10slm-f/acpi/superio.asl b/src/mainboard/supermicro/x10slm/acpi/superio.asl similarity index 100% rename from src/mainboard/supermicro/x10slm-f/acpi/superio.asl rename to src/mainboard/supermicro/x10slm/acpi/superio.asl diff --git a/src/mainboard/supermicro/x10slm-f/acpi_tables.c b/src/mainboard/supermicro/x10slm/acpi_tables.c similarity index 100% rename from src/mainboard/supermicro/x10slm-f/acpi_tables.c rename to src/mainboard/supermicro/x10slm/acpi_tables.c diff --git a/src/mainboard/supermicro/x10slm-f/board_info.txt b/src/mainboard/supermicro/x10slm/board_info.txt similarity index 100% rename from src/mainboard/supermicro/x10slm-f/board_info.txt rename to src/mainboard/supermicro/x10slm/board_info.txt diff --git a/src/mainboard/supermicro/x10slm-f/bootblock.c b/src/mainboard/supermicro/x10slm/bootblock.c similarity index 100% rename from src/mainboard/supermicro/x10slm-f/bootblock.c rename to src/mainboard/supermicro/x10slm/bootblock.c diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm/cmos.default similarity index 100% rename from src/mainboard/supermicro/x10slm-f/cmos.default rename to src/mainboard/supermicro/x10slm/cmos.default diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm/cmos.layout similarity index 100% rename from src/mainboard/supermicro/x10slm-f/cmos.layout rename to src/mainboard/supermicro/x10slm/cmos.layout diff --git a/src/mainboard/supermicro/x10slm-f/dsdt.asl b/src/mainboard/supermicro/x10slm/dsdt.asl similarity index 100% rename from src/mainboard/supermicro/x10slm-f/dsdt.asl rename to src/mainboard/supermicro/x10slm/dsdt.asl diff --git a/src/mainboard/supermicro/x10slm-f/gpio.c b/src/mainboard/supermicro/x10slm/gpio.c similarity index 100% rename from src/mainboard/supermicro/x10slm-f/gpio.c rename to src/mainboard/supermicro/x10slm/gpio.c diff --git a/src/mainboard/supermicro/x10slm-f/mainboard.c b/src/mainboard/supermicro/x10slm/mainboard.c similarity index 100% rename from src/mainboard/supermicro/x10slm-f/mainboard.c rename to src/mainboard/supermicro/x10slm/mainboard.c diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm/romstage.c similarity index 100% rename from src/mainboard/supermicro/x10slm-f/romstage.c rename to src/mainboard/supermicro/x10slm/romstage.c diff --git a/src/mainboard/supermicro/x10slm-f/devicetree.cb b/src/mainboard/supermicro/x10slm/variants/x10slm-f/devicetree.cb similarity index 100% rename from src/mainboard/supermicro/x10slm-f/devicetree.cb rename to src/mainboard/supermicro/x10slm/variants/x10slm-f/devicetree.cb diff --git a/src/mainboard/supermicro/x10slm-f/hda_verb.c b/src/mainboard/supermicro/x10slm/variants/x10slm-f/hda_verb.c similarity index 100% rename from src/mainboard/supermicro/x10slm-f/hda_verb.c rename to src/mainboard/supermicro/x10slm/variants/x10slm-f/hda_verb.c diff --git a/src/mainboard/supermicro/x10slm/variants/x10slm-ln4f/devicetree.cb b/src/mainboard/supermicro/x10slm/variants/x10slm-ln4f/devicetree.cb new file mode 100644 index 0000000..5dce6b0 --- /dev/null +++ b/src/mainboard/supermicro/x10slm/variants/x10slm-ln4f/devicetree.cb @@ -0,0 +1,141 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/haswell + + device cpu_cluster 0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + + device lapic 0 on end + device lapic 0xacac off end + end + end + + device domain 0 on + subsystemid 0x15d9 0x0803 inherit + + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG 10 + device pci 01.1 on end # PEG 11 + device pci 02.0 off end # IGD + device pci 03.0 off end # Mini-HD audio + + chip southbridge/intel/lynxpoint + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8a" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x85" + + register "sata_ahci" = "1" + register "sata_port_map" = "0x3f" + + register "gen1_dec" = "0x00000295" # Super I/O HWM + + device pci 14.0 on end # xHCI controller + device pci 16.0 on end # Management Engine interface 1 + device pci 16.1 on end # Management Engine interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # EHCI controller 2 + device pci 1b.0 off end # HD audio controller + device pci 1c.0 on # PCIe root port 1 + device pci 00.0 on # ASPEED PCI-to-PCI bridge + device pci 00.0 on end # VGA controller + end + end + device pci 1c.1 off end # PCIe root port 2 + device pci 1c.2 on # PCIe root port 3 + device pci 00.0 on # Intel I210 Gigabit Ethernet + subsystemid 0x15d9 0x1533 + end + end + device pci 1c.3 on # PCIe root port 4 + device pci 00.0 on # Intel I210 Gigabit Ethernet + subsystemid 0x15d9 0x1533 + end + end + device pci 1c.4 on end # PCIe root port 5 + device pci 1c.5 off end # PCIe root port 6 + device pci 1c.6 on # PCIe root port 7 + device pci 00.0 on # Intel I210 Gigabit Ethernet + subsystemid 0x15d9 0x1533 + end + end + device pci 1c.7 on # PCIe root port 8 + device pci 00.0 on # Intel I210 Gigabit Ethernet + subsystemid 0x15d9 0x1533 + end + end + device pci 1d.0 on end # EHCI controller 1 + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # UART B + io 0x60 = 0x02f8 + irq 0x70 = 3 + end + device pnp 2e.5 off end # PS/2 KBC + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on end # SATA controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA controller 2 + device pci 1f.6 on end # PCH thermal sensor + end + end +end diff --git a/src/mainboard/supermicro/x10slm-f/hda_verb.c b/src/mainboard/supermicro/x10slm/variants/x10slm-ln4f/hda_verb.c similarity index 100% copy from src/mainboard/supermicro/x10slm-f/hda_verb.c copy to src/mainboard/supermicro/x10slm/variants/x10slm-ln4f/hda_verb.c -- To view, visit https://review.coreboot.org/c/coreboot/+/34906 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ec3b983e195ac0f840558f86472c43c4f815ad4 Gerrit-Change-Number: 34906 Gerrit-PatchSet: 1 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Christian Walter (Code Review) 30 Aug '19

30 Aug '19

Hello Angel Pons, Patrick Rudolph, Felix Singer, build bot (Jenkins), Patrick Georgi, Alexander Couzens, T. Hudson, Keno Fischer, Name of user not set #1002358, Trammell Hudson, Philipp Deppenwiese, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/32734 to look at the new patch set (#75). Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... mb/supermicro/x11ssh: Add Supermicro X11SSH-TF Add support for the X11SSH-TF which is based on Intel KBL. Working: * SeaBios payload * LinuxBoot payload * IPMI of BMC * PCIe, SATA, USB and M.2 ports * RS232 serial * Native graphics init Not working: * Tianocore doesn't work yet as the Aspeed NGI is text mode only. * Intel SGX, due to random crashes in soc/intel/common For more details have a look at the documentation. Please apply those patches as well for good user experience: I456be647b159f7a2ea7d94986a24424e56dcc8c4 I22c6885eae6fd7c778ac37b18f95b8775e9064e3 Ica0c20255f661dd61edc3a7d15646b7447c4658e Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 --- M Documentation/mainboard/index.md A Documentation/mainboard/supermicro/x11ssh-tf.md A Documentation/mainboard/supermicro/x11ssh_flash.jpg A src/mainboard/supermicro/x11ssh/Kconfig A src/mainboard/supermicro/x11ssh/Kconfig.name A src/mainboard/supermicro/x11ssh/Makefile.inc A src/mainboard/supermicro/x11ssh/acpi/ec.asl A src/mainboard/supermicro/x11ssh/acpi/mainboard.asl A src/mainboard/supermicro/x11ssh/acpi/superio.asl A src/mainboard/supermicro/x11ssh/acpi_tables.c A src/mainboard/supermicro/x11ssh/board_info.txt A src/mainboard/supermicro/x11ssh/bootblock.c A src/mainboard/supermicro/x11ssh/cmos.layout A src/mainboard/supermicro/x11ssh/dsdt.asl A src/mainboard/supermicro/x11ssh/gpio.h A src/mainboard/supermicro/x11ssh/mainboard.c A src/mainboard/supermicro/x11ssh/ramstage.c A src/mainboard/supermicro/x11ssh/romstage.c A src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt A src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb A src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd 21 files changed, 1,020 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/32734/75 -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 75 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit August 2019