coreboot-gerrit August 2019

coreboot-gerrit@coreboot.org

1 participants
1942 discussions

Change in coreboot[master]: mb/dell: Add Dell Optiplex 790
by Angel Pons (Code Review) 30 Aug '19

30 Aug '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21774 ) Change subject: mb/dell: Add Dell Optiplex 790 ...................................................................... Patch Set 59: (2 comments) Build failure is unrelated to this change. Also SMSC SCH5544 is evil. https://review.coreboot.org/c/coreboot/+/21774/59/src/mainboard/dell/optipl… File src/mainboard/dell/optiplex_790/variants/optiplex_790_mt-sff/devicetree.cb: https://review.coreboot.org/c/coreboot/+/21774/59/src/mainboard/dell/optipl… PS59, Line 54: 0x4 This is what makes SATA not work on USFF https://review.coreboot.org/c/coreboot/+/21774/59/src/mainboard/dell/optipl… PS59, Line 78: d MT/DT probably want this on -- To view, visit https://review.coreboot.org/c/coreboot/+/21774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3d3a13163d5da1368259a7498019d42fb3ed57f Gerrit-Change-Number: 21774 Gerrit-PatchSet: 59 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Fri, 30 Aug 2019 01:09:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[4.10_branch]: soc/intel/fsp_broadwell_de: Fix use of config_of()
by Angel Pons (Code Review) 30 Aug '19

30 Aug '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35045 ) Change subject: soc/intel/fsp_broadwell_de: Fix use of config_of() ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.10_branch Gerrit-Change-Id: I96d423720fbe67c067373436ad250edf37939e99 Gerrit-Change-Number: 35045 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Aug 2019 01:01:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[4.10_branch]: google/link: fix detection of dimm on channel 1
by Angel Pons (Code Review) 30 Aug '19

30 Aug '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35046 ) Change subject: google/link: fix detection of dimm on channel 1 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.10_branch Gerrit-Change-Id: Id01d57d5e5f928dfc1cd9063ab1625c440ef2bbe Gerrit-Change-Number: 35046 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 30 Aug 2019 00:54:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: arch/arm64: Make ARM64 stages select ARCH_ARM64
by Julius Werner (Code Review) 29 Aug '19

29 Aug '19

Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31315 ) Change subject: arch/arm64: Make ARM64 stages select ARCH_ARM64 ...................................................................... arch/arm64: Make ARM64 stages select ARCH_ARM64 Also don't define the default as this result in spurious lines in the .config. The only difference in config.h is on boards with the Nvidia tegra210 SOC that now select ARCH_ARM64, because its ramstage runs in that mode. The resulting binary is identical however. Change-Id: Iaa9cd902281e51f823717f6ea4c72e5736fefb31 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31315 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/arm64/Kconfig M src/arch/arm64/armv8/Kconfig 2 files changed, 11 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved Julius Werner: Looks good to me, approved diff --git a/src/arch/arm64/Kconfig b/src/arch/arm64/Kconfig index 71c9f04..3d1d184 100644 --- a/src/arch/arm64/Kconfig +++ b/src/arch/arm64/Kconfig @@ -1,27 +1,27 @@ config ARCH_ARM64 bool - default n config ARCH_BOOTBLOCK_ARM64 bool - default n select ARCH_ARM64 select C_ENVIRONMENT_BOOTBLOCK config ARCH_VERSTAGE_ARM64 bool - default n + select ARCH_ARM64 config ARCH_ROMSTAGE_ARM64 bool - default n + select ARCH_ARM64 config ARCH_RAMSTAGE_ARM64 bool - default n + select ARCH_ARM64 source src/arch/arm64/armv8/Kconfig +if ARCH_ARM64 + config ARM64_USE_ARCH_TIMER bool default n @@ -58,3 +58,5 @@ incorrect address calculations in rare cases. This option enables a linker workaround to avoid those cases if your toolchain supports it. Should be selected automatically by SoCs that are affected. + +endif # if ARCH_ARM64 diff --git a/src/arch/arm64/armv8/Kconfig b/src/arch/arm64/armv8/Kconfig index 2070bea..f70b529 100644 --- a/src/arch/arm64/armv8/Kconfig +++ b/src/arch/arm64/armv8/Kconfig @@ -1,17 +1,17 @@ config ARCH_BOOTBLOCK_ARMV8_64 - def_bool n + bool select ARCH_BOOTBLOCK_ARM64 config ARCH_VERSTAGE_ARMV8_64 - def_bool n + bool select ARCH_VERSTAGE_ARM64 config ARCH_ROMSTAGE_ARMV8_64 - def_bool n + bool select ARCH_ROMSTAGE_ARM64 config ARCH_RAMSTAGE_ARMV8_64 - def_bool n + bool select ARCH_RAMSTAGE_ARM64 config ARCH_ARMV8_EXTENSION -- To view, visit https://review.coreboot.org/c/coreboot/+/31315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa9cd902281e51f823717f6ea4c72e5736fefb31 Gerrit-Change-Number: 31315 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: arch/arm: Make ARM specific options depend on select ARCH_ARM
by Arthur Heymans (Code Review) 29 Aug '19

29 Aug '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31313 Change subject: arch/arm: Make ARM specific options depend on select ARCH_ARM ...................................................................... arch/arm: Make ARM specific options depend on select ARCH_ARM Also don't define the default as this result in spurious lines in the .config. Change-Id: I1ed4a71599641db606510e5304b9f0acf9b7eb88 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/arm/Kconfig M src/soc/nvidia/tegra124/Kconfig M src/soc/nvidia/tegra210/Kconfig M src/soc/qualcomm/ipq40xx/Kconfig M src/soc/qualcomm/ipq806x/Kconfig M src/soc/rockchip/rk3288/Kconfig M src/soc/samsung/exynos5250/Kconfig M src/soc/samsung/exynos5420/Kconfig 8 files changed, 11 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/31313/1 diff --git a/src/arch/arm/Kconfig b/src/arch/arm/Kconfig index 6d9cc78..14d054a 100644 --- a/src/arch/arm/Kconfig +++ b/src/arch/arm/Kconfig @@ -1,11 +1,11 @@ config ARCH_ARM bool - default n + +if ARCH_ARM config ARCH_BOOTBLOCK_ARM bool default n - select ARCH_ARM select C_ENVIRONMENT_BOOTBLOCK config ARCH_VERSTAGE_ARM @@ -26,3 +26,5 @@ config ARM_LPAE bool default n + +endif #if ARCH_ARM diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index eecb59b..e9e43a5 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -1,6 +1,7 @@ config SOC_NVIDIA_TEGRA124 bool default n + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV4 select BOOTBLOCK_CUSTOM select ARCH_VERSTAGE_ARMV7 diff --git a/src/soc/nvidia/tegra210/Kconfig b/src/soc/nvidia/tegra210/Kconfig index 8883baa..52118c3 100644 --- a/src/soc/nvidia/tegra210/Kconfig +++ b/src/soc/nvidia/tegra210/Kconfig @@ -1,6 +1,7 @@ config SOC_NVIDIA_TEGRA210 bool default n + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV4 select BOOTBLOCK_CUSTOM select ARCH_VERSTAGE_ARMV4 diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig index 72e05fa..7a0648c 100644 --- a/src/soc/qualcomm/ipq40xx/Kconfig +++ b/src/soc/qualcomm/ipq40xx/Kconfig @@ -1,6 +1,7 @@ config SOC_QC_IPQ40XX bool default n + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 0b112d9..3bea529 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -1,6 +1,7 @@ config SOC_QC_IPQ806X bool default n + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 53666c2..654374c 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -16,6 +16,7 @@ config SOC_ROCKCHIP_RK3288 bool default n + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 diff --git a/src/soc/samsung/exynos5250/Kconfig b/src/soc/samsung/exynos5250/Kconfig index 5b39724..149d703 100644 --- a/src/soc/samsung/exynos5250/Kconfig +++ b/src/soc/samsung/exynos5250/Kconfig @@ -1,4 +1,5 @@ config CPU_SAMSUNG_EXYNOS5250 + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 diff --git a/src/soc/samsung/exynos5420/Kconfig b/src/soc/samsung/exynos5420/Kconfig index 7b87650..4ffbf7f 100644 --- a/src/soc/samsung/exynos5420/Kconfig +++ b/src/soc/samsung/exynos5420/Kconfig @@ -1,4 +1,5 @@ config CPU_SAMSUNG_EXYNOS5420 + select ARCH_ARM select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 -- To view, visit https://review.coreboot.org/c/coreboot/+/31313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ed4a71599641db606510e5304b9f0acf9b7eb88 Gerrit-Change-Number: 31313 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: arch/arm64: Make ARM64 stages select ARCH_ARM64
by Julius Werner (Code Review) 29 Aug '19

29 Aug '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31315 ) Change subject: arch/arm64: Make ARM64 stages select ARCH_ARM64 ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/31315/5/src/arch/arm64/Kconfig File src/arch/arm64/Kconfig: https://review.coreboot.org/c/coreboot/+/31315/5/src/arch/arm64/Kconfig@4 PS5, Line 4: if ARCH_ARM64 > Why not put this below the individual stage options and then 'select ARCH_ARM64' from each of them? […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/31315 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa9cd902281e51f823717f6ea4c72e5736fefb31 Gerrit-Change-Number: 31315 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 29 Aug 2019 20:45:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/timer: Make TSC frequency calculation dynamically
by Kyösti Mälkki (Code Review) 29 Aug '19

29 Aug '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35148 ) Change subject: soc/intel/common/timer: Make TSC frequency calculation dynamically ...................................................................... Patch Set 4: (4 comments) https://review.coreboot.org/c/coreboot/+/35148/4/src/soc/intel/common/block… File src/soc/intel/common/block/timer/timer.c: https://review.coreboot.org/c/coreboot/+/35148/4/src/soc/intel/common/block… PS4, Line 24: #define CPU_MODEL_INTEL_ATOM_DENVERTON 0x5F Why remove the header that provided this? https://review.coreboot.org/c/coreboot/+/35148/4/src/soc/intel/common/block… PS4, Line 67: assert(cpuidr_15h.ebx != 0 || cpuidr_15h.eax != 0); I know this is what I wrote, but I have second thoughts about the assert() now. It's probably too early for console/printk() to work and this could hit infinite recursion via udelay(). Better leave assert() away. https://review.coreboot.org/c/coreboot/+/35148/4/src/soc/intel/common/block… PS4, Line 78: core_crystal_nominal_freq_khz = 25000; Indentation is confusing. You don't use cpuidr_15 for atom/denvertgon at all so you can move this up. For common code it is recommended that you check feature bits(?) that certain CPUID is implemented before accessing those leafs. This file should be made compatible with older intel SoCs as well, but can be followup work. https://review.coreboot.org/c/coreboot/+/35148/4/src/soc/intel/common/block… PS4, Line 94: return (core_crystal_nominal_freq_khz * cpuidr_15h.ebx / Returning 0 here is what I want to avoid. That assert() might be fall-thru and not appear in the logs at all. I have a topic thread 'monotonic-timer', I will come up with some plan such that the detected timebase always gets printed on the console. -- To view, visit https://review.coreboot.org/c/coreboot/+/35148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da Gerrit-Change-Number: 35148 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 29 Aug 2019 19:58:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: intel/fsp_broadwell_de: Move and rename smm_lock()
by Kyösti Mälkki (Code Review) 29 Aug '19

29 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34874 ) Change subject: intel/fsp_broadwell_de: Move and rename smm_lock() ...................................................................... intel/fsp_broadwell_de: Move and rename smm_lock() There will be inlined smm_lock() that would conflict with this special case. Change-Id: I6752cbcf4775f9c013f0b16033b40beb2c503f81 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/fsp_broadwell_de/cpu.c M src/soc/intel/fsp_broadwell_de/smmrelocate.c 2 files changed, 18 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/34874/1 diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c index db33f2e..ac4dcc9 100644 --- a/src/soc/intel/fsp_broadwell_de/cpu.c +++ b/src/soc/intel/fsp_broadwell_de/cpu.c @@ -25,8 +25,12 @@ #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <device/device.h> +#include <device/pci_ops.h> +#include <soc/lpc.h> #include <soc/msr.h> #include <soc/pattrs.h> +#include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/smm.h> @@ -94,6 +98,19 @@ wrmsr(IA32_PERF_CTL, perf_ctl); } +static void alt_smm_lock(void) +{ + struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC); + uint16_t smi_lock; + + /* There is no register to lock SMRAM region on Broadwell-DE. + Use this function to lock the SMI control bits. */ + printk(BIOS_DEBUG, "Locking SMM.\n"); + smi_lock = pci_read_config16(dev, GEN_PMCON_1); + smi_lock |= (SMI_LOCK | SMI_LOCK_GP6 | SMI_LOCK_GP22); + pci_write_config16(dev, GEN_PMCON_1, smi_lock); +} + static void post_mp_init(void) { /* Set Max Ratio */ @@ -103,7 +120,7 @@ smm_southbridge_enable_smi(); /* Set SMI lock bits. */ - smm_lock(); + alt_smm_lock(); } static const struct mp_ops mp_ops = { diff --git a/src/soc/intel/fsp_broadwell_de/smmrelocate.c b/src/soc/intel/fsp_broadwell_de/smmrelocate.c index b0d3f14..efd42e9 100644 --- a/src/soc/intel/fsp_broadwell_de/smmrelocate.c +++ b/src/soc/intel/fsp_broadwell_de/smmrelocate.c @@ -27,7 +27,6 @@ #include <cpu/intel/smm_reloc.h> #include <console/console.h> #include <device/pci_ops.h> -#include <soc/lpc.h> #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/smm.h> @@ -305,16 +304,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - pci_devfn_t dev = PCI_DEV(BUS0, LPC_DEV, LPC_FUNC); - uint16_t smi_lock; - - /* There is no register to lock SMRAM region on Broadwell-DE. - Use this function to lock the SMI control bits. */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - smi_lock = pci_read_config16(dev, GEN_PMCON_1); - smi_lock |= (SMI_LOCK | SMI_LOCK_GP6 | SMI_LOCK_GP22); - pci_write_config16(dev, GEN_PMCON_1, smi_lock); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/34874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6752cbcf4775f9c013f0b16033b40beb2c503f81 Gerrit-Change-Number: 34874 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/drallion: Update memory map
by Bernardo Perez Priego (Code Review) 29 Aug '19

29 Aug '19

Bernardo Perez Priego has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35129 ) Change subject: mb/google/drallion: Update memory map ...................................................................... mb/google/drallion: Update memory map This will enable to optionally inject ISH binaries into coreboot. BUG:b:139820063 TEST='compile successfully' Change-Id: I38659460726a3f647cda3bc3efd442f18aea24f0 Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> --- M src/mainboard/google/drallion/chromeos.fmd 1 file changed, 11 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/35129/1 diff --git a/src/mainboard/google/drallion/chromeos.fmd b/src/mainboard/google/drallion/chromeos.fmd index ece0eda..78b12bd 100644 --- a/src/mainboard/google/drallion/chromeos.fmd +++ b/src/mainboard/google/drallion/chromeos.fmd @@ -1,27 +1,26 @@ FLASH@0xfe000000 0x2000000 { - SI_ALL@0x0 0x400000 { + SI_ALL@0x0 0x402000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x100000 - SI_GBE(PRESERVE)@0x101000 0x2000 - SI_ME@0x103000 0x2f9000 - SI_PDR(PRESERVE)@0x3fc000 0x4000 + SI_ME@0x101000 0x2fd000 + SI_PDR(PRESERVE)@0x3fe000 0x4000 } - SI_BIOS@0x400000 0x1c00000 { - RW_DIAG@0x0 0x12d0000 { - RW_LEGACY(CBFS)@0x0 0x12c0000 - DIAG_NVRAM@0x12c0000 0x10000 + SI_BIOS@0x402000 0x1bfe000 { + RW_DIAG@0x0 0x12ce000 { + RW_LEGACY(CBFS)@0x0 0x12be000 + DIAG_NVRAM@0x12be000 0x10000 } - RW_SECTION_A@0x12d0000 0x280000 { + RW_SECTION_A@0x12ce000 0x280000 { VBLOCK_A@0x0 0x10000 FW_MAIN_A(CBFS)@0x10000 0x26ffc0 RW_FWID_A@0x27ffc0 0x40 } - RW_SECTION_B@0x1550000 0x280000 { + RW_SECTION_B@0x154e000 0x280000 { VBLOCK_B@0x0 0x10000 FW_MAIN_B(CBFS)@0x10000 0x26ffc0 RW_FWID_B@0x27ffc0 0x40 } - RW_MISC@0x17d0000 0x30000 { + RW_MISC@0x17ce000 0x30000 { UNIFIED_MRC_CACHE@0x0 0x20000 { RECOVERY_MRC_CACHE@0x0 0x10000 RW_MRC_CACHE@0x10000 0x10000 @@ -34,7 +33,7 @@ RW_VPD(PRESERVE)@0x28000 0x2000 RW_NVRAM(PRESERVE)@0x2a000 0x6000 } - WP_RO@0x1800000 0x400000 { + WP_RO@0x17fe000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_UNUSED@0x4000 0xc000 RO_SECTION@0x10000 0x3f0000 { -- To view, visit https://review.coreboot.org/c/coreboot/+/35129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38659460726a3f647cda3bc3efd442f18aea24f0 Gerrit-Change-Number: 35129 Gerrit-PatchSet: 1 Gerrit-Owner: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/drallion: Correct drallion HWID and add HWID for variants
by Mathew King (Code Review) 29 Aug '19

29 Aug '19

Mathew King has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35104 ) Change subject: mb/google/drallion: Correct drallion HWID and add HWID for variants ...................................................................... mb/google/drallion: Correct drallion HWID and add HWID for variants The current HWID for drallion is reported as invalid by chrome, generate new valid HWID with the following command and taking last 4 digits. `printf "%d\n" 0x$(crc32 <(echo -n '$1'))` BUG=b:140013681 Change-Id: I410d37fc3f3372e9420d674b65f2c9a704b670f2 Signed-off-by: Mathew King <mathewk(a)chromium.org> --- M src/mainboard/google/drallion/Kconfig 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/35104/1 diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig index cff56a4..076d3e2 100644 --- a/src/mainboard/google/drallion/Kconfig +++ b/src/mainboard/google/drallion/Kconfig @@ -64,7 +64,10 @@ config GBB_HWID string depends on CHROMEOS - default "DRALLION TEST 3556" + default "ARCADA_CML TEST 4940" if BOARD_GOOGLE_ARCADA_CML + default "SARIEN_CML TEST 2073" if BOARD_GOOGLE_SARIEN_CML + default "DRALLION TEST 4932" if BOARD_GOOGLE_DRALLION + config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/35104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I410d37fc3f3372e9420d674b65f2c9a704b670f2 Gerrit-Change-Number: 35104 Gerrit-PatchSet: 1 Gerrit-Owner: Mathew King <mathewk(a)chromium.org> Gerrit-MessageType: newchange

4 9

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2019